micheleandClaude Sonnet 5
835ae881dc
n2_system_ddr3_top.v: the first synthesizable top wiring the real mig_7series_0 DDR3 controller (public wrapper, real calibration) + mig_native_adapter.v + sdram_arbiter_n.v (3-way: 2 packed_slot + host raw-access) + neural_director_packed.v + spi_host_bridge_v3.v. Real Vivado in-context synth+impl against the actual MIG-generated XDC (pin locations, DDR3 timing exceptions) on xc7a100tcsg324-2: route_design 100%, all timing constraints met (WNS +0.040ns, WHS +0.048ns, 0 failing endpoints), 310.078MHz DDR3 PHY clock / 155.039MHz compute domain, 5140 LUTs / 5952 regs / 16 DSP48E1 / 0 BRAM. Fixed three real issues found getting here: a SystemVerilog literal synth_design can't parse, MIG stub port mismatch (calib_tap_* isn't exposed in this IP config), and a genuine design mistake -- exposing packed_slot.v's activation-fetch stand-in ports as literal top-level pins demanded ~360 I/O against the package's 324 total. Made that interface internal (stub-driven) instead. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC