micheleandClaude Sonnet 5
7e2711fa27
Bumps ADDR_WIDTH's default from 22 to 23 bits across every RTL module (neuron_memory, layer_sequencer, spi_engine, spi_neuron_top, mem_arbiter, int8_memory_access, memory_interface, psram_controller, memory_model) and every testbench that mirrors it, so the system's byte-address space reaches the full 8 MiB the recommended PSRAM part (ISSI IS66WVE4M16EBLL-70BLI, docs/FPGA-Neural-Hardware-Design.md §3) actually provides -- previously only 4 MiB (half the chip) was reachable, since int8_memory_access.v's byte->word address shift (addr >> 1) turned the old 22-bit byte address into only 21 real word bits, one short of the chip's real 22-bit word address (A0-A21). At 23 bits, that same shift lands exactly on all 22 chip address lines, so the whole part is usable now instead of deferred to a future widening. Also fixes a stray 22'd11-sized literal in layer_sequencer.v's descriptor-table address increment (numerically already safe via Verilog's zero-extension, but now correctly unsized so it always matches ADDR_WIDTH instead of silently assuming 22). Updated docs/FPGA-NeuralNetwork-Engine.md's SPI protocol address-field note (23 bits, top 1 reserved bit instead of 2) and docs/FPGA-Neural-Hardware-Design.md's PSRAM section (the "chip has one spare address line" framing is gone now that all 22 are wired and used). Full regression (all 11 ADDR_WIDTH-touching testbenches, plus a Yosys elaboration check of spi_neuron_top with the new default and no override) passes clean. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
357 lines
12 KiB
Verilog
357 lines
12 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// SPI_NEURON_TOP
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//
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// Full Phase 3 + Phase 4 integration: SPI host interface (spi_slave
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// + spi_engine, docs §8.1) driving neuron_memory.v (Phase 3,
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// N_NEURONS>=1) through a shared PSRAM (memory_interface +
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// psram_controller), arbitrated between spi_engine's own RAM access
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// (WRITE_RAM/READ_RAM opcodes) and neuron_memory's own X/W/bias
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// reads during a run.
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//
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// neuron_memory's own `rst` is the global reset OR'd with the
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// RESET opcode's soft-reset pulse from spi_engine, so a host can
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// recover the compute engine over SPI without a physical reset
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// (RAM contents are untouched either way).
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// ================================================================
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module spi_neuron_top #(
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parameter ADDR_WIDTH = 23,
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parameter DATA_WIDTH = 8,
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parameter N_INPUTS = 32,
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parameter N_NEURONS = 1,
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parameter PARALLEL = 8,
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parameter ACC_WIDTH = 32,
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parameter MEM_DATA_WIDTH = 16,
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parameter CLK_FREQ_MHZ = 80,
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parameter N_LAYERS = 4 // Phase 5: RUN_NETWORK, requires N_INPUTS==N_NEURONS
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)(
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input wire clk,
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input wire rst,
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// ------------------------------------------------------------
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// SPI host interface
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// ------------------------------------------------------------
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input wire sclk,
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input wire mosi,
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output wire miso,
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input wire cs_n,
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// ------------------------------------------------------------
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// PSRAM physical interface
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// ------------------------------------------------------------
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output wire [ADDR_WIDTH-1:0] psram_a,
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inout wire [MEM_DATA_WIDTH-1:0] psram_dq,
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output wire psram_ce_n,
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output wire psram_oe_n,
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output wire psram_we_n,
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output wire psram_lb_n,
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output wire psram_ub_n,
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output wire psram_zz_n
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);
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// ============================================================
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// SPI PHYSICAL LAYER
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// ============================================================
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wire [7:0] rx_byte;
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wire rx_valid;
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wire cs_start;
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wire cs_end;
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wire [7:0] tx_byte;
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wire tx_byte_req;
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spi_slave u_spi_slave (
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.clk(clk), .rst(rst),
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.sclk(sclk), .mosi(mosi), .miso(miso), .cs_n(cs_n),
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.rx_byte(rx_byte), .rx_valid(rx_valid),
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.tx_byte(tx_byte), .tx_byte_req(tx_byte_req),
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.cs_active(), .cs_start(cs_start), .cs_end(cs_end)
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);
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// ============================================================
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// SPI PROTOCOL ENGINE
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// ============================================================
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wire spi_ram_req;
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wire spi_ram_wr;
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wire [ADDR_WIDTH-1:0] spi_ram_addr;
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wire signed [7:0] spi_ram_wdata;
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wire signed [7:0] spi_ram_rdata;
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wire spi_ram_ready;
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wire [ADDR_WIDTH-1:0] x_base;
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wire [ADDR_WIDTH-1:0] w_base;
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wire [ADDR_WIDTH-1:0] bias_addr;
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wire [1:0] activation;
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wire [15:0] n_inputs_real;
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wire [15:0] n_neurons_real;
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wire nm_start;
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wire nm_busy;
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wire nm_done;
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wire signed [DATA_WIDTH*N_NEURONS-1:0] y_bus;
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wire nm_soft_rst;
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// Phase 5: layer_sequencer control/status, driven by spi_engine's
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// RUN_NETWORK opcode.
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wire [ADDR_WIDTH-1:0] table_base;
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wire [ADDR_WIDTH-1:0] buf_a_base;
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wire [ADDR_WIDTH-1:0] buf_b_base;
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wire run_start;
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wire [7:0] run_num_layers;
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wire seq_busy;
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wire seq_done;
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spi_engine #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.N_INPUTS(N_INPUTS),
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.N_NEURONS(N_NEURONS),
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.PARALLEL(PARALLEL)
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) u_spi_engine (
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.clk(clk), .rst(rst),
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.rx_byte(rx_byte), .rx_valid(rx_valid),
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.cs_start(cs_start), .cs_end(cs_end),
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.tx_byte(tx_byte), .tx_byte_req(tx_byte_req),
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.ram_req(spi_ram_req), .ram_wr(spi_ram_wr),
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.ram_addr(spi_ram_addr), .ram_wdata(spi_ram_wdata),
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.ram_rdata(spi_ram_rdata), .ram_ready(spi_ram_ready),
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.x_base(x_base), .w_base(w_base), .bias_addr(bias_addr),
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.activation(activation),
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.n_inputs_real(n_inputs_real), .n_neurons_real(n_neurons_real),
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.nm_start(nm_start), .nm_busy(nm_busy), .nm_done(nm_done),
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.y_bus(y_bus),
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.nm_soft_rst(nm_soft_rst),
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.table_base(table_base), .buf_a_base(buf_a_base), .buf_b_base(buf_b_base),
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.run_start(run_start), .run_num_layers(run_num_layers),
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.seq_busy(seq_busy), .seq_done(seq_done)
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);
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// ============================================================
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// LAYER SEQUENCER (Phase 5: RUN_NETWORK)
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//
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// Requires N_INPUTS == N_NEURONS (both equal N_WIDTH below) --
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// see rtl/layer_sequencer.v header for why. neuron_memory is
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// shared with the legacy single-layer path: the two mux_nm_*
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// wires below select which master drives it, based on seq_busy.
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// ============================================================
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wire [ADDR_WIDTH-1:0] seq_nm_x_base;
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wire [ADDR_WIDTH-1:0] seq_nm_w_base;
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wire [ADDR_WIDTH-1:0] seq_nm_bias_addr;
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wire [1:0] seq_nm_activation;
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wire [15:0] seq_nm_n_inputs;
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wire [15:0] seq_nm_n_neurons;
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wire seq_nm_start;
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wire seq_ram_req;
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wire seq_ram_wr;
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wire [ADDR_WIDTH-1:0] seq_ram_addr;
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wire signed [7:0] seq_ram_wdata;
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wire signed [7:0] seq_ram_rdata;
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wire seq_ram_ready;
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layer_sequencer #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.N_WIDTH(N_NEURONS),
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.N_LAYERS(N_LAYERS)
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) u_layer_sequencer (
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.clk(clk), .rst(rst),
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.run_start(run_start), .run_num_layers(run_num_layers),
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.seq_busy(seq_busy), .seq_done(seq_done),
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.x_base(x_base), .table_base(table_base),
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.buf_a_base(buf_a_base), .buf_b_base(buf_b_base),
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.nm_x_base(seq_nm_x_base), .nm_w_base(seq_nm_w_base),
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.nm_bias_addr(seq_nm_bias_addr), .nm_activation(seq_nm_activation),
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.nm_n_inputs(seq_nm_n_inputs), .nm_n_neurons(seq_nm_n_neurons),
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.nm_start(seq_nm_start),
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.nm_busy(nm_busy), .nm_done(nm_done),
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.y_bus(y_bus),
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.ram_req(seq_ram_req), .ram_wr(seq_ram_wr),
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.ram_addr(seq_ram_addr), .ram_wdata(seq_ram_wdata),
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.ram_rdata(seq_ram_rdata), .ram_ready(seq_ram_ready)
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);
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// neuron_memory master mux: the sequencer owns it for the whole
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// duration of a RUN_NETWORK job (seq_busy), otherwise spi_engine
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// drives it directly (legacy single-layer SET_BASE/START path).
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wire [ADDR_WIDTH-1:0] mux_nm_x_base = seq_busy ? seq_nm_x_base : x_base;
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wire [ADDR_WIDTH-1:0] mux_nm_w_base = seq_busy ? seq_nm_w_base : w_base;
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wire [ADDR_WIDTH-1:0] mux_nm_bias_addr = seq_busy ? seq_nm_bias_addr : bias_addr;
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wire [1:0] mux_nm_activation = seq_busy ? seq_nm_activation : activation;
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wire [15:0] mux_nm_n_inputs = seq_busy ? seq_nm_n_inputs : n_inputs_real;
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wire [15:0] mux_nm_n_neurons = seq_busy ? seq_nm_n_neurons : n_neurons_real;
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wire mux_nm_start = seq_busy ? seq_nm_start : nm_start;
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// ============================================================
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// NEURON MEMORY
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//
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// rst is the global reset OR'd with the SPI RESET opcode pulse.
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// ============================================================
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wire nm_rst = rst | nm_soft_rst;
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wire nm_ram_req;
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wire nm_ram_wr;
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wire [ADDR_WIDTH-1:0] nm_ram_addr;
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wire signed [7:0] nm_ram_wdata;
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wire signed [7:0] nm_ram_rdata;
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wire nm_ram_ready;
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neuron_memory #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.N_INPUTS(N_INPUTS),
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.N_NEURONS(N_NEURONS),
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.PARALLEL(PARALLEL),
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.ACC_WIDTH(ACC_WIDTH)
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) u_neuron_memory (
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.clk(clk), .rst(nm_rst),
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.start(mux_nm_start),
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.mem_req(nm_ram_req), .mem_wr(nm_ram_wr),
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.mem_addr(nm_ram_addr), .mem_wdata(nm_ram_wdata),
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.mem_rdata(nm_ram_rdata), .mem_ready(nm_ram_ready),
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.x_base(mux_nm_x_base), .w_base(mux_nm_w_base), .bias_addr(mux_nm_bias_addr),
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.activation(mux_nm_activation),
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.n_inputs_real(mux_nm_n_inputs), .n_neurons_real(mux_nm_n_neurons),
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.y_bus(y_bus), .busy(nm_busy), .done(nm_done)
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);
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// ============================================================
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// SHARED MEMORY ARBITER
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// ============================================================
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wire arb_req;
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wire arb_wr;
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wire [ADDR_WIDTH-1:0] arb_addr;
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wire signed [7:0] arb_wdata;
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wire signed [7:0] arb_rdata;
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wire arb_ready;
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mem_arbiter #(
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.ADDR_WIDTH(ADDR_WIDTH)
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) u_arbiter (
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.clk(clk), .rst(rst),
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.a_req(spi_ram_req), .a_wr(spi_ram_wr),
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.a_addr(spi_ram_addr), .a_wdata(spi_ram_wdata),
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.a_rdata(spi_ram_rdata), .a_ready(spi_ram_ready),
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.b_req(nm_ram_req), .b_wr(nm_ram_wr),
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.b_addr(nm_ram_addr), .b_wdata(nm_ram_wdata),
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.b_rdata(nm_ram_rdata), .b_ready(nm_ram_ready),
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.c_req(seq_ram_req), .c_wr(seq_ram_wr),
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.c_addr(seq_ram_addr), .c_wdata(seq_ram_wdata),
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.c_rdata(seq_ram_rdata), .c_ready(seq_ram_ready),
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.m_req(arb_req), .m_wr(arb_wr),
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.m_addr(arb_addr), .m_wdata(arb_wdata),
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.m_rdata(arb_rdata), .m_ready(arb_ready)
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);
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// ============================================================
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// BYTE <-> WORD BRIDGE (shared, single instance)
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// ============================================================
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wire i8_mem_req;
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wire i8_mem_wr;
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wire [ADDR_WIDTH-1:0] i8_mem_addr;
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wire [MEM_DATA_WIDTH-1:0] i8_mem_wdata;
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wire i8_mem_lb_n;
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wire i8_mem_ub_n;
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wire [MEM_DATA_WIDTH-1:0] i8_mem_rdata;
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wire i8_mem_ready;
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int8_memory_access #(
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.ADDR_WIDTH(ADDR_WIDTH)
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) u_int8_access (
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.clk(clk), .rst(rst),
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.req(arb_req), .wr(arb_wr), .addr(arb_addr), .wdata(arb_wdata),
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.rdata(arb_rdata), .ready(arb_ready),
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.mem_req(i8_mem_req), .mem_wr(i8_mem_wr),
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.mem_addr(i8_mem_addr), .mem_wdata(i8_mem_wdata),
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.mem_lb_n(i8_mem_lb_n), .mem_ub_n(i8_mem_ub_n),
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.mem_rdata(i8_mem_rdata), .mem_ready(i8_mem_ready)
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);
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// ============================================================
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// MEMORY INTERFACE / PSRAM CONTROLLER
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// ============================================================
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wire [MEM_DATA_WIDTH-1:0] psram_mem_rdata;
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wire psram_mem_ready;
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wire psram_mem_req;
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wire psram_mem_wr;
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wire [ADDR_WIDTH-1:0] psram_mem_addr;
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wire [MEM_DATA_WIDTH-1:0] psram_mem_wdata;
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wire psram_mem_lb_n;
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wire psram_mem_ub_n;
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memory_interface #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(MEM_DATA_WIDTH)
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) u_memory_if (
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.clk(clk), .rst(rst),
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.req(i8_mem_req), .wr(i8_mem_wr), .addr(i8_mem_addr), .wdata(i8_mem_wdata),
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.lb_n(i8_mem_lb_n), .ub_n(i8_mem_ub_n),
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.rdata(i8_mem_rdata), .ready(i8_mem_ready),
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.mem_req(psram_mem_req), .mem_wr(psram_mem_wr),
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.mem_addr(psram_mem_addr), .mem_wdata(psram_mem_wdata),
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.mem_lb_n(psram_mem_lb_n), .mem_ub_n(psram_mem_ub_n),
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.mem_rdata(psram_mem_rdata), .mem_ready(psram_mem_ready)
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);
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psram_controller #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(MEM_DATA_WIDTH),
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ)
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) u_psram_ctrl (
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.clk(clk), .rst(rst),
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.mem_req(psram_mem_req), .mem_wr(psram_mem_wr),
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.mem_addr(psram_mem_addr), .mem_wdata(psram_mem_wdata),
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.mem_lb_n(psram_mem_lb_n), .mem_ub_n(psram_mem_ub_n),
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.mem_rdata(psram_mem_rdata), .mem_ready(psram_mem_ready),
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.psram_a(psram_a), .psram_dq(psram_dq),
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.psram_ce_n(psram_ce_n), .psram_oe_n(psram_oe_n), .psram_we_n(psram_we_n),
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.psram_lb_n(psram_lb_n), .psram_ub_n(psram_ub_n), .psram_zz_n(psram_zz_n)
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);
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endmodule
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