micheleandClaude Sonnet 5
0303aacb9f
N=2 re-verified with the same shared pipelined neural_processor_packed.v (EXP-0097's fix): real functional xsim 8/8 PASS (identical completion time to the pre-fix baseline), real full P&R WNS=+0.389ns (up from +0.099962ns), 0 failing endpoints, 16 DSP48E1 -- no regression. Real, consolidated family state, all sharing the same pipelined core: N=2: WNS=+0.389ns, 16 DSP48E1, 8/8 functional PASS N=8: WNS=+0.108ns, 64 DSP48E1, 16/16 functional PASS N=16: WNS=+0.269ns, 128 DSP48E1, 32/32 functional PASS Updated the project's own primary real docs (docs/PHYSICAL_REALIZATION.md S3, docs/ARCHITECTURE_ANALYSIS.md S5.6) to the same depth EXP-0096 gave N=8 alone -- not just the docs/latex/ deliverables. Clear two-track framing throughout: the physically fabricated board still uses N=8's original, unmodified core (WNS=0.000ns exact); this consolidated, improved family lives on the isolated n16-timing-closure branch, pending a real hardware decision on whether/when to adopt it. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
Formato dei log V2
Regola non negoziabile (docs/v2-description.md §25-29): ogni attività
significativa (modifica, simulazione, sintesi, benchmark, decisione, errore)
deve essere registrata. Nessun log viene mai sovrascritto o troncato — solo
append. Nessun ID esperimento (EXP-XXXX) o decisione (DEC-XXXX) viene mai
riutilizzato, anche se il risultato è un FAIL.
File
development.log— log principale di sviluppo, un'entry per ogni sessione di lavoro/milestone (creazione file, refactor, avanzamento roadmap).architecture.log— decisioni e note di architettura a grana fine (non scelte finali — quelle vanno indecisions.log— ma esplorazioni, alternative considerate, vincoli scoperti).simulation.log— ogni run di simulazione (Icarus/Verilator): test, vettori, cicli, PASS/FAIL, confronto bit-exact con V1, stall/memory-wait.synthesis.log— ogni run Yosys: LUT/FF/DSP/BRAM, warning, problemi CHECK.timing.log— ogni run nextpnr-ecp5: Fmax, percorso critico, WNS/TNS se disponibili. Fmax "ufficiale" di una configurazione = solo da qui, mai da simulazione o stima.benchmark.log— tabelle di confronto per configurazione (Fmax, MAC/cycle, cycles/neuron, utilization, ecc.), sempre con etichetta THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R.decisions.log— decisioni architetturali importanti, formatoDEC-XXXX(vedidocs/v2-description.md§27).experiments.log— registro principale, unEXP-XXXXper ogni esperimento end-to-end (config → sim/synth/timing → risultato), rimanda areports/experiments/EXP-XXXX/.errors.log— errori/bug/regressioni incontrati durante lo sviluppo V2 stesso (non i bug V1, già chiusi inhardware/v1/docs/validation/bugs.md).
Campi minimi per entry (§26)
timestamp, experiment_id (se applicabile), git_commit, session/agent,
module, configuration, action, reason, command, result, errors, decision,
next_action
Per synthesis/timing aggiungere: LUT, FF, DSP, BRAM, Fmax, critical path, WNS/TNS. Per simulazione: test, vectors, cycles, PASS/FAIL, bit-exact result, stall cycles, memory wait, utilization.