micheleandClaude Sonnet 5
77baa8fc16
dataflow_core.v integrates dependency_manager (M6) -> neural_director (M5) -> N_SLOTS x (memory_manager (M4) + neural_processor (M1)) for the first time. A slot's completion (via neural_director's new slot_node_id tracking, an additive port) feeds back as a producer_done event to dependency_manager, waking up any node that depended on it - closing the dataflow loop without external glue. Verified end-to-end (Verilator) on a 3-node DAG: two independent nodes plus a third depending on both, confirmed to dispatch only after both genuinely complete via real neural_processor computation. 4/4 PASS. Real synthesis + nextpnr-ecp5 P&R via a synthesis-only timing harness (bare per-slot backend ports exceed the LFE5U-45F's TRELLIS_IO budget, same pattern as ERR-0005): N_SLOTS=2 -> 165.15 MHz, N_SLOTS=4 -> 133.19 MHz, both PASS at 80MHz, 0 synthesis problems. Scope explicitly deferred to M8 (DEC-0009): M3's BRAM buffers not wired in yet, per-slot Memory Backend Interface ports not arbitrated to one shared PSRAM master yet - both need real measured data before committing to a design, not guessed at here. Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0009)/ experiments (EXP-0008)/errors (ERR-0007, a Yosys chparam-ordering build quirk, not an RTL bug)/development.log, ROADMAP.md updated. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
67 lines
3.6 KiB
Markdown
67 lines
3.6 KiB
Markdown
# FPGA-Neural V2 — stato roadmap
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Fonte del mandato: `docs/v2-description.md` (root del repository). Baseline
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funzionale/numerica/bit-exact: `hardware/v1/` (frozen, sola lettura — vedi
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`hardware/v1/README.md`).
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Legenda: `[ ]` non iniziato · `[~]` in corso · `[x]` completo (sim+synth+timing
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reali, non solo scritto).
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- [x] **M1 — Neural Processor** (`hardware/v2/rtl/neural_processor.v`, P8).
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Bit-exact vs V1 (7/7 test, Verilator), pipeline a 8 stadi
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funzionante, throughput reale (1 tile/ciclo). Sintesi reale: 0
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problemi CHECK, Fmax 183.12 MHz (ACC_WIDTH=32) — vedi
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`logs/experiments.log` EXP-0001/EXP-0002, `logs/errors.log` per 3
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bug reali trovati e risolti (2 del toolchain Icarus, 1 RTL).
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- [x] **M2 — Processor Array** (`neural_processor_array.v`). 1/2/4/8
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processor testati (sim concorrenza reale + sintesi/P&R reali).
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Fmax sempre PASS a 80MHz (159.11→134.70 MHz). Scoperta: il DSP
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(MULT18X18D), non LUT/FF, satura per primo (88% a N=8) — vedi
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`logs/decisions.log` DEC-0005.
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- [x] **M3 — Buffers** (`activation_buffer.v`, `weight_buffer.v`,
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`result_buffer.v`). Tutti inferiscono DP16KD reale (10/10 test,
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6/6 config sintetizzate 0 problemi). Scoperta: il costo BRAM di
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weight_buffer e' guidato da P_IN (larghezza), non da DEPTH.
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- [x] **M4 — Memory Manager** (`memory_manager.v`, `prefetch_engine.v`),
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backend PSRAM V1 riusato SENZA MODIFICHE. End-to-end reale (3/3
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job PASS) con vero neural_processor + vera catena PSRAM V1.
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3 bug RTL trovati/risolti (`logs/errors.log` ERR-0006). Fmax
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165.86 MHz.
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- [x] **M5 — Neural Director** (`neural_director.v`), scheduling
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first-free. 4/4 test PASS (dispatch + coda + backpressure reale
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su N_SLOTS=2). FSM ridotta a 4 stati, dependency rimandata a M6
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(`logs/decisions.log` DEC-0007). Fmax 250.50 MHz.
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- [x] **M6 — Dependency Manager** (`dependency_manager.v`), ready/waiting
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queue, dependency counters, wake-up, producer tracking. 4/4 test
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PASS (dipendenze multiple + produttore condiviso/piu' consumer).
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Fmax 155.30 MHz. Forwarding di valori e riuso slot rimandati
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(`logs/decisions.log` DEC-0008).
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- [x] **M7 — Dataflow Core** (`dataflow_core.v`), prima integrazione
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completa: Dependency Manager (M6) -> Neural Director (M5) ->
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N_SLOTS x (Memory Manager (M4) + Neural Processor (M1)), loop di
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wake-up chiuso end-to-end. 4/4 test PASS su un DAG a 3 nodi (node2
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dipende da entrambi node0+node1, dispatch confermato solo dopo che
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ENTRAMBI completano davvero). Sintesi reale 0 problemi a
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N_SLOTS=2 e N_SLOTS=4. Fmax reale (harness): 165.15 MHz
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(N_SLOTS=2), 133.19 MHz (N_SLOTS=4). Buffer M3 e arbitraggio PSRAM
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condiviso rimandati esplicitamente a M8 (`logs/decisions.log`
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DEC-0009).
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- [ ] **M8 — PSRAM integration**, controller V1 non modificato, misura reale.
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- [ ] **M9 — Full benchmark**, tabella V1 vs V2 (§32 del mandato).
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- [ ] **M10 — Optimization**, solo sulla base dei dati raccolti in M1-M9.
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## Log
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Vedi `hardware/v2/logs/` (`development.log` per la cronologia di sessione,
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`decisions.log` per le decisioni architetturali con motivazione,
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`experiments.log` per ogni EXP-XXXX end-to-end).
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## Regole non negoziabili attive (§34 del mandato, per riferimento rapido)
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1. V1 (`hardware/v1/`) rimane intatta — mai modificata.
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2. V2 vive esclusivamente sotto `hardware/v2/`.
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3. Nessun risultato inventato: THEORETICAL vs SIMULATED vs SYNTHESIZED vs
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POST-P&R sempre etichettati esplicitamente.
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4. Ogni modifica/esperimento/decisione registrata nei log, mai persa.
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5. Ogni esperimento ha un ID univoco, mai riutilizzato — anche i FAIL restano.
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