micheleandClaude Sonnet 5
6a46dc857f
DEC-0043: slot_mem_arbiter.v/slot_mem_arbiter_wide.v both still had the exact runtime-variable-indexed part-select anti-pattern (pending_addr[grant_idx*ADDR_WIDTH +: ADDR_WIDTH], grant_idx a runtime register) that neural_director.v had already found and fixed once before -- ADDR_WIDTH=26 not being a power of 2 means this synthesizes as a real multiplier + wide crossbar, sitting right on the arbiter<->backend boundary this project's own N=8 congestion diagnosis names, growing with N_PORTS=N_SLOTS(+1). Also fixed the cheaper but same-class dir_job_out_slot*16 mux in nms_dataflow_core_sdram.v, feeding directly into dependency_manager -- this exact signal was DEC-0042's own diagnosed N=4 critical path. Fix: N_PORTS/N_SLOTS parallel constant-indexed comparisons (unrolled for-loop) instead of a runtime-indexed read -- same technique already proven in neural_director.v. Purely an internal-implementation change. Verified bit-exact via Verilator: tb_fpga_neural_v2_top_smoke.v 11/11 PASS; tb_nms_dstress_sdram_unified.v (256-neuron stress) at both N_SLOTS_CFG=4 and =8, 256/256 bit-exact vs golden, total_cycles IDENTICAL to pre-fix historical values (49927/49909, exact match to DEC-0042's own recorded numbers). Bonus finding from the same D-Stress run (not this commit's main point, logged for Phase 3/4): sdram_busy_cycles ~81.6% and useful-MAC-cycle fraction HALVING from N=4 to N=8 (2.04%->1.02%) -- real existing evidence the system is memory-bound on a single SDRAM bank well before N=8, independent of Fmax. Re-synthesis (8-seed sweep, N=4/N=8) in progress to measure the actual Fmax delta from this fix -- committed separately once complete. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
207 lines
11 KiB
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207 lines
11 KiB
Plaintext
# V2 simulation log -- solo append, mai troncato/sovrascritto (vedi README.md)
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# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
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[2026-09-05] EXP-0001/EXP-0002 -- hardware/v2/sim/tb_neural_processor.v
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test: 7 cases (16/32/8/8/8/8/64-input jobs; ACT_NONE + ACT_RELU;
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extreme INT8 saturation; back-to-back zero-idle-gap tiles)
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vectors: regular positive, mixed-sign cancellation, extreme INT8
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(-128,-127,-1,0,1,126,127,127 in one 8-lane tile), back-to-back
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jobs, 8-tile (64-input) job
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simulator: Verilator 5.050 (--binary --timing) -- see decisions.log
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DEC-0004 for why Icarus v13.0 is not trusted for this testbench
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cycles: not separately profiled at this milestone (throughput/stall
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cycle counting deferred to M9 per §22)
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PASS/FAIL: 7/7 PASS (ACC_WIDTH=32); 7/7 PASS (ACC_WIDTH=24, EXP-0002)
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bit-exact result: V1.y === V2.result_data for every case, both widths
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stall cycles / memory wait / utilization: N/A (no Memory Manager yet,
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M1 operands fed directly by testbench per the roadmap)
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[2026-09-05] EXP-0003 -- hardware/v2/sim/tb_neural_processor_array.v
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(N_PROCESSORS=4)
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test: 7 cases (single-processor sanity; 4-way same-cycle concurrent
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launch with different tile counts; staggered-start 2-processor test)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 7/7 PASS
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bit-exact result: N/A at this milestone (hand-computed expected
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values, arithmetic itself already bit-exact-certified vs V1 at M1)
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concurrency: confirmed genuine -- in the staggered test, the
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later-launched, shorter job (processor 1) completes BEFORE the
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earlier-launched, longer job (processor 0), proving independent
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progress rather than serialization.
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[2026-09-05] EXP-0004 -- hardware/v2/sim/tb_buffers.v
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test: 10 cases across activation_buffer/weight_buffer/result_buffer
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vectors: extreme INT8 (-128, 127, -100, 100), regular values, full
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64-bit tile round-trip (weight_buffer), re-reads confirming earlier
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writes undisturbed
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 10/10 PASS
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[2026-09-05] EXP-0005 -- hardware/v2/sim/tb_memory_manager.v
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test: 3 end-to-end jobs (3-tile/saturating, 1-tile/non-saturating,
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5-tile/steady-state-swap), real V1 PSRAM backend chain (unmodified),
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real M1 neural_processor
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 3/3 PASS
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bit-exact result: PSRAM-read-back result byte matches hand-computed
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expectation in every case (independent oracle, not derived from the
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RTL under test)
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cycles: 446 (3 tiles), 166 (1 tile), 728 (5 tiles) -- real PSRAM
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latency dominates, not memory_manager's own control overhead
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[2026-09-05] EXP-0006 -- hardware/v2/sim/tb_neural_director.v
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test: 4 cases (3-jobs-2-slots first-free dispatch + queueing,
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backpressure fill/recover)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS
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[2026-09-05] EXP-0007 -- hardware/v2/sim/tb_dependency_manager.v
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test: 4 cases on a 4-node DAG (2 independent + 1 dual-dependency +
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1 single-dependency-shared-producer)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS
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[2026-09-05] EXP-0008 -- hardware/v2/sim/tb_dataflow_core.v
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test: full end-to-end M1-M6 integration through dataflow_core.v (M7),
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a 3-node DAG (node0/node1 independent, node2 depends on BOTH) run
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through the REAL dependency_manager -> neural_director -> N_SLOTS x
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(memory_manager + neural_processor) chain for the first time, each
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slot backed by its own independent behavioral byte memory
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS -- node0=48, node1=8 (both real neural_processor
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computations via the full stack), node2=40 dispatched only after
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BOTH node0 and node1 genuinely completed (continuously polled every
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cycle up to completion, not just checked at the end) -- the
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dependency-manager-to-director wake-up loop closes correctly
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end-to-end with real hardware in between, not just in isolation
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(M6's own testbench already proved the wake-up logic alone)
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[2026-09-05] EXP-0009 -- hardware/v2/sim/tb_neural_multiprocessor.v
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test: same 3-node DAG as EXP-0008 (node0/node1 independent, node2
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depends on both), routed through neural_multiprocessor.v (M8): the
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REAL, UNMODIFIED V1 PSRAM backend chain (int8_memory_access ->
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memory_interface -> psram_controller -> psram_model) shared across
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N_SLOTS=2 genuinely concurrent memory_manager instances via the new
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slot_mem_arbiter.v -- node0 and node1 are registered back-to-back
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with no dependencies, so both dispatch to their slots essentially
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simultaneously and genuinely contend for the one real PSRAM port.
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS after fixing a real dropped-request bug in the
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first arbiter draft (errors.log ERR-0008) -- node0=48, node1=8
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(concurrent, real PSRAM, real arbitration), node2=40 dispatched only
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after both genuinely completed. 444 cycles end-to-end (vs 20000-cycle
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watchdog timeout with the buggy first draft, where node1's request
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was silently dropped and its slot hung forever).
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regression: hardware/v2/sim/tb_memory_manager.v (M4) re-run unchanged
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(no M4 file touched) -- still 3/3 PASS, identical cycle counts
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(446/166/728), confirming slot_mem_arbiter.v is purely additive.
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[2026-09-05] EXP-0013 -- hardware/v2/sim/tb_neural_multiprocessor.v,
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M10 cycle-accounting instrumentation (closes decisions.log DEC-0011's
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deferred stall %/utilization gap with real data, testbench-only
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addition, no RTL touched)
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test: same EXP-0009 scenario (3-node DAG, N_SLOTS=2, real V1 PSRAM
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chain, real slot_mem_arbiter contention), instrumented with cycle
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counters (shared PSRAM port busy cycles via
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u_nmp.u_arbiter.owner!=0, each slot's memory_manager busy cycles via
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its own state!=MM_IDLE), measured from the first node registration
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to test completion.
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS (unchanged from EXP-0009), plus real measured
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data: 684 total cycles measured; shared PSRAM port busy 559/684
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(81.7% utilization, 18.3% idle); slot 0 (memory_manager) busy
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651/684 (95.2%); slot 1 (memory_manager) busy 446/684 (65.2%).
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note: slot 0's higher utilization is at least partly explained by it
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serving TWO sequential jobs in this run (node0, then whichever slot
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frees first serves node2 -- likely slot 0, first-free/lowest-index)
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while slot 1 only ever serves node1 -- NOT conclusive evidence of
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harmful priority starvation on its own; see decisions.log DEC-0010's
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original fairness deferral, now informed by this real (if small)
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data point.
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[2026-09-05] EXP-0014 -- hardware/v2/sim/tb_benchmark_suite.v (final
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benchmark campaign, post-M10)
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test: 6 workloads (16/64/128/256 independent neurons + 10-node
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multilayer with random data + 6-node 2-hop DAG), each bit-exact
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verified against a software golden model, at N_SLOTS=1/2/4/8 (24
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total runs) through the real full neural_multiprocessor.v (real V1
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PSRAM chain, real slot_mem_arbiter)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 24/24 PASS bit-exact (11,520 individual neuron/node
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comparisons, zero mismatches) after fixing 3 real issues found
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during this campaign (errors.log ERR-0009: 1 real RTL bug in
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neural_director.v at N_SLOTS=1, never exercised before; 2 testbench
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sizing bugs -- psram_model DEPTH too small, N_NODES too small
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causing a real node-id wraparound deadlock)
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full data/analysis: hardware/v2/docs/benchmarks/final-benchmark.md
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[2026-09-05] EXP-0015 -- regression + real improvement measurement
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after word-level burst-read rewrite (DEC-0015)
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test: hardware/v2/sim/tb_memory_manager.v (M4, updated to connect
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memory_manager directly to memory_interface.v, skipping
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int8_memory_access.v), hardware/v2/sim/tb_dataflow_core.v (M7,
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sim_byte_mem -> sim_word_mem), hardware/v2/sim/tb_neural_multiprocessor.v
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(M8, UNCHANGED -- black-box on neural_multiprocessor.v, no edits
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needed), hardware/v2/sim/tb_benchmark_suite.v (final campaign,
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UNCHANGED, re-run at N_SLOTS=1/2/4/8)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: M4 3/3 PASS (166/446/728 -> 84/204/322 cycles, bit-exact).
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M7 4/4 PASS (wd=67->43 cycles to first dependency check). M8 4/4
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PASS (684->337 cycles). Final campaign 24/24 PASS bit-exact,
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D-Stress cycles roughly halved to a bit more at every N_SLOTS
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(see benchmark.log EXP-0015 for the full table).
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errors: none found during this implementation (clean first-pass
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correctness at every regression point).
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[2026-09-05] EXP-0016 -- regression + real improvement measurement
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after adding shared activation_cache.v (DEC-0016)
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test: hardware/v2/sim/tb_memory_manager.v (M4, updated: memory_manager
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now wired to a real activation_cache instance + a real 2-port
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arbiter, N_SLOTS=1 scope), hardware/v2/sim/tb_dataflow_core.v (M7,
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updated: sim_word_mem array widened to N_SLOTS+1, X data poked once
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into the shared cache's own backing memory instead of duplicated
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per-slot), hardware/v2/sim/tb_neural_multiprocessor.v (M8,
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UNCHANGED -- black-box), hardware/v2/sim/tb_benchmark_suite.v (final
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campaign, UNCHANGED, re-run at N_SLOTS=1/2/4/8)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: M4 3/3 PASS (bit-exact, cycle counts higher than DEC-0015
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alone for this SPECIFIC single-instance test -- expected, no sharing
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benefit possible with only one memory_manager, only the cache's real
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arbitration overhead shows up here). M7 4/4 PASS. M8 4/4 PASS
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(unchanged testbench). Final campaign 24/24 PASS bit-exact,
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D-Stress cycles reduced a further 1.66-2.00x on top of DEC-0015's
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own reduction (see benchmark.log EXP-0016 for the full table) --
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the real sharing benefit this cache targets only manifests with
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multiple neurons genuinely sharing one x_base, which only the full
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campaign's dense-layer workloads (not M4/M7/M8's own small tests)
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exercise.
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errors: 2 real bugs found and fixed during implementation (errors.log
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ERR-0010): a target-bank/pending-bank race (same class as ERR-0006,
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a new instance in the activation-cache side of memory_manager.v),
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and a repeat of ERR-0009's N_SLOTS=1 zero-width replication bug
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(this time in activation_cache.v itself).
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[2026-09-15] DEC-0043 verification -- Verilator 5.053 (-DSIM for PLL
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behavioral bypass on tb_fpga_neural_v2_top_smoke.v; plain build for
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tb_nms_dstress_sdram_unified.v, -GN_SLOTS_CFG override)
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test=tb_fpga_neural_v2_top_smoke, config=fpga_neural_v2_top N_SLOTS=4
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(default): 11/11 PASS, unchanged.
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test=tb_nms_dstress_sdram_unified (D-Stress, 256 neurons, 128 inputs
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each), config=N_SLOTS_CFG=4: PASS, 256/256 bit-exact vs golden,
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total_cycles=49927 (IDENTICAL to pre-fix), sdram_busy=81.56%,
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weight_stall=89.37% of total_cycles*N_SLOTS, useful_mac_cycles=2.04%
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of slot-cycles.
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test=tb_nms_dstress_sdram_unified (D-Stress), config=N_SLOTS_CFG=8:
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PASS, 256/256 bit-exact vs golden, total_cycles=49909 (IDENTICAL to
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pre-fix, matches DEC-0042's own recorded N=8 cycle count exactly),
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sdram_busy=81.62%, weight_stall=94.54% of total_cycles*N_SLOTS,
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useful_mac_cycles=1.02% of slot-cycles (HALF of N=4's fraction --
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more slots sharing one SDRAM channel does not proportionally
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increase useful work).
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Result: zero behavioral/cycle-count regression from the slot_mem_
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arbiter.v/slot_mem_arbiter_wide.v/nms_dataflow_core_sdram.v runtime-
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index fix (DEC-0043). Real, disclosed evidence the system is
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memory-bound at both N=4 and N=8 on a single SDRAM bank, independent
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of the arbiter fix or Fmax -- relevant to Phase 3/4 of the current
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brief.
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