micheleandClaude Sonnet 5
6a46dc857f
DEC-0043: slot_mem_arbiter.v/slot_mem_arbiter_wide.v both still had the exact runtime-variable-indexed part-select anti-pattern (pending_addr[grant_idx*ADDR_WIDTH +: ADDR_WIDTH], grant_idx a runtime register) that neural_director.v had already found and fixed once before -- ADDR_WIDTH=26 not being a power of 2 means this synthesizes as a real multiplier + wide crossbar, sitting right on the arbiter<->backend boundary this project's own N=8 congestion diagnosis names, growing with N_PORTS=N_SLOTS(+1). Also fixed the cheaper but same-class dir_job_out_slot*16 mux in nms_dataflow_core_sdram.v, feeding directly into dependency_manager -- this exact signal was DEC-0042's own diagnosed N=4 critical path. Fix: N_PORTS/N_SLOTS parallel constant-indexed comparisons (unrolled for-loop) instead of a runtime-indexed read -- same technique already proven in neural_director.v. Purely an internal-implementation change. Verified bit-exact via Verilator: tb_fpga_neural_v2_top_smoke.v 11/11 PASS; tb_nms_dstress_sdram_unified.v (256-neuron stress) at both N_SLOTS_CFG=4 and =8, 256/256 bit-exact vs golden, total_cycles IDENTICAL to pre-fix historical values (49927/49909, exact match to DEC-0042's own recorded numbers). Bonus finding from the same D-Stress run (not this commit's main point, logged for Phase 3/4): sdram_busy_cycles ~81.6% and useful-MAC-cycle fraction HALVING from N=4 to N=8 (2.04%->1.02%) -- real existing evidence the system is memory-bound on a single SDRAM bank well before N=8, independent of Fmax. Re-synthesis (8-seed sweep, N=4/N=8) in progress to measure the actual Fmax delta from this fix -- committed separately once complete. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>