micheleandClaude Sonnet 5 5afa6a7477 exp: real P&R of verified weight-reuse memory path + packed core (EXP-0063) ...

New hardware/v3/rtl/np_packed_weight_reuse_top.v: flat structural
synthesis wrapper around the EXP-0062-verified module chain (real SDR
SDRAM controller -> layer_prefetch_ctrl.v -> layer_weight_buffer.v ->
weight_tile_gather.v -> neural_processor_packed.v).

Real Vivado post-route: 8/240 DSP48E1 (unchanged, memory path uses
zero DSPs), WNS -2.502ns @ 200MHz -> Fmax ~133.3MHz, only -1.2% vs
the isolated single core (134.9MHz, EXP-0059). Real memory-path
control logic adds negligible Fmax cost at this scale.

Full writeup in hardware/v2/logs/experiments.log EXP-0063.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-16 23:44:24 +02:00

..

mac2_dsp_packed.v

v3: real Artix-7 compute core -- DSP48 packing verified, 2 real bugs found and fixed

2026-09-16 19:48:46 +02:00

neural_processor_packed.v

v3: real Artix-7 compute core -- DSP48 packing verified, 2 real bugs found and fixed

2026-09-16 19:48:46 +02:00

np_packed_array.v

exp: N=8 packed-core array real P&R, isolates placement density from interconnect (EXP-0060)

2026-09-16 23:29:54 +02:00

np_packed_weight_reuse_top.v

exp: real P&R of verified weight-reuse memory path + packed core (EXP-0063)

2026-09-16 23:44:24 +02:00

weight_tile_gather.v

feat: weight_tile_gather.v, real synthesizable byte-to-tile adapter (EXP-0061)

2026-09-16 23:34:09 +02:00