micheleandClaude Sonnet 5
5c127fb069
Closes the gap EXP-0058 left testbench-only: assembling P_IN sequential layer_weight_buffer.v byte reads into one weight_data tile bus, as real RTL instead of a testbench driver task. Avoids the runtime-indexed-part-select anti-pattern already found and fixed once in neural_director.v (ERR-0027-class Fmax collapse) by using a fixed shift-concat instead. Verified in isolation against a real, unmodified layer_weight_buffer.v: 37/37 tests, 0 errors, bit-exact across sequential, back-to-back, and non-sequential/repeated (real reuse-position-style) access patterns. Full writeup in hardware/v2/logs/experiments.log EXP-0061. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
91 lines
3.7 KiB
Verilog
91 lines
3.7 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// V3 -- real synthesizable tile-gather adapter, the piece EXP-0058's
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// own log entry flagged as still missing ("a real 'tile gather
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// adapter' (8:1 byte-to-tile packer) would be the natural next M4
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// Memory Manager deliverable if this architecture is adopted for the
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// real board" -- tb_neural_processor_layer_reuse.v did this step in
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// the testbench only, not in RTL).
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//
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// Sits between layer_weight_buffer.v's byte-wide read port (one
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// address = one byte) and neural_processor_packed.v's P_IN-wide
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// weight_data tile bus. Sequences P_IN reads, one byte/cycle, and
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// assembles them via a FIXED (compile-time-constant) shift-concat --
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// deliberately NOT a runtime-indexed part-select into the wide
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// tile_data register. This project has already been bitten by that
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// exact anti-pattern twice (neural_director.v's own slot_x_base_r
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// fix, ERR-0027-class: a variable-indexed write into a wide packed
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// register synthesizes as a real hard-multiplier-fed crossbar, real
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// measured Fmax collapse 68.51->~40-47MHz) -- avoided here from the
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// start rather than found and fixed later.
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//
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// Byte read at tile_base+i lands at tile_data[i*DATA_WIDTH +:
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// DATA_WIDTH] (i=0 is the FIRST byte read, ends at the LSB end) --
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// matches neural_processor_packed.v's own w0[gi] <=
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// weight_data[gi*DATA_WIDTH +: DATA_WIDTH] indexing exactly.
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//
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// Latency: P_IN+1 cycles from tile_req to tile_valid (1 address-setup
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// cycle + P_IN capture-and-advance cycles) -- correctness-first, not
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// yet pipelined/overlapped; matches this project's own staged
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// performance-after-correctness discipline.
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// ============================================================
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module weight_tile_gather #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter BUFADDRW = 7
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)(
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input wire clk,
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input wire rst,
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// ---- control: gather the tile starting at tile_base ----
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input wire tile_req,
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input wire [BUFADDRW-1:0] tile_base,
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output reg tile_valid, // one-cycle pulse
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output reg [DATA_WIDTH*P_IN-1:0] tile_data,
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// ---- layer_weight_buffer.v read port ----
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output reg [BUFADDRW-1:0] rd_addr,
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input wire [DATA_WIDTH-1:0] rd_data
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);
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localparam CNTW = $clog2(P_IN+1);
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localparam G_IDLE = 1'b0, G_RUN = 1'b1;
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reg g_state;
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reg [CNTW-1:0] byte_cnt;
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always @(posedge clk) begin
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if (rst) begin
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g_state <= G_IDLE;
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tile_valid <= 1'b0;
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rd_addr <= {BUFADDRW{1'b0}};
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byte_cnt <= {CNTW{1'b0}};
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tile_data <= {(DATA_WIDTH*P_IN){1'b0}};
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end else begin
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tile_valid <= 1'b0;
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case (g_state)
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G_IDLE: begin
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if (tile_req) begin
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rd_addr <= tile_base;
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byte_cnt <= {CNTW{1'b0}};
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g_state <= G_RUN;
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end
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end
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G_RUN: begin
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// rd_data reflects the rd_addr driven last cycle
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// (layer_weight_buffer.v's read is combinational).
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tile_data <= {rd_data, tile_data[DATA_WIDTH*P_IN-1:DATA_WIDTH]};
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if (byte_cnt == P_IN[CNTW-1:0] - 1'b1) begin
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tile_valid <= 1'b1;
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g_state <= G_IDLE;
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end else begin
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rd_addr <= tile_base + byte_cnt + 1'b1;
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byte_cnt <= byte_cnt + 1'b1;
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end
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end
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default: g_state <= G_IDLE;
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endcase
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end
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end
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endmodule
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