micheleandClaude Sonnet 5
94b63705be
New hardware/v3/rtl/np_packed_array.v: flat array of 8 unmodified neural_processor_packed.v instances, fully independent I/O, zero shared arbiter/Director logic -- isolates exactly one variable (DSP/placement density) from EXP-0059's single-core baseline. Real Vivado post-route: 64/240 DSP48E1 (26.67%), WNS -2.592ns @ 200MHz -> Fmax ~131.7MHz, only -2.4% vs the single-core 134.9MHz. Placement density alone is NOT the main driver of the ECP5-era gap between isolated-core and full-system Fmax -- narrows the question for the still-unbuilt real Director/arbiter/memory integration. Full writeup in hardware/v2/logs/experiments.log EXP-0060. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
81 lines
3.8 KiB
Verilog
81 lines
3.8 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// EXP-0059 follow-up -- N independent neural_processor_packed.v
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// cores, flat array, NO Director/arbiter/memory path yet.
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//
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// PURPOSE: isolate exactly one variable -- what real P&R placement/
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// routing congestion does to Fmax once N copies of the DSP48-packed
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// core sit side by side on XC7A100T -- before adding any new
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// (unverified) integration RTL (Director, arbiter, memory path).
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// Each core keeps its own independent, unshared I/O (flattened to
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// N*WIDTH buses, sliced per-instance below); there is deliberately NO
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// interconnect logic here to conflate with the placement-density
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// question this experiment is asking. Matches this project's own
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// "one variable at a time" convention (see decisions.log).
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// ============================================================
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module np_packed_array #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter ACC_WIDTH = 32,
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parameter N_CORES = 8
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)(
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input wire clk,
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input wire rst,
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input wire [N_CORES-1:0] job_valid,
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output wire [N_CORES-1:0] job_ready,
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input wire [N_CORES*16-1:0] job_node_id_a,
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input wire [N_CORES*16-1:0] job_node_id_b,
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input wire [N_CORES*DATA_WIDTH-1:0] job_bias,
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input wire [N_CORES*2-1:0] job_activation,
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input wire [N_CORES-1:0] operand_valid,
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output wire [N_CORES-1:0] operand_ready,
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input wire [N_CORES*DATA_WIDTH*P_IN-1:0] input_data_a,
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input wire [N_CORES*DATA_WIDTH*P_IN-1:0] input_data_b,
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input wire [N_CORES*DATA_WIDTH*P_IN-1:0] weight_data,
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input wire [N_CORES-1:0] tile_last,
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output wire [N_CORES-1:0] result_valid,
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input wire [N_CORES-1:0] result_ready,
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output wire [N_CORES*DATA_WIDTH-1:0] result_data_a,
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output wire [N_CORES*DATA_WIDTH-1:0] result_data_b,
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output wire [N_CORES*16-1:0] result_node_id_a,
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output wire [N_CORES*16-1:0] result_node_id_b,
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output wire [N_CORES*4-1:0] np_state,
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output wire [N_CORES-1:0] np_error
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);
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genvar gc;
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generate
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for (gc = 0; gc < N_CORES; gc = gc + 1) begin : GEN_CORE
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neural_processor_packed #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH)
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) u_core (
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.clk(clk), .rst(rst),
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.job_valid(job_valid[gc]),
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.job_ready(job_ready[gc]),
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.job_node_id_a(job_node_id_a[gc*16 +: 16]),
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.job_node_id_b(job_node_id_b[gc*16 +: 16]),
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.job_bias(job_bias[gc*DATA_WIDTH +: DATA_WIDTH]),
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.job_activation(job_activation[gc*2 +: 2]),
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.operand_valid(operand_valid[gc]),
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.operand_ready(operand_ready[gc]),
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.input_data_a(input_data_a[gc*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]),
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.input_data_b(input_data_b[gc*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]),
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.weight_data(weight_data[gc*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]),
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.tile_last(tile_last[gc]),
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.result_valid(result_valid[gc]),
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.result_ready(result_ready[gc]),
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.result_data_a(result_data_a[gc*DATA_WIDTH +: DATA_WIDTH]),
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.result_data_b(result_data_b[gc*DATA_WIDTH +: DATA_WIDTH]),
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.result_node_id_a(result_node_id_a[gc*16 +: 16]),
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.result_node_id_b(result_node_id_b[gc*16 +: 16]),
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.np_state(np_state[gc*4 +: 4]),
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.np_error(np_error[gc])
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);
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end
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endgenerate
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endmodule
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