FPGA-Neural

Files

T

micheleandClaude Sonnet 5 562cf91f1e feat: spi_host_bridge_v3.v, SPI opcode re-audit against real V3 RTL (EXP-0072)

Forked from V2's spi_host_bridge.v after finding two real protocol
mismatches: WRITE_JOB carried dependency-manager fields (required/
producer_ids) that neural_director_packed.v's job_in_* port doesn't
have (no dependency manager exists in V3 -- dropped, disclosed, not
silently ignored), and WRITE_MEM/READ_MEM assumed a word-granularity
host-arb port V3 never had (now wired through host_mem_bridge.v,
EXP-0071). Physical SPI layer carried over unchanged.

Verified standalone: 18/18 tests, 0 errors, including a case
exercising the narrower 25-bit MEM_ADDR_WIDTH's own top bit.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-17 08:56:15 +02:00

host_mem_bridge.v

feat: host_mem_bridge.v, word<->burst translator for host DDR3 access (EXP-0071)

2026-09-17 08:53:23 +02:00

mac2_dsp_packed.v

v3: real Artix-7 compute core -- DSP48 packing verified, 2 real bugs found and fixed

2026-09-16 19:48:46 +02:00

mig_native_adapter.v

feat: real DDR3 memory path verified against MIG's own ddr3_model.sv (EXP-0068)

2026-09-17 08:43:22 +02:00

n2_system_top.v

exp: real P&R of the N=2 multi-core system, first genuine system Fmax (EXP-0067)