micheleandClaude Sonnet 5
264950923b
New n8_system_ddr3_top.v: a real, permanent, named top-level (not a build-time -generic override), byte-for-byte the same RTL as n16_system_ddr3_top.v with N_GROUPS defaulting to 2. Real, full P&R under this file's own name reproduces EXP-0095's own generic-override result exactly: WNS=0.000ns, WHS=+0.017ns, 0 failing setup endpoints, 64 DSP48E1/26.7%, 12535 LUTs/19.77%. New tb_n8_system_ddr3.v (real DDR3-model methodology, adapted from tb_n16_system_ddr3.v, M=16 positions covering every one of the 2 groups x 4 PEs x 2 lanes exactly once): real functional xsim, 16/16 PASS, 0 errors -- closes the real functional-verification gap this specific N previously had. N=8 is now BOTH functionally verified AND timing-closed under its own permanent name -- the real, definitive deployment target. N=2 kept as a documented, valid fallback; N=16 kept as documented, functionally- verified-but-not-timing-closed future work, not abandoned. docs/PHYSICAL_REALIZATION.md, docs/ARCHITECTURE_ANALYSIS.md, docs/PINOUT.md updated to reflect N=8 as the current real signoff. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
Formato dei log V2
Regola non negoziabile (docs/v2-description.md §25-29): ogni attività
significativa (modifica, simulazione, sintesi, benchmark, decisione, errore)
deve essere registrata. Nessun log viene mai sovrascritto o troncato — solo
append. Nessun ID esperimento (EXP-XXXX) o decisione (DEC-XXXX) viene mai
riutilizzato, anche se il risultato è un FAIL.
File
development.log— log principale di sviluppo, un'entry per ogni sessione di lavoro/milestone (creazione file, refactor, avanzamento roadmap).architecture.log— decisioni e note di architettura a grana fine (non scelte finali — quelle vanno indecisions.log— ma esplorazioni, alternative considerate, vincoli scoperti).simulation.log— ogni run di simulazione (Icarus/Verilator): test, vettori, cicli, PASS/FAIL, confronto bit-exact con V1, stall/memory-wait.synthesis.log— ogni run Yosys: LUT/FF/DSP/BRAM, warning, problemi CHECK.timing.log— ogni run nextpnr-ecp5: Fmax, percorso critico, WNS/TNS se disponibili. Fmax "ufficiale" di una configurazione = solo da qui, mai da simulazione o stima.benchmark.log— tabelle di confronto per configurazione (Fmax, MAC/cycle, cycles/neuron, utilization, ecc.), sempre con etichetta THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R.decisions.log— decisioni architetturali importanti, formatoDEC-XXXX(vedidocs/v2-description.md§27).experiments.log— registro principale, unEXP-XXXXper ogni esperimento end-to-end (config → sim/synth/timing → risultato), rimanda areports/experiments/EXP-XXXX/.errors.log— errori/bug/regressioni incontrati durante lo sviluppo V2 stesso (non i bug V1, già chiusi inhardware/v1/docs/validation/bugs.md).
Campi minimi per entry (§26)
timestamp, experiment_id (se applicabile), git_commit, session/agent,
module, configuration, action, reason, command, result, errors, decision,
next_action
Per synthesis/timing aggiungere: LUT, FF, DSP, BRAM, Fmax, critical path, WNS/TNS. Per simulazione: test, vectors, cycles, PASS/FAIL, bit-exact result, stall cycles, memory wait, utilization.