micheleandClaude Sonnet 5
19ef54aea8
N=8 baseline (EXP-0050, real fpga_neural_v2_top + v2_board_top.lpf, fresh 8-seed sweep): 8/8 PASS at 64MHz, worst 80.97MHz, mean 84.62MHz. DSP 64/72 (88.9%) confirms real N_SLOTS=8. This directly contradicts the brief's own premise (N8 expected to collapse to ~31MHz) and the project's historical numbers (3-5/8 pass, worst ~55-67MHz) despite bit-identical RTL. Investigated and closed the same discrepancy already flagged for N=4: logs/experiments.log:2563 explicitly tags historical Fmax numbers as measured on "Yosys 0.68+"; this session's toolchain is Yosys 0.69+59, a nightly dated the same day as the session -- a confirmed ~59-commit version gap. Critical-path inspection on both N=4 and N=8 confirms the underlying RTL congestion the project diagnosed is real and still present (same bottleneck locations as previously documented) -- the newer toolchain just places it well enough to still clear 64MHz. Decision: this session's numbers are adopted as the operative baseline for Phase 1+ (see timing.log for the full writeup). Also found, not yet applied: slot_mem_arbiter.v/slot_mem_arbiter_wide.v both still have the runtime-indexed-crossbar anti-pattern already fixed in neural_director.v, sitting right on the arbiter<->backend boundary the brief names -- a concrete Phase 1 candidate. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Formato dei log V2
Regola non negoziabile (docs/v2-description.md §25-29): ogni attività
significativa (modifica, simulazione, sintesi, benchmark, decisione, errore)
deve essere registrata. Nessun log viene mai sovrascritto o troncato — solo
append. Nessun ID esperimento (EXP-XXXX) o decisione (DEC-XXXX) viene mai
riutilizzato, anche se il risultato è un FAIL.
File
development.log— log principale di sviluppo, un'entry per ogni sessione di lavoro/milestone (creazione file, refactor, avanzamento roadmap).architecture.log— decisioni e note di architettura a grana fine (non scelte finali — quelle vanno indecisions.log— ma esplorazioni, alternative considerate, vincoli scoperti).simulation.log— ogni run di simulazione (Icarus/Verilator): test, vettori, cicli, PASS/FAIL, confronto bit-exact con V1, stall/memory-wait.synthesis.log— ogni run Yosys: LUT/FF/DSP/BRAM, warning, problemi CHECK.timing.log— ogni run nextpnr-ecp5: Fmax, percorso critico, WNS/TNS se disponibili. Fmax "ufficiale" di una configurazione = solo da qui, mai da simulazione o stima.benchmark.log— tabelle di confronto per configurazione (Fmax, MAC/cycle, cycles/neuron, utilization, ecc.), sempre con etichetta THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R.decisions.log— decisioni architetturali importanti, formatoDEC-XXXX(vedidocs/v2-description.md§27).experiments.log— registro principale, unEXP-XXXXper ogni esperimento end-to-end (config → sim/synth/timing → risultato), rimanda areports/experiments/EXP-XXXX/.errors.log— errori/bug/regressioni incontrati durante lo sviluppo V2 stesso (non i bug V1, già chiusi inhardware/v1/docs/validation/bugs.md).
Campi minimi per entry (§26)
timestamp, experiment_id (se applicabile), git_commit, session/agent,
module, configuration, action, reason, command, result, errors, decision,
next_action
Per synthesis/timing aggiungere: LUT, FF, DSP, BRAM, Fmax, critical path, WNS/TNS. Per simulazione: test, vectors, cycles, PASS/FAIL, bit-exact result, stall cycles, memory wait, utilization.