micheleandClaude Sonnet 5
19ef54aea8
N=8 baseline (EXP-0050, real fpga_neural_v2_top + v2_board_top.lpf, fresh 8-seed sweep): 8/8 PASS at 64MHz, worst 80.97MHz, mean 84.62MHz. DSP 64/72 (88.9%) confirms real N_SLOTS=8. This directly contradicts the brief's own premise (N8 expected to collapse to ~31MHz) and the project's historical numbers (3-5/8 pass, worst ~55-67MHz) despite bit-identical RTL. Investigated and closed the same discrepancy already flagged for N=4: logs/experiments.log:2563 explicitly tags historical Fmax numbers as measured on "Yosys 0.68+"; this session's toolchain is Yosys 0.69+59, a nightly dated the same day as the session -- a confirmed ~59-commit version gap. Critical-path inspection on both N=4 and N=8 confirms the underlying RTL congestion the project diagnosed is real and still present (same bottleneck locations as previously documented) -- the newer toolchain just places it well enough to still clear 64MHz. Decision: this session's numbers are adopted as the operative baseline for Phase 1+ (see timing.log for the full writeup). Also found, not yet applied: slot_mem_arbiter.v/slot_mem_arbiter_wide.v both still have the runtime-indexed-crossbar anti-pattern already fixed in neural_director.v, sitting right on the arbiter<->backend boundary the brief names -- a concrete Phase 1 candidate. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>