94 lines
5.2 KiB
TeX
94 lines
5.2 KiB
TeX
\chapter{System overview}
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\label{ch:overview}
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\section{Project goal}
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FPGA-Neural implements a \textbf{reusable Neural Network Engine in FPGA hardware}.
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The whole is made of three elements: the FPGA, which is the actual accelerator; a
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dedicated RAM physically associated with the FPGA and not shared with the host; and a
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host interface independent of the operating system, initially SPI (with possible
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future extension to Dual~SPI).
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The founding principle is the separation between who \emph{executes} the computation
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and who \emph{uses} it: the neural network computation happens entirely inside the
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FPGA, while the host system only provides configuration, network parameters, input
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data, control and result readback. The host is not part of the computational datapath.
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Possible host systems include Linux SoCs, Raspberry~Pi-like systems, ESP32,
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microcontrollers and development PCs: the same engine architecture must be usable in
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completely different systems.
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\begin{center}
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\begin{tikzpicture}[font=\footnotesize,node distance=8mm]
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\node[fnblockD,minimum width=42mm,minimum height=20mm] (host){\textbf{HOST}\\[2pt]
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{\scriptsize Configuration}\\{\scriptsize Training}\\{\scriptsize Control}};
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\node[fnblockT,below=14mm of host,minimum width=42mm,minimum height=20mm] (fpga)
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{\textbf{FPGA}\\[2pt]{\scriptsize Neural Network Engine}\\{\scriptsize Compute / Control}};
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\node[fnblock,below=14mm of fpga,minimum width=42mm,minimum height=13mm] (ram)
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{\textbf{Dedicated RAM}\\{\scriptsize weights / bias / buffers}};
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\draw[fnbus] (host) -- node[fnlbl,right]{SPI / Dual SPI} (fpga);
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\draw[fnbus] (fpga) -- node[fnlbl,right]{parallel bus} (ram);
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\end{tikzpicture}
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\end{center}
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\section{Hardware configuration versus network configuration}
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The project draws a precise distinction between the accelerator's \textbf{hardware
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architecture} and the \textbf{neural network parameters}.
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The physical architecture of the engine is defined at FPGA synthesis and
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implementation time. Typical hardware parameters are \code{N\_INPUTS},
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\code{N\_NEURONS}, \code{N\_LAYERS}, \code{PARALLEL}, \code{DATA\_WIDTH},
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\code{ACC\_WIDTH}: they are Verilog parameters resolved at synthesis and they
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determine the datapath contained in the bitstream. The network parameters --- weights,
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bias, activation and quantization parameters, specific constants --- are instead loaded
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at runtime through the host interface and stored in the RAM associated with the FPGA.
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\begin{fnnote}[Central architectural principle]
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A build fixes the \emph{ceiling} of the machine (maximum number of layers, maximum
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width, \code{PARALLEL}); the host configures the \emph{actual} network --- number of
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layers, per-layer input/output width, per-layer activation and trained parameters ---
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entirely at runtime, over SPI, into the FPGA's local memory. A single bitstream serves
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any topology up to that ceiling.
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\end{fnnote}
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\section{Boot and initialization}
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The FPGA is configured at power-on through the usual configuration mechanism (bitstream
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loading from SPI flash). The bitstream defines the hardware architecture of the engine;
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the host does not dynamically build the datapath during normal operation, but rather
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configures the network data on which the already existing datapath operates.
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\begin{center}
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\begin{tikzpicture}[font=\scriptsize,node distance=4.5mm,start chain=going below,
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every node/.style={on chain}]
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\node[fnblockA,minimum width=60mm](p){Power-on};
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\node[fnblock,minimum width=60mm]{FPGA configuration (bitstream from flash)};
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\node[fnblockT,minimum width=60mm]{Neural Network Engine available};
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\node[fnblock,minimum width=60mm]{Host initialization (SPI)};
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\node[fnblock,minimum width=60mm]{Loading network parameters / weights / bias};
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\node[fnblockD,minimum width=60mm]{Engine ready};
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\begin{scope}[every path/.style={fnarrow}]
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\foreach \a/\b in {1/2,2/3,3/4,4/5,5/6}{}
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\end{scope}
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\foreach \i [count=\j from 2] in {1,...,5}{
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\draw[fnarrow] (chain-\i) -- (chain-\j);}
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\end{tikzpicture}
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\end{center}
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\section{Training and inference}
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Training and inference are conceptually separate. The first implementation does not
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require the FPGA to perform training: weights can be computed externally
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(PC/Linux/other host) and transferred over SPI into the FPGA's RAM, which then performs
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inference. This drastically reduces the complexity of the initial hardware, without
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precluding a future implementation of assisted or fully hardware training (roadmap
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Phase~8, ch.~\ref{ch:roadmap}). During inference the host only provides the input data
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and retrieves the result, obtaining deterministic computation, reduced host load,
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hardware parallelism, predictable latency and independence from the host CPU
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architecture.
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\section{Design philosophy and reuse}
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The project should be understood as a \emph{reusable FPGA neural acceleration platform}
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rather than a single network. The application determines input size, topology, number
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of layers and neurons, parallelism, numeric precision, activation functions, memory and
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performance requirements; the hardware generation process produces the corresponding
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FPGA implementation. The same HDL architecture remains conceptually unchanged while the
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synthesis parameters generate implementations appropriate to the different application
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targets.
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