michele 18bf038ed5 v1 datasheet latex source

2026-09-06 15:02:25 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

V2.1.0-dev: SPI host bridge + clock/reset architecture (NOT release-ready)

2026-09-06 14:35:14 +02:00

hardware

v1 datasheet latex source

2026-09-06 15:02:25 +02:00

rtl

fix: close 7 zero-value/mid-run guard gaps found in re-certification campaign

2026-09-04 20:29:05 +02:00

sim

fix: close 7 zero-value/mid-run guard gaps found in re-certification campaign

2026-09-04 20:29:05 +02:00

synth/ecp5

fix: close 7 zero-value/mid-run guard gaps found in re-certification campaign

2026-09-04 20:29:05 +02:00

tools

fix: close 7 zero-value/mid-run guard gaps found in re-certification campaign

2026-09-04 20:29:05 +02:00

.gitignore

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

WORKLOG.md

fix: close 7 zero-value/mid-run guard gaps found in re-certification campaign

2026-09-04 20:29:05 +02:00

S

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