micheleandClaude Sonnet 5
ccaf3ee059
Adds result_writeback.v, one instance per packed_slot.v, writing each completed job's result directly into DDR3 at the job's own result_addr_a/b instead of driving literal top-level pins -- the same architectural shape as the weight-fetch path, in reverse. job_done now means "durably in DDR3", not "captured in a register only a pin could see". n2_system_ddr3_top.v's own s0_result_data_a/b, s1_result_data_a/b top-level package pins are removed (and the now-dangling XDC constraint for them), closing the real, hard scaling blocker docs/ARCHITECTURE_ ANALYSIS.md flagged since EXP-0074/0079 (8 bits x 2 lanes x N cores -> 256 pins at N=16). Addressing reuses the exact same JOB_ADDR_WIDTH->ctrl-bus-word truncation x_base_a/w_base already use (verified against act_tile_ fetch.v's/layer_prefetch_ctrl.v's own real code, not guessed). The host reads results back via the already-existing READ_MEM (0x02) SPI opcode -- no new protocol. A real EXP-0066-class bug (issuing ctrl_req before mem_grant) was caught and fixed before ever compiling, by re-deriving the design against act_tile_fetch.v's own proven S_MEMWAIT/S_GAP sequencing. Verified two ways: tb_packed_slot.v extended with a real DDR3 read-after-write check (9/9 PASS, confirms the write actually landed, not just that job_done pulsed); tb_n2_system_ddr3.v re-run via real xsim to confirm correct behavior under real 2-slot shared-bus arbitration (8/8 PASS, 0 errors, consistent timing with EXP-0087's own baseline for this workload). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
110 lines
6.3 KiB
Tcl
110 lines
6.3 KiB
Tcl
# ============================================================
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# V3 -- top-level pin/IOSTANDARD constraints for n2_system_ddr3_top.v,
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# real xc7a100tcsg324-2, board is the user's own custom design (bare
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# chip + DDR3, no dev board). DDR3 pins themselves are NOT here --
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# those come from the MIG-generated mig_7series_0.xdc (dictated by
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# the FPGA's internal DDR3 PHY hardware, not a free choice).
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#
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# Verified against the real device via a routed checkpoint query
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# (open_checkpoint + get_package_pins/get_ports on n2_system_ddr3_
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# top_routed.dcp), not guessed from a datasheet table.
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# ============================================================
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# ---- required for flash_spi_master.v to work at all: D00_MOSI/
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# D01_DIN/FCS_B only become ordinary fabric I/O post-configuration
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# when PERSIST is FALSE (the Vivado default -- set explicitly here so
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# this dependency is self-documenting in the constraints, not just a
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# silent default someone could flip later without realizing why).
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set_property BITSTREAM.CONFIG.PERSIST NO [current_design]
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# ---- config-flash passthrough (-> flash_spi_master.v, EXP-0077):
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# EXP-0084 REAL, RE-CONFIRMED CONFLICT (not hypothetical any more):
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# D00_MOSI/D01_DIN/FCS_B's ORIGINAL pins (K17/K18/L13, bank 14) share
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# bank 14 with the real differential reference clock (clk_ref_p/n,
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# T14/T15) chosen during the EXP-0084 MIG wizard session -- a single
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# I/O bank can only have ONE VCCO, and LVCMOS33 (3.3V, what the flash
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# needs) is incompatible with LVDS_25 (2.5V, what clk_ref needs). This
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# was flagged as a real *risk* when T14/T15 was chosen (real device
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# data showed bank 14 already hosted the flash bus); EXP-0084's real
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# place_design run turned that risk into a real, observed placement
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# failure ("IO placement is infeasible" -- flash_mosi/flash_cs_n
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# couldn't be placed at their old LOCs at all). FIX: moved the flash
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# bus to bank 16 (D9/D10/C9) -- completely unconstrained, no VCCO
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# commitment, so it can freely be 3.3V with zero conflict. Real,
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# verified-available pins (queried from the actual part database, not
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# guessed) -- D9/D10/C9 are ordinary I/O in bank 16, none of them are
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# the config-mode-reserved EMCCLK/RDWR_B/CSI_B pins (still PROHIBITed
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# below regardless). CCLK is NOT constrained here -- it's driven via
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# STARTUPE2 internally, never a plain top-level port.
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set_property PACKAGE_PIN D9 [get_ports flash_mosi]
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set_property PACKAGE_PIN D10 [get_ports flash_miso]
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set_property PACKAGE_PIN C9 [get_ports flash_cs_n]
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set_property IOSTANDARD LVCMOS33 [get_ports flash_mosi]
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set_property IOSTANDARD LVCMOS33 [get_ports flash_miso]
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set_property IOSTANDARD LVCMOS33 [get_ports flash_cs_n]
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# ---- EMCCLK/RDWR_B/CSI_B (bank 14): not used by this design at all
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# (this project's Master SPI config mode never needed them -- they're
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# only relevant to modes this board doesn't use, e.g. BPI or Quad-SPI
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# extra data lines) -- PROHIBITed so Vivado's auto-placement never
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# lands an unrelated port there by accident (it already had once,
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# before this constraint existed, on a result-data bit).
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set_property PROHIBIT true [get_sites -of_objects [get_package_pins {L16 R16 V15}]]
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# ---- EXP-0084: remaining top-level ports with no fixed board LOC yet
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# (status signals) default to LVCMOS18 with no explicit IOSTANDARD set
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# -- real place_design found this real, concrete: banks 14/15/34/35 are
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# ALL already committed to other real voltages (2.5V/3.3V/1.5V/1.5V),
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# leaving only bank 16's spare pins as LVCMOS18-compatible, and there
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# aren't enough of them. Assign these explicitly to LVCMOS33 so they
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# place in bank 15's own real spare capacity instead -- a real,
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# necessary fix, not a workaround; a permanent board LOC for each
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# should still be assigned once the rest of the board layout is
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# decided (S7 of docs/PHYSICAL_REALIZATION.md).
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# EXP-0088: the s0_result_data_a/b, s1_result_data_a/b ports this
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# constraint used to also cover no longer exist as top-level ports --
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# each slot now writes its own result directly into DDR3 via its own
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# internal result_writeback.v (see packed_slot.v's own header) instead
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# of exposing literal, N-scaled result pins.
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set_property IOSTANDARD LVCMOS33 [get_ports {job_out_slot[*] job_out_done init_calib_complete ui_clk_o}]
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# ---- neural-processor management SPI (-> spi_host_bridge_v3.v):
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# job submission + register file. Bank 15, column A/B (package edge,
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# physically adjacent pins for short/easy PCB routing), well clear of
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# both DDR3 (banks 34/35) and the reserved config-flash pins above.
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# IOSTANDARD assumes bank 15 is powered at 3.3V on the custom board --
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# change to match whatever VCCO the user's own power plan uses for
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# that bank.
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set_property PACKAGE_PIN A15 [get_ports sclk]
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set_property PACKAGE_PIN B16 [get_ports mosi]
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set_property PACKAGE_PIN B17 [get_ports miso]
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set_property PACKAGE_PIN A16 [get_ports cs_n]
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set_property IOSTANDARD LVCMOS33 [get_ports sclk]
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set_property IOSTANDARD LVCMOS33 [get_ports mosi]
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set_property IOSTANDARD LVCMOS33 [get_ports miso]
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set_property IOSTANDARD LVCMOS33 [get_ports cs_n]
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# ---- sys_rst: EXP-0084 found this real -- with the 32-bit DDR3
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# interface now committing banks 14/34/35 to 2.5V/1.5V/1.5V and bank
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# 15 to 3.3V, there is genuinely NO bank left at the 1.8V sys_rst was
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# silently defaulting to (no explicit IOSTANDARD was ever set) -- real
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# place_design failure ("IO placement is infeasible... needs 1.8V,
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# has 0 sites"), not hit before only because the smaller 16-bit I/O
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# footprint happened to leave enough slack somewhere. Placed here
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# temporarily in bank 15 alongside the management SPI bus (same real,
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# already-committed 3.3V) -- NOT a final board decision, still pending
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# the real PCB layout for the reset circuit (button/supervisor IC),
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# per S7 of docs/PHYSICAL_REALIZATION.md. Real, verified-free pin
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# (queried from the actual part database).
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set_property PACKAGE_PIN G13 [get_ports sys_rst]
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set_property IOSTANDARD LVCMOS33 [get_ports sys_rst]
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# ---- data_ready_n: real, user-requested active-low sticky IRQ so the
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# ESP32 can be interrupt-driven instead of polling STATUS (see
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# spi_host_bridge_v3.v's own header for the real set/clear semantics).
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# Placed in bank 15 alongside the management SPI bus (same real,
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# already-committed 3.3V) -- real, verified-free pin, not yet a final
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# board decision (same caveat as sys_rst above).
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set_property PACKAGE_PIN D14 [get_ports data_ready_n]
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set_property IOSTANDARD LVCMOS33 [get_ports data_ready_n]
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