micheleandClaude Sonnet 5
175f697ae1
Implements M4: memory_manager.v (arbitration/buffering/forwarding/ latency hiding/double buffering, §12) + prefetch_engine.v (double-buffered tile fetch, §13), sitting on the REAL, UNMODIFIED V1 PSRAM backend chain (int8_memory_access.v -> memory_interface.v -> psram_controller.v, per §15's explicit mandate not to touch the controller). Verified fully end-to-end with Verilator: real neural_processor (M1) fed entirely by memory_manager, computing against PSRAM-resident X/W tiles (double-buffered prefetch across up to 5 tiles) and writing its result back to PSRAM -- checked via an independent PSRAM read-back, with poison bytes around the operand regions to catch addressing errors. 3/3 jobs pass (1/3/5-tile configurations). Three real RTL bugs found and fixed during integration (full diagnostic trail in errors.log ERR-0006): prefetch_engine had no single-in-flight-request discipline, letting a queued request corrupt the bank bookkeeping of a fetch already running; the fix's own !pf_busy guard had a one-cycle blind spot (pf_busy lags pf_start by a clock) that needed an explicit !pf_start term; and a state-based mux for the shared backend port was off by one cycle, silently dropping the PSRAM result write entirely. Real synthesis: 0 CHECK problems, 851 LUT4/789 FF/108 CCU2C/0 DSP (expected, no multiplication in this module). Real place&route (via a synthesis-only timing harness, needed for the same TRELLIS_IO pin- budget reason as M2's array): Fmax 165.86 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
72 lines
3.0 KiB
Verilog
72 lines
3.0 KiB
Verilog
// ================================================================
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// SYNTHESIS-ONLY TIMING HARNESS -- NOT a functional deliverable.
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// Same rationale/pattern as harness_neural_processor_array.v (see its
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// header and hardware/v2/logs/errors.log ERR-0005): memory_manager's
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// wide ports (input_data/weight_data alone, 64 bits) exceed the
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// LFE5U-45F's TRELLIS_IO budget as a bare top-level module. Drives
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// them from an internal LFSR and reduces outputs to a small
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// checksum, keeping only clk/rst/seed/checksum as real pins, to get
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// a representative Fmax for memory_manager's own logic/routing.
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// ================================================================
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module harness_memory_manager #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter ADDR_WIDTH = 23
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)(
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input wire clk,
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input wire rst,
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input wire [7:0] seed,
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output wire [7:0] checksum
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);
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reg [31:0] lfsr;
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always @(posedge clk) begin
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if (rst) lfsr <= {24'h0, seed} | 32'h1;
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else lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]};
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end
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wire job_start = lfsr[0];
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wire [ADDR_WIDTH-1:0] x_base = lfsr[ADDR_WIDTH-1:0];
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wire [ADDR_WIDTH-1:0] w_base = {lfsr[7:0], lfsr[ADDR_WIDTH-9:0]};
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wire [15:0] n_tiles = lfsr[15:0];
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wire [ADDR_WIDTH-1:0] result_addr = {lfsr[3:0], lfsr[ADDR_WIDTH-5:0]};
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wire operand_ready = lfsr[2];
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wire result_valid = lfsr[3];
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wire signed [DATA_WIDTH-1:0] result_data = lfsr[7:0];
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wire signed [7:0] mem_rdata = lfsr[15:8];
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wire mem_ready = lfsr[4];
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wire job_done;
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wire operand_valid;
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wire signed [DATA_WIDTH*P_IN-1:0] input_data, weight_data;
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wire tile_last;
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wire result_ready;
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wire mem_req, mem_wr;
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wire [ADDR_WIDTH-1:0] mem_addr;
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wire signed [7:0] mem_wdata;
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memory_manager #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ADDR_WIDTH(ADDR_WIDTH)
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) dut (
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.clk(clk), .rst(rst),
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.job_start(job_start), .x_base(x_base), .w_base(w_base),
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.n_tiles(n_tiles), .result_addr(result_addr), .job_done(job_done),
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.operand_valid(operand_valid), .operand_ready(operand_ready),
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.input_data(input_data), .weight_data(weight_data), .tile_last(tile_last),
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.result_valid(result_valid), .result_ready(result_ready), .result_data(result_data),
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.mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr), .mem_wdata(mem_wdata),
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.mem_rdata(mem_rdata), .mem_ready(mem_ready)
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);
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reg [7:0] chk;
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always @(posedge clk) begin
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if (rst) chk <= 8'h0;
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else chk <= chk ^ input_data[7:0] ^ weight_data[7:0] ^ {7'h0, job_done}
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^ {6'h0, tile_last, result_ready} ^ mem_addr[7:0]
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^ {7'h0, mem_req} ^ {7'h0, mem_wr} ^ mem_wdata;
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end
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assign checksum = chk;
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endmodule
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