micheleandClaude Sonnet 5
2e4cedc761
Implements M5: neural_director.v dispatches job descriptors to whichever of N_SLOTS (memory_manager, neural_processor) pairs is currently free (first-free scheduling per §9's initial policy), with a parametric-depth ready-queue FIFO for jobs arriving faster than slots can absorb them. Scope for this milestone (see decisions.log DEC-0007): a reduced 4-state FSM (DIR_IDLE/SCAN_READY/ALLOCATE/ERROR) rather than §9's full 8-state baseline -- dependency tracking, the waiting queue, and wake-up are §10's explicit responsibility (Dependency Manager, M6, not yet built), and slot-completion detection runs as an always-active per-slot tracker rather than a dedicated FSM state, for the same reason DEC-0002 already gave for the Neural Processor's own FSM (gating concurrent per-unit progress behind one shared state kills throughput). Verified with Verilator (N_SLOTS=2, each slot backed by its own independent behavioral memory rather than sharing V1's real PSRAM -- M4 already proved that path for one slot; this milestone's own concern is scheduling across multiple slots): 4/4 tests pass -- 3 jobs submitted to 2 slots (first two dispatch immediately, third correctly queues until a slot frees), and a deliberate burst that forces the ready queue to genuinely fill and recover. Real synthesis: 0 CHECK problems, 382 LUT4/366 FF/4 CCU2C/0 DSP. Real place&route (via a synthesis-only timing harness, same TRELLIS_IO pin-budget reason as M2/M4): Fmax 250.50 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
323 lines
14 KiB
Verilog
323 lines
14 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// M5 testbench (docs/v2-description.md §9/§20): neural_director.v
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// dispatching to N_SLOTS=2 (memory_manager + neural_processor) pairs.
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// Verified with Verilator (decisions.log DEC-0004).
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//
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// Scope decision (decisions.log DEC-0007): each slot gets its OWN
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// independent simple behavioral byte memory (sim_byte_mem below,
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// fixed 2-cycle latency, matching int8_memory_access.v's req/wr/addr/
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// wdata -> rdata/ready contract exactly) instead of sharing V1's real
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// PSRAM chain -- M4 already proved the real PSRAM path end-to-end
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// with ONE slot (EXP-0005); M5's own concern is scheduling/dispatch
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// across MULTIPLE slots, which is what this testbench isolates.
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// Multiple slots genuinely sharing ONE physical PSRAM port is a
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// backend-arbitration problem explicitly deferred (DEC-0006), not
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// re-solved here.
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//
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// Coverage:
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// - more jobs submitted (3) than slots exist (2): first two must
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// dispatch immediately (first-free), the third must wait in the
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// ready queue until a slot frees up, then dispatch automatically.
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// - each job's result independently verified (own oracle).
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// - ready-queue backpressure: fill the queue past N jobs beyond
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// slot capacity and confirm job_in_ready deasserts, then confirm
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// it drains and reasserts as slots complete.
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// ============================================================
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module sim_byte_mem #(
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parameter ADDR_WIDTH = 23,
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parameter DEPTH = 1024
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)(
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input wire clk,
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input wire rst,
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input wire req,
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input wire wr,
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input wire [ADDR_WIDTH-1:0] addr,
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input wire signed [7:0] wdata,
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output reg signed [7:0] rdata,
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output reg ready
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);
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reg signed [7:0] mem [0:DEPTH-1];
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reg [1:0] state;
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reg [ADDR_WIDTH-1:0] addr_reg;
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reg wr_reg;
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localparam ST_IDLE = 0, ST_WAIT = 1;
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always @(posedge clk) begin
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if (rst) begin
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state <= ST_IDLE; ready <= 1'b0; rdata <= 8'sd0;
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end else begin
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ready <= 1'b0;
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case (state)
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ST_IDLE: if (req) begin
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addr_reg <= addr; wr_reg <= wr;
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if (wr) mem[addr] <= wdata;
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state <= ST_WAIT;
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end
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ST_WAIT: begin
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rdata <= mem[addr_reg];
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ready <= 1'b1;
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state <= ST_IDLE;
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end
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endcase
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end
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end
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endmodule
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module tb;
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localparam ADDR_WIDTH = 23;
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localparam DATA_WIDTH = 8;
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localparam P_IN = 8;
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localparam ACC_WIDTH = 32;
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localparam N_SLOTS = 2;
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localparam QUEUE_DEPTH = 4;
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reg clk, rst;
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initial begin clk = 0; forever #5 clk = ~clk; end
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reg job_in_valid;
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wire job_in_ready;
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reg [ADDR_WIDTH-1:0] job_in_x_base, job_in_w_base, job_in_result_addr;
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reg [15:0] job_in_n_tiles, job_in_node_id;
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wire [N_SLOTS-1:0] slot_job_start;
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wire [ADDR_WIDTH*N_SLOTS-1:0] slot_x_base, slot_w_base, slot_result_addr;
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wire [16*N_SLOTS-1:0] slot_n_tiles;
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wire [N_SLOTS-1:0] slot_job_done;
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wire job_out_done;
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wire [$clog2(N_SLOTS)-1:0] job_out_slot;
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wire [3:0] dir_state;
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wire dir_error;
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neural_director #(
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.ADDR_WIDTH(ADDR_WIDTH), .N_SLOTS(N_SLOTS), .QUEUE_DEPTH(QUEUE_DEPTH)
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) u_dir (
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.clk(clk), .rst(rst),
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.job_in_valid(job_in_valid), .job_in_ready(job_in_ready),
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.job_in_x_base(job_in_x_base), .job_in_w_base(job_in_w_base),
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.job_in_n_tiles(job_in_n_tiles), .job_in_result_addr(job_in_result_addr),
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.job_in_node_id(job_in_node_id),
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.slot_job_start(slot_job_start), .slot_x_base(slot_x_base), .slot_w_base(slot_w_base),
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.slot_n_tiles(slot_n_tiles), .slot_result_addr(slot_result_addr), .slot_job_done(slot_job_done),
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.job_out_done(job_out_done), .job_out_slot(job_out_slot),
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.dir_state(dir_state), .dir_error(dir_error)
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);
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genvar g;
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generate
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for (g = 0; g < N_SLOTS; g = g + 1) begin : GEN_SLOT
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wire mm_operand_valid, mm_operand_ready;
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wire signed [DATA_WIDTH*P_IN-1:0] mm_input_data, mm_weight_data;
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wire mm_tile_last;
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wire mm_result_valid, mm_result_ready;
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wire signed [DATA_WIDTH-1:0] mm_result_data;
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wire mem_req, mem_wr;
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wire [ADDR_WIDTH-1:0] mem_addr;
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wire signed [7:0] mem_wdata, mem_rdata;
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wire mem_ready;
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memory_manager #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ADDR_WIDTH(ADDR_WIDTH)
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) u_mm (
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.clk(clk), .rst(rst),
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.job_start(slot_job_start[g]),
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.x_base(slot_x_base[g*ADDR_WIDTH +: ADDR_WIDTH]),
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.w_base(slot_w_base[g*ADDR_WIDTH +: ADDR_WIDTH]),
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.n_tiles(slot_n_tiles[g*16 +: 16]),
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.result_addr(slot_result_addr[g*ADDR_WIDTH +: ADDR_WIDTH]),
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.job_done(slot_job_done[g]),
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.operand_valid(mm_operand_valid), .operand_ready(mm_operand_ready),
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.input_data(mm_input_data), .weight_data(mm_weight_data), .tile_last(mm_tile_last),
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.result_valid(mm_result_valid), .result_ready(mm_result_ready), .result_data(mm_result_data),
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.mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr), .mem_wdata(mem_wdata),
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.mem_rdata(mem_rdata), .mem_ready(mem_ready)
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);
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reg job_valid_np;
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wire job_ready_np;
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wire result_valid_np;
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wire signed [DATA_WIDTH-1:0] result_data_np;
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wire [3:0] np_state;
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wire np_error;
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neural_processor #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH)
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) u_np (
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.clk(clk), .rst(rst),
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.job_valid(job_valid_np), .job_ready(job_ready_np),
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.job_node_id(16'h0), .job_bias(8'sd0), .job_activation(2'd1),
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.operand_valid(mm_operand_valid), .operand_ready(mm_operand_ready),
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.input_data(mm_input_data), .weight_data(mm_weight_data), .tile_last(mm_tile_last),
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.result_valid(result_valid_np), .result_ready(mm_result_ready),
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.result_data(result_data_np), .result_node_id(),
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.np_state(np_state), .np_error(np_error)
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);
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assign mm_result_valid = result_valid_np;
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assign mm_result_data = result_data_np;
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always @(posedge clk) begin
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if (rst) job_valid_np <= 1'b0;
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else if (slot_job_start[g]) job_valid_np <= 1'b1;
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else if (job_valid_np && job_ready_np) job_valid_np <= 1'b0;
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end
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sim_byte_mem #(.ADDR_WIDTH(ADDR_WIDTH), .DEPTH(4096)) u_mem (
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.clk(clk), .rst(rst),
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.req(mem_req), .wr(mem_wr), .addr(mem_addr), .wdata(mem_wdata),
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.rdata(mem_rdata), .ready(mem_ready)
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);
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end
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endgenerate
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task automatic poke(input integer slot, input [ADDR_WIDTH-1:0] addr, input [7:0] val);
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begin
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case (slot)
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0: tb.GEN_SLOT[0].u_mem.mem[addr] = val;
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1: tb.GEN_SLOT[1].u_mem.mem[addr] = val;
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default: ;
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endcase
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end
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endtask
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function automatic signed [7:0] peek(input integer slot, input [ADDR_WIDTH-1:0] addr);
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begin
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case (slot)
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0: peek = tb.GEN_SLOT[0].u_mem.mem[addr];
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1: peek = tb.GEN_SLOT[1].u_mem.mem[addr];
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default: peek = 8'sdx;
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endcase
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end
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endfunction
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integer errors, tests;
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task automatic submit_job(
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input [ADDR_WIDTH-1:0] xb, input [ADDR_WIDTH-1:0] wb,
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input [15:0] nt, input [ADDR_WIDTH-1:0] resaddr, input [15:0] nid
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);
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begin
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@(posedge clk);
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job_in_x_base = xb; job_in_w_base = wb; job_in_n_tiles = nt;
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job_in_result_addr = resaddr; job_in_node_id = nid;
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job_in_valid = 1'b1;
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while (!job_in_ready) @(posedge clk);
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@(posedge clk);
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job_in_valid = 1'b0;
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end
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endtask
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integer i;
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integer wd;
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initial begin
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errors = 0; tests = 0;
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rst = 1; job_in_valid = 0; job_in_x_base = 0; job_in_w_base = 0;
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job_in_n_tiles = 0; job_in_result_addr = 0; job_in_node_id = 0;
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repeat(4) @(posedge clk);
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rst = 0;
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@(posedge clk);
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// ---- prepare 3 independent jobs (2 slots, so job 2 must
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// wait in the ready queue for a slot to free up) ----
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// Job 0 (slot 0 pre-loaded region 0x100/0x200): 8 inputs, x=2,w=3 -> acc=48
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for (i = 0; i < 8; i = i + 1) begin poke(0, 23'h100+i, 8'sd2); poke(0, 23'h200+i, 8'sd3); poke(1, 23'h100+i, 8'sd2); poke(1, 23'h200+i, 8'sd3); end
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// Job 1 (either slot, region 0x300/0x400): 16 inputs, x=1,w=1 -> acc=16
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for (i = 0; i < 16; i = i + 1) begin poke(0, 23'h300+i, 8'sd1); poke(0, 23'h400+i, 8'sd1); poke(1, 23'h300+i, 8'sd1); poke(1, 23'h400+i, 8'sd1); end
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// Job 2 (queued until a slot frees, region 0x500/0x600): 8 inputs, x=1,w=5 -> acc=40
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for (i = 0; i < 8; i = i + 1) begin poke(0, 23'h500+i, 8'sd1); poke(0, 23'h600+i, 8'sd5); poke(1, 23'h500+i, 8'sd1); poke(1, 23'h600+i, 8'sd5); end
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submit_job(23'h100, 23'h200, 16'd1, 23'h700, 16'd1); // -> dispatches to slot 0 (first-free)
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submit_job(23'h300, 23'h400, 16'd2, 23'h701, 16'd2); // -> dispatches to slot 1
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submit_job(23'h500, 23'h600, 16'd1, 23'h702, 16'd3); // -> waits in queue
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// job_in_ready should have stayed high throughout (only 3
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// jobs, queue depth 4) -- confirmed implicitly: submit_job's
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// own while-loop would have hung the testbench otherwise.
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tests = tests + 3;
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wd = 0;
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begin
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integer completions;
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completions = 0;
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while (completions < 3 && wd < 3000) begin
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@(posedge clk);
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wd = wd + 1;
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if (job_out_done) completions = completions + 1;
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end
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if (completions < 3)
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$display("FAIL: only %0d/3 jobs completed within watchdog", completions);
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end
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// give the last-completing job's write a little extra margin
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repeat(5) @(posedge clk);
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if (peek(0, 23'h700) !== 8'sd48) begin
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$display("FAIL job0: result=%0d expected=48", peek(0,23'h700)); errors = errors + 1;
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end else $display("PASS job0 (slot dispatched first-free): result=48");
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if (peek(1, 23'h701) !== 8'sd16) begin
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$display("FAIL job1: result=%0d expected=16", peek(1,23'h701)); errors = errors + 1;
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end else $display("PASS job1 (slot dispatched first-free): result=16");
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// Job 2 could have landed on either slot (whichever freed
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// first) -- check both.
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if (peek(0, 23'h702) !== 8'sd40 && peek(1, 23'h702) !== 8'sd40) begin
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$display("FAIL job2 (queued): neither slot's result byte at 0x702 is 40 (got %0d / %0d)", peek(0,23'h702), peek(1,23'h702));
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errors = errors + 1;
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end else $display("PASS job2 (queued until a slot freed): result=40");
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// ---- backpressure: occupy both slots with LONG jobs (many
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// tiles, so they stay busy for a while and won't drain the
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// queue mid-burst), then push jobs faster than they can be
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// consumed and confirm job_in_ready genuinely deasserts once
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// the queue fills, then recovers once slots free up again. ----
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tests = tests + 1;
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for (i = 0; i < 64; i = i + 1) begin poke(0, 23'h800+i, 8'sd1); poke(0, 23'h900+i, 8'sd1); poke(1, 23'h800+i, 8'sd1); poke(1, 23'h900+i, 8'sd1); end
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submit_job(23'h800, 23'h900, 16'd64, 23'h704, 16'd10); // occupies slot 0/1 for a while
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submit_job(23'h800, 23'h900, 16'd64, 23'h705, 16'd11); // occupies the other slot
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job_in_x_base = 23'h100; job_in_w_base = 23'h200; job_in_n_tiles = 16'd1;
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job_in_result_addr = 23'h706; job_in_node_id = 16'd12;
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i = 0;
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while (job_in_ready && i < QUEUE_DEPTH + 2) begin
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@(posedge clk);
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job_in_valid = 1'b1;
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@(posedge clk);
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i = i + 1;
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end
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if (i > QUEUE_DEPTH) begin
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$display("FAIL backpressure: job_in_ready never deasserted after %0d pushes (QUEUE_DEPTH=%0d) -- both slots busy, queue should have filled", i, QUEUE_DEPTH);
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errors = errors + 1;
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end else begin
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$display("PASS backpressure: job_in_ready correctly deasserted after %0d queued jobs (QUEUE_DEPTH=%0d), both slots busy", i, QUEUE_DEPTH);
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end
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job_in_valid = 1'b0;
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// Drain: wait for everything (2 long jobs + whatever got
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// queued) to finish, no watchdog failure, and confirm
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// job_in_ready recovers once slots/queue free up.
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wd = 0;
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while (!job_in_ready && wd < 5000) begin @(posedge clk); wd = wd + 1; end
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if (!job_in_ready) begin
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$display("FAIL backpressure: job_in_ready never recovered within watchdog");
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errors = errors + 1;
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end else begin
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$display("PASS backpressure: job_in_ready recovered once slots/queue drained");
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end
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$display("========================================");
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if (errors == 0)
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$display("ALL %0d TESTS PASSED (neural_director, first-free scheduling, N_SLOTS=%0d)", tests, N_SLOTS);
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else
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$display("FAILED: %0d/%0d test(s) had errors -- see messages above", errors, tests);
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$display("========================================");
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$finish;
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end
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endmodule
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