micheleandClaude Sonnet 5
1ce78dff6e
EXP-0056: N_SLOTS=16 failed timing on LFE5U-85F (23-24MHz vs 64MHz
target). First hypothesis (dependency_manager.v's serial ready-scan)
was wrong but real -- built and verified priority_encoder_lsb.v (a
generic recursive tree encoder) and dependency_manager_fast.v, bit-
exact equivalent to the original, but integrated it made no real
difference (24.26MHz). The real cause, found from nextpnr's own
critical-path report: nms_activation_fill_ctrl_v3.v's balanced max-
tree was only ever extended to N_SLOTS in {1,2,4,8}, silently falling
back to the original slow scan for 16. Added the missing case
(nms_activation_fill_ctrl_v3_n16.v), verified isolated (10017/10017)
and functionally (D-Stress N=16 still 256/256 bit-exact). Real result:
71.01MHz, PASS at 64MHz (single seed so far).
EXP-0057: built layer_weight_buffer.v, a double-buffered per-layer
weight scratchpad (fill one buffer in the background from SDRAM while
compute reads many times from the other -- weight-stationary reuse,
as opposed to D-Stress's own deliberately zero-reuse pattern). Wired
to the real sdram_controller_openrow.v + sdram_model.v, no new
hardware. For the same 32768 bytes of useful data: zero-reuse costs
27048 real cycles, reuse costs 3777 -- 7.16x real measured speedup on
the SAME SDR SDRAM, no DDR3, no clock change. This is the answer to
whether DDR3 is necessary for a workload class that actually has
reuse (e.g. conv-style face recognition, unlike D-Stress) -- it isn't,
at least not for this reason.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
94 lines
4.0 KiB
Verilog
94 lines
4.0 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// EXP-0057 -- double-buffered, per-layer resident weight scratchpad.
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//
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// One layer's worth of weights (up to LAYER_DEPTH entries of
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// DATA_WIDTH bits, real BRAM-style array, same coding idiom as
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// nms_weight_packed.v's own per-slot memories) stays resident and is
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// read MANY times (once per output position that reuses it -- e.g.
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// every spatial position a convolutional filter slides across),
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// while the NEXT layer's weights are being fetched into the OTHER
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// buffer in the background. Buffers swap only when BOTH conditions
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// hold: the compute side has finished consuming the active buffer
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// (consume_done) AND the fill side has finished loading the other one
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// (fill_done) -- matches this project's own established discipline
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// (never swap/overwrite data still in use, same spirit as
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// sdram_unified_backend.v's own req_pending latch correctness fixes).
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//
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// This is deliberately NOT the same thing as the existing per-slot
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// nms_weight_packed.v buffer: that one holds MAX_TILES tiles for ONE
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// job with no reuse across neurons (D-Stress's own zero-reuse case).
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// This module exists for the OPPOSITE traffic pattern -- one weight
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// block read many times before being replaced -- which is what a
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// convolutional filter (or any weight-stationary dataflow) needs.
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// ============================================================
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module layer_weight_buffer #(
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parameter DATA_WIDTH = 8,
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parameter LAYER_DEPTH = 128,
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parameter ADDRW = (LAYER_DEPTH <= 1) ? 1 : $clog2(LAYER_DEPTH)
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)(
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input wire clk,
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input wire rst,
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// ---- fill side: writes into the INACTIVE buffer ----
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input wire fill_we,
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input wire [ADDRW-1:0] fill_addr,
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input wire [DATA_WIDTH-1:0] fill_data,
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input wire fill_done, // pulse: inactive buffer fully loaded
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// ---- compute side: reads from the ACTIVE buffer, any number of
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// times, any order (real conv access pattern is not necessarily
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// sequential -- e.g. im2col-style window reuse) ----
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input wire [ADDRW-1:0] rd_addr,
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output wire [DATA_WIDTH-1:0] rd_data,
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input wire consume_done, // pulse: compute side is done with the active buffer
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// ---- swap: happens the cycle AFTER both fill_done and
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// consume_done have been seen since the last swap -- order-
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// independent (a pulse arriving before the other is latched, not
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// dropped), matching this project's own req_pending latch idiom ----
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output reg active_sel, // which physical buffer (0/1) is active for reads
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output reg swapped // pulses the cycle a swap occurs
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);
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reg [DATA_WIDTH-1:0] mem0 [0:LAYER_DEPTH-1];
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reg [DATA_WIDTH-1:0] mem1 [0:LAYER_DEPTH-1];
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reg fill_done_latched, consume_done_latched;
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wire do_swap = fill_done_latched && consume_done_latched;
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always @(posedge clk) begin
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if (fill_we) begin
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if (active_sel == 1'b0) mem1[fill_addr] <= fill_data; // fill the INACTIVE one
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else mem0[fill_addr] <= fill_data;
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end
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end
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// read from the ACTIVE buffer, combinational (matches
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// nms_weight_packed.v's own same-cycle-bypass-free combinational
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// read convention for a single-port style array read)
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assign rd_data = active_sel ? mem1[rd_addr] : mem0[rd_addr];
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always @(posedge clk) begin
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if (rst) begin
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active_sel <= 1'b0;
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swapped <= 1'b0;
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fill_done_latched <= 1'b0;
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consume_done_latched <= 1'b0;
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end else begin
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swapped <= 1'b0;
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if (fill_done) fill_done_latched <= 1'b1;
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if (consume_done) consume_done_latched <= 1'b1;
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if (do_swap) begin
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active_sel <= ~active_sel;
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swapped <= 1'b1;
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fill_done_latched <= 1'b0;
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consume_done_latched <= 1'b0;
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end
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end
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end
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endmodule
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