micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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1.8 KiB
| 1 | metric | n_slots2 | n_slots4 | unit | classification |
|---|---|---|---|---|---|
| 2 | total_cycles | 52161 | 49430 | cycles | INTEGRATED BENCHMARK |
| 3 | tiles_delivered | 4096 | 4096 | tiles | INTEGRATED BENCHMARK |
| 4 | slot_cycle_budget | 104322 | 197720 | slot-cycles (N_SLOTS*total_cycles) | DERIVED |
| 5 | useful_mac_cycles | 4080 | 4078 | slot-cycles (tile-delivery events summed across slots) | INTEGRATED BENCHMARK |
| 6 | useful_mac_cycles_pct | 3.91 | 2.06 | percent of slot_cycle_budget | DERIVED |
| 7 | weight_stall_cycles | 86464 | 179756 | slot-cycles | INTEGRATED BENCHMARK |
| 8 | weight_stall_pct | 82.88 | 90.91 | percent of slot_cycle_budget | DERIVED |
| 9 | per_slot_idle_cycles_sum | 1072 | 1772 | slot-cycles (sum of total_cycles-busy_cycles per slot) | DERIVED |
| 10 | per_slot_idle_pct | 1.03 | 0.90 | percent of slot_cycle_budget | DERIVED |
| 11 | unaccounted_residual_slot_cycles | 12706 | 12114 | slot-cycles | DERIVED |
| 12 | unaccounted_residual_pct | 12.18 | 6.13 | percent of slot_cycle_budget (plausibly activation-wait + pipeline/tile-boundary bubbles + dispatch overhead -- NOT separately isolated this round; also includes a small ~16-tile/slot-cycle discrepancy between the two independent tile-delivery counters used, itself unexplained and disclosed rather than papered over) | DERIVED |
| 13 | startup_cycles | 56 | 56 | cycles (before first tile delivered anywhere) | INTEGRATED BENCHMARK |
| 14 | drain_cycles | 32 | 32 | cycles (after last tile delivered until completion) | INTEGRATED BENCHMARK |
| 15 | sustained_mac_per_cycle | 0.6282 | 0.6629 | MAC/cycle | INTEGRATED BENCHMARK |
| 16 | theoretical_peak_mac_per_cycle | 16 | 32 | MAC/cycle | THEORETICAL |
| 17 | processor_utilization_pct | 3.93 | 2.07 | percent (sustained/theoretical_peak) | DERIVED |
| 18 | active_slots_0_pct | 0.03 | 0.03 | percent of cycles | INTEGRATED BENCHMARK |
| 19 | active_slots_1_pct | 2.00 | 0.03 | percent of cycles | INTEGRATED BENCHMARK |
| 20 | active_slots_2_pct | 97.97 | 0.66 | percent of cycles | INTEGRATED BENCHMARK |
| 21 | active_slots_3_pct | NA | 2.07 | percent of cycles | INTEGRATED BENCHMARK |
| 22 | active_slots_4_pct | NA | 97.22 | percent of cycles | INTEGRATED BENCHMARK |