micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
181 lines
7.8 KiB
Plaintext
181 lines
7.8 KiB
Plaintext
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 40/43848 0%
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Info: logic LUTs: 16/43848 0%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 16/ 5481 0%
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Info: RAMW LUTs: 8/10962 0%
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Info: Total DFFs: 56/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 32 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x0abbe4f5
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 56/ 43848 0%
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Info: TRELLIS_COMB: 42/ 43848 0%
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Info: TRELLIS_RAMW: 4/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 45 cells, random placement wirelen = 4323.
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Info: at initial placer iter 0, wirelen = 1337
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Info: at initial placer iter 1, wirelen = 1031
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Info: at initial placer iter 2, wirelen = 967
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Info: at initial placer iter 3, wirelen = 962
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Info: Running main analytical placer, max placement attempts per cell = 10000.
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Info: at iteration #1, type ALL: wirelen solved = 959, spread = 1017, legal = 1022; time = 0.00s
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Info: HeAP Placer Time: 0.02s
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Info: of which solving equations: 0.00s
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Info: of which spreading cells: 0.00s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 33, wirelen = 1022
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Info: at iteration #5: temp = 0.000000, timing cost = 10, wirelen = 813
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Info: at iteration #10: temp = 0.000000, timing cost = 23, wirelen = 796
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Info: at iteration #11: temp = 0.000000, timing cost = 14, wirelen = 810
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Info: SA placement time 0.01s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 654.02 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.33 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.80 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 10971, 11010) |*********+
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Info: [ 11010, 11049) |
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Info: [ 11049, 11088) |+
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Info: [ 11088, 11127) |************+
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Info: [ 11127, 11166) |
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Info: [ 11166, 11205) |*************+
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Info: [ 11205, 11244) |************************************************************
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Info: [ 11244, 11283) |
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Info: [ 11283, 11322) |******+
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Info: [ 11322, 11361) |***+
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Info: [ 11361, 11400) |***+
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Info: [ 11400, 11439) |******+
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Info: [ 11439, 11478) |
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Info: [ 11478, 11517) |******+
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Info: [ 11517, 11556) |**+
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Info: [ 11556, 11595) |
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Info: [ 11595, 11634) |*************+
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Info: [ 11634, 11673) |
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Info: [ 11673, 11712) |
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Info: [ 11712, 11751) |**********+
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Info: Checksum: 0x67991a37
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 300 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 334 | 32 302 | 32 302 | 0| 0.10 0.10|
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Info: Routing complete.
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Info: Router1 time 0.10s
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Info: Checksum: 0xcdac7e72
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source lfsr_TRELLIS_FF_Q_16.Q
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Info: routing 0.95 1.35 Net fill_addr_flat[1] (36,36) -> (35,37)
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Info: Sink dut.GEN_SLOT[0].mem.0.0$DPRAM_COMB0.B
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:27.24-27.29
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Info: logic 0.18 1.53 Source dut.GEN_SLOT[0].mem.0.0$DPRAM_COMB0.F
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Info: routing 0.12 1.65 Net dut.GEN_SLOT[0].mem.0.0_DO[0] (35,37) -> (35,37)
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Info: Sink dut.GEN_SLOT[0].rd_data_reg_TRELLIS_FF_Q_7.DI
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Info: setup 0.00 1.65 Source dut.GEN_SLOT[0].rd_data_reg_TRELLIS_FF_Q_7.DI
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Info: 0.57 ns logic, 1.07 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source seed[5]$tr_io.O
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Info: routing 2.80 2.80 Net seed[5]$TRELLIS_IO_IN (90,35) -> (34,35)
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Info: Sink seed_LUT4_B_Z_LUT4_Z_4.B
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:14.23-14.27
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Info: logic 0.18 2.98 Source seed_LUT4_B_Z_LUT4_Z_4.F
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Info: routing 0.12 3.10 Net seed_LUT4_B_Z[5] (34,35) -> (34,35)
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Info: Sink lfsr_TRELLIS_FF_Q_22.DI
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Info: setup 0.00 3.10 Source lfsr_TRELLIS_FF_Q_22.DI
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Info: 0.18 ns logic, 2.92 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_4.Q
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Info: routing 2.73 3.13 Net checksum[4]$TRELLIS_IO_OUT (33,36) -> (90,35)
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Info: Sink checksum[4]$tr_io.I
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:40.15-40.18
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Info: 0.40 ns logic, 2.73 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 607.16 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.10 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.13 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 10853, 10901) |************
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Info: [ 10901, 10949) |*****
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Info: [ 10949, 10997) |*
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Info: [ 10997, 11045) |
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Info: [ 11045, 11093) |****
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Info: [ 11093, 11141) |****
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Info: [ 11141, 11189) |***************************
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Info: [ 11189, 11237) |************
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Info: [ 11237, 11285) |*
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Info: [ 11285, 11333) |************
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Info: [ 11333, 11381) |***************
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Info: [ 11381, 11429) |**********
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Info: [ 11429, 11477) |*****
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Info: [ 11477, 11525) |***************
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Info: [ 11525, 11573) |***
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Info: [ 11573, 11621) |*************
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Info: [ 11621, 11669) |
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Info: [ 11669, 11717) |********
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Info: [ 11717, 11765) |****
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Info: [ 11765, 11813) |*******
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Info: Program finished normally.
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