Info: Logic utilisation before packing:
Info:     Total LUT4s:        40/43848     0%
Info:         logic LUTs:     16/43848     0%
Info:         carry LUTs:      0/43848     0%
Info:           RAM LUTs:     16/ 5481     0%
Info:          RAMW LUTs:      8/10962     0%

Info:      Total DFFs:        56/43848     0%

Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     32 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x0abbe4f5

Info: Device utilisation:
Info: 	          TRELLIS_IO:      18/    245     7%
Info: 	                DCCA:       1/     56     1%
Info: 	              DP16KD:       0/    108     0%
Info: 	          MULT18X18D:       0/     72     0%
Info: 	              ALU54B:       0/     36     0%
Info: 	             EHXPLLL:       0/      4     0%
Info: 	             EXTREFB:       0/      2     0%
Info: 	                DCUA:       0/      2     0%
Info: 	           PCSCLKDIV:       0/      2     0%
Info: 	             IOLOGIC:       0/    160     0%
Info: 	            SIOLOGIC:       0/     85     0%
Info: 	                 GSR:       0/      1     0%
Info: 	               JTAGG:       0/      1     0%
Info: 	                OSCG:       0/      1     0%
Info: 	               SEDGA:       0/      1     0%
Info: 	                 DTR:       0/      1     0%
Info: 	             USRMCLK:       0/      1     0%
Info: 	             CLKDIVF:       0/      4     0%
Info: 	           ECLKSYNCB:       0/     10     0%
Info: 	             DLLDELD:       0/      8     0%
Info: 	              DDRDLL:       0/      4     0%
Info: 	             DQSBUFM:       0/     10     0%
Info: 	     TRELLIS_ECLKBUF:       0/      8     0%
Info: 	        ECLKBRIDGECS:       0/      2     0%
Info: 	                DCSC:       0/      2     0%
Info: 	          TRELLIS_FF:      56/  43848     0%
Info: 	        TRELLIS_COMB:      42/  43848     0%
Info: 	        TRELLIS_RAMW:       4/   5481     0%

Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 45 cells, random placement wirelen = 4323.
Info:     at initial placer iter 0, wirelen = 1337
Info:     at initial placer iter 1, wirelen = 1031
Info:     at initial placer iter 2, wirelen = 967
Info:     at initial placer iter 3, wirelen = 962
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info:     at iteration #1, type ALL: wirelen solved = 959, spread = 1017, legal = 1022; time = 0.00s
Info: HeAP Placer Time: 0.02s
Info:   of which solving equations: 0.00s
Info:   of which spreading cells: 0.00s
Info:   of which strict legalisation: 0.00s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 33, wirelen = 1022
Info:   at iteration #5: temp = 0.000000, timing cost = 10, wirelen = 813
Info:   at iteration #10: temp = 0.000000, timing cost = 23, wirelen = 796
Info:   at iteration #11: temp = 0.000000, timing cost = 14, wirelen = 810 
Info: SA placement time 0.01s

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 654.02 MHz (PASS at 80.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.33 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 4.80 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 10971,  11010) |*********+
Info: [ 11010,  11049) | 
Info: [ 11049,  11088) |+
Info: [ 11088,  11127) |************+
Info: [ 11127,  11166) | 
Info: [ 11166,  11205) |*************+
Info: [ 11205,  11244) |************************************************************ 
Info: [ 11244,  11283) | 
Info: [ 11283,  11322) |******+
Info: [ 11322,  11361) |***+
Info: [ 11361,  11400) |***+
Info: [ 11400,  11439) |******+
Info: [ 11439,  11478) | 
Info: [ 11478,  11517) |******+
Info: [ 11517,  11556) |**+
Info: [ 11556,  11595) | 
Info: [ 11595,  11634) |*************+
Info: [ 11634,  11673) | 
Info: [ 11673,  11712) | 
Info: [ 11712,  11751) |**********+
Info: Checksum: 0x67991a37
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 300 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:        334 |       32        302 |   32   302 |         0|       0.10       0.10|
Info: Routing complete.
Info: Router1 time 0.10s
Info: Checksum: 0xcdac7e72

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info:       type curr  total name
Info:   clk-to-q  0.40  0.40 Source lfsr_TRELLIS_FF_Q_16.Q
Info:    routing  0.95  1.35 Net fill_addr_flat[1] (36,36) -> (35,37)
Info:                          Sink dut.GEN_SLOT[0].mem.0.0$DPRAM_COMB0.B
Info:                          Defined in:
Info:                               hardware/v2/nms/synthesis/harness_nms_weight_direct.v:27.24-27.29
Info:      logic  0.18  1.53 Source dut.GEN_SLOT[0].mem.0.0$DPRAM_COMB0.F
Info:    routing  0.12  1.65 Net dut.GEN_SLOT[0].mem.0.0_DO[0] (35,37) -> (35,37)
Info:                          Sink dut.GEN_SLOT[0].rd_data_reg_TRELLIS_FF_Q_7.DI
Info:      setup  0.00  1.65 Source dut.GEN_SLOT[0].rd_data_reg_TRELLIS_FF_Q_7.DI
Info: 0.57 ns logic, 1.07 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info:       type curr  total name
Info:     source  0.00  0.00 Source seed[5]$tr_io.O
Info:    routing  2.80  2.80 Net seed[5]$TRELLIS_IO_IN (90,35) -> (34,35)
Info:                          Sink seed_LUT4_B_Z_LUT4_Z_4.B
Info:                          Defined in:
Info:                               hardware/v2/nms/synthesis/harness_nms_weight_direct.v:14.23-14.27
Info:      logic  0.18  2.98 Source seed_LUT4_B_Z_LUT4_Z_4.F
Info:    routing  0.12  3.10 Net seed_LUT4_B_Z[5] (34,35) -> (34,35)
Info:                          Sink lfsr_TRELLIS_FF_Q_22.DI
Info:      setup  0.00  3.10 Source lfsr_TRELLIS_FF_Q_22.DI
Info: 0.18 ns logic, 2.92 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info:       type curr  total name
Info:   clk-to-q  0.40  0.40 Source chk_TRELLIS_FF_Q_4.Q
Info:    routing  2.73  3.13 Net checksum[4]$TRELLIS_IO_OUT (33,36) -> (90,35)
Info:                          Sink checksum[4]$tr_io.I
Info:                          Defined in:
Info:                               hardware/v2/nms/synthesis/harness_nms_weight_direct.v:40.15-40.18
Info: 0.40 ns logic, 2.73 ns routing

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 607.16 MHz (PASS at 80.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.10 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 3.13 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 10853,  10901) |************ 
Info: [ 10901,  10949) |***** 
Info: [ 10949,  10997) |* 
Info: [ 10997,  11045) | 
Info: [ 11045,  11093) |**** 
Info: [ 11093,  11141) |**** 
Info: [ 11141,  11189) |*************************** 
Info: [ 11189,  11237) |************ 
Info: [ 11237,  11285) |* 
Info: [ 11285,  11333) |************ 
Info: [ 11333,  11381) |*************** 
Info: [ 11381,  11429) |********** 
Info: [ 11429,  11477) |***** 
Info: [ 11477,  11525) |*************** 
Info: [ 11525,  11573) |*** 
Info: [ 11573,  11621) |************* 
Info: [ 11621,  11669) | 
Info: [ 11669,  11717) |******** 
Info: [ 11717,  11765) |**** 
Info: [ 11765,  11813) |******* 

Info: Program finished normally.