New n8_system_ddr3_top.v: a real, permanent, named top-level (not a
build-time -generic override), byte-for-byte the same RTL as
n16_system_ddr3_top.v with N_GROUPS defaulting to 2. Real, full P&R
under this file's own name reproduces EXP-0095's own generic-override
result exactly: WNS=0.000ns, WHS=+0.017ns, 0 failing setup endpoints,
64 DSP48E1/26.7%, 12535 LUTs/19.77%.
New tb_n8_system_ddr3.v (real DDR3-model methodology, adapted from
tb_n16_system_ddr3.v, M=16 positions covering every one of the 2
groups x 4 PEs x 2 lanes exactly once): real functional xsim, 16/16
PASS, 0 errors -- closes the real functional-verification gap this
specific N previously had.
N=8 is now BOTH functionally verified AND timing-closed under its own
permanent name -- the real, definitive deployment target. N=2 kept as
a documented, valid fallback; N=16 kept as documented, functionally-
verified-but-not-timing-closed future work, not abandoned.
docs/PHYSICAL_REALIZATION.md, docs/ARCHITECTURE_ANALYSIS.md,
docs/PINOUT.md updated to reflect N=8 as the current real signoff.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
Re-measured ddr_prefetch_mgr.v's (EXP-0083) real benefit against the
now-closed 32-bit DDR3 channel (EXP-0086), per this project's own
standing plan. Real result: the 2.86% benefit measured at the old
16-bit channel is GONE at 32-bit (WITH: 100663.1335ns vs WITHOUT:
100656.6835ns -- a 0.0064% regression, statistically a wash). The
wider channel's lower per-tile latency already absorbs the gap the
look-ahead prefetch used to hide. Kept wired in for correctness/
timing-neutrality (real P&R already signs off with it included), but
it's no longer a real performance win. Updated docs/ARCHITECTURE_
ANALYSIS.md and docs/PHYSICAL_REALIZATION.md accordingly.
Found and fixed 3 real testbench/simulation-setup bugs along the way:
- tb_n2_system_ddr3.v and tb_mig_native_adapter.v still had a stale
CLKIN_PERIOD=2900 (the FAILED EXP-0084 clock period) instead of the
current real, closed 3225ps (EXP-0086).
- tb_n2_system_ddr3.v used SystemVerilog-only $signed(8'(...)) cast
syntax, invalid for xvlog's default plain-Verilog mode -- fixed via
an intermediate 8-bit reg.
- Building a fresh sim_1 fileset needs the real MIG simulation
dependency set added explicitly (mig_7series_0_mig.v is marked
USED_IN_SIMULATION=0 in the project since testbenches bypass the
public wrapper); verilog_define is a fileset-level property, not
per-file, in this Vivado version.
New measurement-only fork (not part of the real synthesis target, per
fork-before-promote discipline): packed_slot_noprefetch.v +
tb_n2_system_ddr3_noprefetch.v, reproducing the pre-EXP-0083 direct
per-tile activation-fetch sequencing for a fair A/B baseline.
Also adds docs/BOM.md and docs/PINOUT.md: a real component list (DDR3
x2, flash, FPGA already verified; clk_ref oscillator and an ESP32-S3-
WROOM-1 module newly verified in-stock on LCSC; sys_clk oscillator
flagged as needing a custom-programmed order, no off-the-shelf SKU at
the required 310.077MHz) and a consolidated, board-layout-ready pinout
extract of PHYSICAL_REALIZATION.md's own pin tables.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
micheleandClaude Sonnet 5