FPGA-Neural

103 Commits 5 Branches 1 Tag

103 Commits

Author	SHA1	Message	Date
micheleandClaude Sonnet 5	896f56c675	fix: correct byte/word address conversion in neuron_memory_tb preload tasks preload_vector and preload_weights wrote using base as a word address instead of a byte address (base + (k>>1) instead of (base>>1) + (k>>1)), misaligning X/W data in PSRAM relative to what int8_memory_access expects. Also adds a PATTERN test (X=1..32) to exercise mixed even/odd byte reads and catch this class of bug going forward. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt	2026-09-02 14:08:13 +02:00
michele	16769eaa4b	working with memory	2026-09-02 13:09:20 +02:00
michele	d4ae2417a4	test: validate parametric 32x4 layer with parallelism 8	2026-09-02 09:27:04 +02:00

Author

SHA1

Message

Date

micheleandClaude Sonnet 5

896f56c675

fix: correct byte/word address conversion in neuron_memory_tb preload tasks

preload_vector and preload_weights wrote using base as a word address
instead of a byte address (base + (k>>1) instead of (base>>1) + (k>>1)),
misaligning X/W data in PSRAM relative to what int8_memory_access expects.
Also adds a PATTERN test (X=1..32) to exercise mixed even/odd byte reads
and catch this class of bug going forward.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt

2026-09-02 14:08:13 +02:00

michele

16769eaa4b

working with memory

2026-09-02 13:09:20 +02:00

michele

d4ae2417a4

test: validate parametric 32x4 layer with parallelism 8

2026-09-02 09:27:04 +02:00