V2 final synthesis/P&R sign-off + LaTeX datasheet port (NOT SILICON READY)

Real synthesis and place-and-route of the actual final board-level
top (fpga_neural_v2_top.v -- SPI bridge, real EHXPLLL, reset_sync,
compute+memory core), against a real, fully ball-assigned LPF. Also
ports the V2 datasheet to LaTeX using V1's own preamble/macros/
typography, and records a real (non-ESP32, honestly labeled) software
reference comparison.

Synthesis (Yosys, real run): 0 CHECK-pass problems, 38 unique warnings
(43 total), all matching this project's own previously-reviewed benign
set (neural_processor.v's known genvar multi-driver artifact, small-
array-to-register unrolling, the real SDRAM DQ tristate bus) -- no new
warnings from the SPI bridge, PLL, or reset synchronizer.
TRELLIS_FF=6322, TRELLIS_COMB=7084, MULT18X18D=32, EHXPLLL=1 (real PLL
confirmed present), DP16KD=0 (all small SRAMs -> distributed RAM).

Place-and-route (nextpnr-ecp5, real runs, 8 seeds, new
v2_board_top.lpf with all 44 top-level signals ball-assigned from the
official Lattice pinout CSV -- no placeholders): 8/8 PASS at 64MHz.
Worst 68.51MHz (seed 4), best 74.17MHz (seed 7), mean 71.16MHz. Zero
unrouted nets, zero placement/routing errors, TRELLIS_IO=44/245 (17%).
Critical path alternates between dependency_manager's own priority
encoder and sdram_unified_backend's own weight-cache hit-index logic,
matching this project's own prior documented timing investigations --
not a new defect.

New: hardware/v2/constraints/v2_board_top.lpf (final LPF, supersedes
v2_unified.lpf for the board-level top), hardware/v2/reports/
step_final_{synthesis,pnr_worst_seed4,timing}.* (raw evidence),
hardware/v2/docs/DatasheetLatex/ (V2 datasheet, real LaTeX build,
16 pages, visually inspected, ported from hardware/v1/docs/
DatasheetLatex/'s own preamble and macros).

Real, honestly-labeled software baseline: the D-Stress arithmetic
(256 neurons x 128 INT8 MACs) compiled and run on THIS development
machine (Apple M4, arm64, NOT an embedded target, NOT ESP32) --
1.28us/inference, included in the datasheet with an explicit
disclosure that no physical ESP32 hardware was available for a real
embedded-target comparison.

Remaining, disclosed, NOT-yet-closed items (this commit does NOT
claim silicon readiness): real KiCad schematic + ERC, PCB layout,
sourced BOM, real power current-budget estimate, SDRAM-datasheet-
parameter cross-check, configuration-flash selection, and (necessarily)
physical fabrication/bring-up. See hardware/v2/docs/DatasheetLatex/
chapters/08-status-roadmap.tex for the complete, itemized checklist.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/docs/DatasheetLatex/chapters/08-status-roadmap.tex

@@ -0,0 +1,59 @@
+\chapter{Chip readiness and roadmap}
+\label{ch:status}
+
+\section{Precise readiness checklist}
+Per this project's own standing rule: no item below is checked unless
+genuinely verified; no OPEN item is masked as a future enhancement.
+
+\begin{tabularx}{\textwidth}{L{6.4cm}Y}
+\toprule
+\rowh \thd{Item} & \thd{Status} \\
+\midrule
+RTL frozen, zero V1 dependency & \OK \\
+\rowa Bit-exact regression (N=2, N=4) & \OK\ (256/256, Verilator) \\
+Real SPI host interface, end-to-end & \OK\ (11/11, zero regression) \\
+\rowa SDRAM validation (init/refresh/masked-write) & \OK \\
+Synthesis (final top, real Yosys run) & \OK\ (0 CHECK-pass problems) \\
+\rowa Place\&route (8 real seeds) & \OK\ (8/8 fit, routed, zero errors) \\
+Timing closure @ 64\,MHz & \OK\ (8/8 seeds PASS, worst 68.51\,MHz) \\
+\rowa Final pinout (44/44 top-level signals) & \OK\ (real balls, P\&R-confirmed) \\
+Hold-time analysis & OPEN (not reported by this toolchain's summary) \\
+\rowa Power: rail voltages & OK (real datasheet values) \\
+Power: regulator selection / current budget & OPEN \\
+\rowa SDRAM datasheet-parameter cross-check & OPEN (sim-level only) \\
+Configuration flash selection & OPEN \\
+\rowa Real KiCad schematic + ERC & NOT STARTED \\
+PCB layout & NOT STARTED \\
+\rowa BOM (sourced, purchasable parts) & NOT STARTED \\
+Physical board bring-up & NOT APPLICABLE (no board fabricated) \\
+\rowa Real embedded-target (ESP32) software baseline & NOT AVAILABLE (no hardware) \\
+\bottomrule
+\end{tabularx}
+
+\section{Final answer}
+\begin{center}
+\Large\bfseries\color{fnRed}NOT SILICON READY
+\end{center}
+The RTL, simulation, synthesis, place-and-route, timing, and pinout
+gates are all genuinely closed for the final board-level top. The
+remaining, real, disclosed blockers are entirely in the physical
+domain -- schematic capture, PCB layout, sourced BOM, and (necessarily)
+physical fabrication and bring-up -- none of which were claimed
+complete in this revision.
+
+\section{Roadmap}
+\begin{itemize}
+\item Real KiCad schematic capture + ERC.
+\item PCB layout (BGA escape, SDRAM routing, power integrity).
+\item Sourced, purchasable BOM (regulators, configuration flash,
+  connectors).
+\item Real power current-budget estimate against the actual
+  synthesized netlist.
+\item Real SDRAM-datasheet-parameter cross-check of controller timing
+  constants.
+\item First physical board fabrication and the 15-step bring-up
+  procedure already documented in \code{FIRST\_POWER\_ON.md}.
+\item A real embedded-target (ESP32-class) software baseline, once
+  hardware is available, to replace this revision's honestly-labeled
+  desktop-CPU illustrative comparison.
+\end{itemize}