V2 final synthesis/P&R sign-off + LaTeX datasheet port (NOT SILICON READY)

Real synthesis and place-and-route of the actual final board-level
top (fpga_neural_v2_top.v -- SPI bridge, real EHXPLLL, reset_sync,
compute+memory core), against a real, fully ball-assigned LPF. Also
ports the V2 datasheet to LaTeX using V1's own preamble/macros/
typography, and records a real (non-ESP32, honestly labeled) software
reference comparison.

Synthesis (Yosys, real run): 0 CHECK-pass problems, 38 unique warnings
(43 total), all matching this project's own previously-reviewed benign
set (neural_processor.v's known genvar multi-driver artifact, small-
array-to-register unrolling, the real SDRAM DQ tristate bus) -- no new
warnings from the SPI bridge, PLL, or reset synchronizer.
TRELLIS_FF=6322, TRELLIS_COMB=7084, MULT18X18D=32, EHXPLLL=1 (real PLL
confirmed present), DP16KD=0 (all small SRAMs -> distributed RAM).

Place-and-route (nextpnr-ecp5, real runs, 8 seeds, new
v2_board_top.lpf with all 44 top-level signals ball-assigned from the
official Lattice pinout CSV -- no placeholders): 8/8 PASS at 64MHz.
Worst 68.51MHz (seed 4), best 74.17MHz (seed 7), mean 71.16MHz. Zero
unrouted nets, zero placement/routing errors, TRELLIS_IO=44/245 (17%).
Critical path alternates between dependency_manager's own priority
encoder and sdram_unified_backend's own weight-cache hit-index logic,
matching this project's own prior documented timing investigations --
not a new defect.

New: hardware/v2/constraints/v2_board_top.lpf (final LPF, supersedes
v2_unified.lpf for the board-level top), hardware/v2/reports/
step_final_{synthesis,pnr_worst_seed4,timing}.* (raw evidence),
hardware/v2/docs/DatasheetLatex/ (V2 datasheet, real LaTeX build,
16 pages, visually inspected, ported from hardware/v1/docs/
DatasheetLatex/'s own preamble and macros).

Real, honestly-labeled software baseline: the D-Stress arithmetic
(256 neurons x 128 INT8 MACs) compiled and run on THIS development
machine (Apple M4, arm64, NOT an embedded target, NOT ESP32) --
1.28us/inference, included in the datasheet with an explicit
disclosure that no physical ESP32 hardware was available for a real
embedded-target comparison.

Remaining, disclosed, NOT-yet-closed items (this commit does NOT
claim silicon readiness): real KiCad schematic + ERC, PCB layout,
sourced BOM, real power current-budget estimate, SDRAM-datasheet-
parameter cross-check, configuration-flash selection, and (necessarily)
physical fabrication/bring-up. See hardware/v2/docs/DatasheetLatex/
chapters/08-status-roadmap.tex for the complete, itemized checklist.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/docs/DatasheetLatex/chapters/04-host-interface.tex

@@ -0,0 +1,47 @@
+\chapter{Host interface (SPI)}
+
+\code{spi\_host\_bridge.v} is the real, physical host interface for
+V2's board-level top (\code{fpga\_neural\_v2\_top.v}). It replaces the
+internal 110-pin \code{reg\_*} bus (a simulation/testbench convenience
+that must never be represented as a physical board interface) with 4
+real pins: \sig{spi\_sclk}, \sig{spi\_mosi}, \sig{spi\_miso},
+\sig{spi\_cs\_n}. Mode 0 (CPOL=0/CPHA=0), MSB-first, one opcode per
+CS-low period.
+
+\section{Opcodes}
+\begin{tabularx}{\textwidth}{L{2cm}L{3.2cm}Y}
+\toprule
+\rowh \thd{Opcode} & \thd{Name} & \thd{Function} \\
+\midrule
+\op{0x10} & \op{WRITE\_JOB} & 15-byte payload: node id, required
+  dependency count, producer ids, \sig{x\_base}, \sig{w\_base},
+  \sig{n\_tiles}, \sig{result\_addr}. Registers one Dependency Manager
+  job; \sig{reg\_valid} is held until the same-cycle
+  \sig{reg\_valid}\,\&\&\,\sig{reg\_ready} acceptance fires. \\
+\rowa \op{0x01} & \op{WRITE\_MEM} & word-addressed raw SDRAM write,
+  via a second, arbitrated AR port. \\
+\op{0x02} & \op{READ\_MEM} & word-addressed raw SDRAM read. \\
+\rowa \op{0x20} & \op{STATUS} & 1-byte status: job-busy, mem-busy,
+  sticky last-job-accepted. \\
+\op{0x0F} & \op{RESET} & pulses a soft-reset into the compute+memory
+  core (not the SPI bridge's own state, avoiding a self-reset hazard). \\
+\bottomrule
+\end{tabularx}
+
+\section{Verification}
+\label{sec:host}
+The protocol engine is verified in two independent ways:
+\begin{itemize}
+\item \textbf{Isolated}: \code{tb\_spi\_host\_bridge.v}, 18/18 PASS --
+  every opcode, including a real DQM-style byte-masked
+  \op{WRITE\_MEM}.
+\item \textbf{End-to-end}: \code{tb\_fpga\_neural\_v2\_top\_smoke.v},
+  11/11 PASS -- a single job, two jobs back-to-back, two jobs across a
+  realistic $\sim$85\,\textmu s SPI-paced gap, and a parametric sweep
+  of inter-job gaps (100\,ns / 5\,000\,ns / 50\,000\,ns), all checked
+  bit-exact against a software golden model via a real SDRAM backdoor
+  readback.
+\end{itemize}
+Both regressions pass with \textbf{zero regression} to the existing
+N=2/N=4 D-Stress bit-exact baseline (identical cycle counts before and
+after every fix applied during this interface's own development).