V2 final synthesis/P&R sign-off + LaTeX datasheet port (NOT SILICON READY)

Real synthesis and place-and-route of the actual final board-level
top (fpga_neural_v2_top.v -- SPI bridge, real EHXPLLL, reset_sync,
compute+memory core), against a real, fully ball-assigned LPF. Also
ports the V2 datasheet to LaTeX using V1's own preamble/macros/
typography, and records a real (non-ESP32, honestly labeled) software
reference comparison.

Synthesis (Yosys, real run): 0 CHECK-pass problems, 38 unique warnings
(43 total), all matching this project's own previously-reviewed benign
set (neural_processor.v's known genvar multi-driver artifact, small-
array-to-register unrolling, the real SDRAM DQ tristate bus) -- no new
warnings from the SPI bridge, PLL, or reset synchronizer.
TRELLIS_FF=6322, TRELLIS_COMB=7084, MULT18X18D=32, EHXPLLL=1 (real PLL
confirmed present), DP16KD=0 (all small SRAMs -> distributed RAM).

Place-and-route (nextpnr-ecp5, real runs, 8 seeds, new
v2_board_top.lpf with all 44 top-level signals ball-assigned from the
official Lattice pinout CSV -- no placeholders): 8/8 PASS at 64MHz.
Worst 68.51MHz (seed 4), best 74.17MHz (seed 7), mean 71.16MHz. Zero
unrouted nets, zero placement/routing errors, TRELLIS_IO=44/245 (17%).
Critical path alternates between dependency_manager's own priority
encoder and sdram_unified_backend's own weight-cache hit-index logic,
matching this project's own prior documented timing investigations --
not a new defect.

New: hardware/v2/constraints/v2_board_top.lpf (final LPF, supersedes
v2_unified.lpf for the board-level top), hardware/v2/reports/
step_final_{synthesis,pnr_worst_seed4,timing}.* (raw evidence),
hardware/v2/docs/DatasheetLatex/ (V2 datasheet, real LaTeX build,
16 pages, visually inspected, ported from hardware/v1/docs/
DatasheetLatex/'s own preamble and macros).

Real, honestly-labeled software baseline: the D-Stress arithmetic
(256 neurons x 128 INT8 MACs) compiled and run on THIS development
machine (Apple M4, arm64, NOT an embedded target, NOT ESP32) --
1.28us/inference, included in the datasheet with an explicit
disclosure that no physical ESP32 hardware was available for a real
embedded-target comparison.

Remaining, disclosed, NOT-yet-closed items (this commit does NOT
claim silicon readiness): real KiCad schematic + ERC, PCB layout,
sourced BOM, real power current-budget estimate, SDRAM-datasheet-
parameter cross-check, configuration-flash selection, and (necessarily)
physical fabrication/bring-up. See hardware/v2/docs/DatasheetLatex/
chapters/08-status-roadmap.tex for the complete, itemized checklist.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/docs/DatasheetLatex/chapters/01-overview.tex

@@ -0,0 +1,64 @@
+\chapter{Overview}
+
+FPGA-Neural V2 succeeds V1 with three architectural changes, all
+frozen and verified in this revision:
+
+\begin{enumerate}
+\item \textbf{Neural multiprocessor}: N\_PROCESSORS (4, frozen
+  reference) independent Neural Processors instead of V1's single
+  engine, scheduled by a real dependency-graph Dependency Manager and
+  Neural Director.
+\item \textbf{Unified single-SDRAM memory}: one physical Alliance
+  Memory \code{AS4C4M16SA-6TIN} SDRAM serves weights, activations,
+  \emph{and} results. V1's PSRAM (\code{IS66WVE4M16EBLL-70BLI}) and
+  its controller are not part of V2's physical path at all.
+\item \textbf{Real physical host interface}: a from-scratch SPI
+  protocol engine (\code{spi\_host\_bridge.v}) replaces the internal
+  110-pin \code{reg\_*} testbench bus as the board-level top's own
+  physical interface.
+\end{enumerate}
+
+V1 itself (\code{hardware/v1/**}) is untouched and remains the golden,
+independently certified reference design; V2 shares no RTL file with
+it.
+
+\section{Document scope and status labels}
+\label{sec:status-labels}
+This datasheet distinguishes explicitly between:
+\begin{itemize}
+\item \textbf{RTL verified} -- verified through RTL simulation only.
+\item \textbf{Simulation verified} -- verified in simulation for the
+  specific configuration named.
+\item \textbf{Synthesis verified} -- synthesizes cleanly for the
+  target FPGA (Yosys, real run, zero unintended latches or
+  multi-driver issues beyond a small, previously-reviewed benign set).
+\item \textbf{P\&R verified} -- successfully placed, routed, and
+  timing-analyzed by nextpnr-ecp5 for a real, ball-assigned LPF.
+\item \textbf{Hardware designed} -- schematic/PCB electrically
+  designed but not fabricated.
+\item \textbf{Hardware validated} -- physically tested on fabricated
+  hardware.
+\item \textbf{Silicon validated} -- the actual physical FPGA has been
+  programmed and tested.
+\end{itemize}
+As of \datasheetdate, V2 is \textbf{RTL verified}, \textbf{simulation
+verified} (bit-exact), \textbf{synthesis verified}, and \textbf{P\&R
+verified}. No item in this datasheet is presented as hardware- or
+silicon-validated -- no fabricated V2 board exists. See
+Chapter~\ref{ch:status} for the complete, itemized status.
+
+\section{Frozen reference configuration}
+\begin{tabularx}{\textwidth}{L{4cm}Y}
+\toprule
+\rowh \thd{Parameter} & \thd{Value} \\
+\midrule
+FPGA & Lattice \code{LFE5U-45F-8BG381}, speed grade $-8$, CABGA381 \\
+\rowa N\_PROCESSORS & 4 (frozen reference; N=2 also fully validated) \\
+P\_IN & 8 (MAC width per processor) \\
+\rowa ACC\_WIDTH & 32 \\
+External memory & 1 $\times$ SDRAM, Alliance Memory \code{AS4C4M16SA-6TIN}, 8\,MB \\
+\rowa Oscillator & 16\,MHz (board-level, external) \\
+System clock & 64\,MHz, generated by a real ECP5 \code{EHXPLLL} \\
+\rowa Host interface & real SPI (4 pins), \code{spi\_host\_bridge.v} \\
+\bottomrule
+\end{tabularx}