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test: directed SDRAM boundary verification + SPI frequency sweep

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PRE-PCB CLOSURE Point 1: adds tb_sdram_boundary.v, a directed (not
randomized) regression covering address 0/1/last/last-1, an explicit
row-boundary crossing, all 3 inter-bank boundary crossings, the real
V2 memory-map region boundaries (weights/activations/results), and
every DQM byte-mask combination with explicit read-after-write.
21/21 PASS at both 64MHz and 166MHz, zero bugs found.

PRE-PCB CLOSURE Point 2: adds tb_spi_freq_sweep.v, a reproducible SPI
bit-rate sweep against the real fpga_neural_v2_top (osc_clk driven at
the real 64MHz clk_sys rate via the SIM PLL bypass). Found and fixed a
race in the new test harness itself (a fixed-time wait before reading
a WRITE_MEM/READ_MEM response, too short whenever a periodic AUTO
REFRESH delayed the backend) -- not a spi_host_bridge.v defect,
confirmed against tb_spi_host_bridge.v's own isolated regression.
Determined the real, deterministic CDC margin: the synchronizer
requires >=5 system-clock cycles per SPI bit (exactly 64MHz/5 =
12.8MHz); recommends SPI_MAX_VERIFIED=12MHz with real margin below
that hard edge.

Full writeup: hardware/v2/docs/PRE_PCB_CLOSURE_4POINT.md.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-06 19:42:37 +02:00
co-authored by Claude Sonnet 5
parent eb0b0f9170
commit c4763aab10
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hardware/v2/docs/PRE_PCB_CLOSURE_4POINT.md
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# FPGA-Neural V2 — FINAL 4-POINT PRE-PCB CLOSURE
Follows `PRE_PCB_VERIFICATION.md` (PRE-PCB VERIFIED baseline, commit
`d6376e8` + `8890b0a` + `eb0b0f9`). Closes the four remaining
practical items the user identified as still open before schematic
capture. Does not redesign the verified architecture; no working RTL
was modified as a result of this pass (see Point 2 for the one bug
found and fixed, which was in a NEW test harness, not in
`spi_host_bridge.v` itself).
---
## POINT 1 — Directed SDRAM boundary verification
New file: `hardware/v2/nms/sim/tb_sdram_boundary.v`.
Real Alliance Memory AS4C4M16SA-6TIN geometry (confirmed against
`sdram_controller.v`'s own address decode:
`addr_bank=addr[21:20]`, `addr_row=addr[19:8]`, `addr_col=addr[7:0]`):
4 banks × 4096 rows × 256 cols × 16 bits = 4M words = 8MB.
Coverage (21 checks, BURST_LEN=1 for exact single-word addressing):
- **Address boundaries**: 0x000000 (addr 0), 0x000001 (addr 1),
0x3FFFFF (last valid), 0x3FFFFE (last valid − 1).
- **Row boundary**: bank0/row10/col255 (last column of row 10) and
bank0/row11/col0 (first column of row 11).
- **Bank boundaries**: last address / first address at all 3
inter-bank crossings (bank0↔1, bank1↔2, bank2↔3).
- **Memory-map boundaries**: the real V2 map (weights@byte 0x010000,
activations@byte 0x200000, results@byte 0x300000) converted to this
controller's word addresses (word=byte/2) — weights base, last word
before activations, activations base, last word before results,
results base.
- **Byte-mask combinations, explicit read-after-write**: lower-byte-
only (wmask=2'b10), upper-byte-only (wmask=2'b01), both-bytes
(wmask=2'b00), using the requested deterministic patterns 0xAAAA,
0x5555, 0x0000, 0xFFFF.
All 17 boundary/adjacency addresses are written first, then read back
in **reversed** order with distinct address-derived patterns
(`addr[15:0] ^ 0xC3A5`) — this proves no write to any one address
corrupted any neighbour in the set, which is exactly the "adjacent
regions cannot corrupt each other" property requested, for every
boundary simultaneously.
### Exact results
```
$ verilator --binary --timing -Wno-fatal --top-module tb_sdram_boundary -o tb_bnd \
-GCLK_FREQ_MHZ=64 hardware/v2/nms/rtl/sdram_controller.v \
hardware/v2/nms/sim/sdram_model.v hardware/v2/nms/sim/tb_sdram_boundary.v
$ ./obj_dir/tb_bnd
=== 21/21 tests, 0 errors (tb_sdram_boundary, CLK_FREQ_MHZ=64) ===
ALL TESTS PASSED (tb_sdram_boundary, CLK_FREQ_MHZ=64)
```
Cross-checked at the legacy CLK_FREQ_MHZ=166 (same command with
`-GCLK_FREQ_MHZ=166`): **21/21 PASS, 0 errors**, identical.
Full per-address results at 64MHz (expected vs actual, all matched):
| Label | Address | Data |
|---|---|---|
| addr-0 | 0x000000 | 0xc3a5 |
| addr-1 | 0x000001 | 0xc3a4 |
| addr-last | 0x3fffff | 0x3c5a |
| addr-last-1 | 0x3ffffe | 0x3c5b |
| row10-lastcol | 0x000aff | 0xc95a |
| row11-firstcol | 0x000b00 | 0xc8a5 |
| bank0-last | 0x0fffff | 0x3c5a |
| bank1-first | 0x100000 | 0xc3a5 |
| bank1-last | 0x1fffff | 0x3c5a |
| bank2-first | 0x200000 | 0xc3a5 |
| bank2-last | 0x2fffff | 0x3c5a |
| bank3-first | 0x300000 | 0xc3a5 |
| weights-base | 0x008000 | 0x43a5 |
| weights-last(pre-act) | 0x0fffff | 0x3c5a |
| activations-base | 0x100000 | 0xc3a5 |
| activations-last(pre-res) | 0x17ffff | 0x3c5a |
| results-base | 0x180000 | 0xc3a5 |
| mask-lower-only | 0x001000 | 0xaa34 |
| mask-upper-only | 0x001000 | 0x5655 |
| mask-both-bytes | 0x001000 | 0xffff |
| pattern-5555-plain | 0x001001 | 0x5555 |
**No bug found.** Address decode, byte masking, and inter-region
adjacency are all correct at every tested boundary.
**RESULT: SDRAM directed boundaries: PASS.**
---
## POINT 2 — Verified SPI operating clock
New file: `hardware/v2/nms/sim/tb_spi_freq_sweep.v`. Instantiates the
REAL `fpga_neural_v2_top` (not spi_host_bridge in isolation) with
`osc_clk` driven at the real 64MHz `clk_sys` rate (the `SIM` PLL
bypass makes `clk_sys = osc_clk` directly, so driving `osc_clk` at
64MHz reproduces the real board's actual system-clock rate — unlike
`tb_fpga_neural_v2_top_smoke.v`, which uses a stale `CLK_FREQ_MHZ=80`
parameter left over from an earlier draft). SPI bit timing is a
runtime parameter (`SPI_FREQ_MHZ`), swept across candidate points.
Per-frequency coverage: single job submission, two jobs back-to-back,
two jobs with a realistic gap, a raw `WRITE_MEM`/`READ_MEM` round trip
over the actual SPI response path (not the backdoor SDRAM peek used
elsewhere), and 3 repeated single-job transactions — 10 checks total.
### A bug found and fixed — in the new test harness, not the RTL
The first sweep attempt (fixed `#2000`-real-time wait before clocking
out a `READ_MEM` response) failed once, at 2MHz, with the response's
MSB read back as 0 instead of 1 — every other bit correct. Before
concluding anything about the RTL, this was root-caused: the real
host-arb/SDRAM-controller backend latency (unlike
`tb_spi_host_bridge.v`'s own isolated unit test, which drives
`mem_rdata`/`mem_ready` from a simple behavioral mock with fixed
timing) genuinely varies cycle-to-cycle — a periodic AUTO REFRESH can
land during the request and push `mem_ready` later than the guessed
`#2000` margin. `tb_spi_host_bridge.v`'s own regression already proves
`spi_host_bridge.v`'s FIRST `READ_MEM` after reset delivers all 16
bits correctly when its own mock backend responds within that test's
own assumed timing — confirming the FSM logic itself is correct, and
the failure was this new harness's own race. **Fixed** by polling
`dut.u_spi_bridge.state` directly (`ST_MEM_ROUT`/`ST_IGNORE`) instead
of guessing a fixed real-time margin — eliminates the race entirely.
Re-ran the full sweep from 2MHz upward with this fix: no further
data-corruption failures at any frequency below the real CDC limit
(see below).
### Sweep results
| SPI_FREQ_MHZ | sysclk cycles/bit (64MHz) | Result |
|---|---|---|
| 2 | 32.0 | 10/10 PASS |
| 4 | 16.0 | 10/10 PASS |
| 8 | 8.0 | 10/10 PASS |
| 10 | 6.4 | 10/10 PASS |
| 12 | 5.33 | 10/10 PASS |
| 12.5 | 5.12 | 10/10 PASS |
| 12.8 | 5.0 (exact) | 10/10 PASS |
| 12.9 | 4.96 | FAIL (data corruption) + protocol FSM HANG (watchdog) |
| 13 | 4.92 | FAIL + HANG |
| 14 | 4.57 | FAIL + HANG |
| 15 | 4.27 | FAIL + HANG |
| 16 | 4.0 | FAIL + HANG |
| 20, 24, 32 | <4.0 | FAIL + HANG |
The breakpoint is **exact and deterministic**: 12.8MHz is precisely
64MHz/5 — the triple-flop CDC synchronizer plus edge-detect/FSM
reaction in `spi_host_bridge.v` requires at least 5 full system-clock
cycles per SPI bit period to reliably track `sclk`/`mosi`/`cs_n`
transitions. Below that, the synchronizer misses edges outright,
which doesn't just corrupt data (as briefly seen in the harness-race
case above) but eventually desyncs the byte-framing state machine
badly enough that it never reaches an expected state again — a real
protocol lockup, not merely wrong data. This is a genuine, real
property of the CDC design (not a bug — the double/triple-flop
synchronizer is standard, correct practice; it simply has a minimum
bit-period requirement, which every synchronous CDC scheme does), now
precisely measured rather than assumed.
### Distinguishing the three kinds of limit the mandate asks for
- **RTL/simulation limit (measured, this session)**: 12.8MHz exact
edge; 12MHz recommended verified operating point (real margin below
the hard edge: 5.33 vs the minimum 5.0 cycles/bit, ~6.7% headroom).
- **FPGA timing limit**: not applicable in the way P&R timing closure
applies to the internal 64MHz domain — the SPI pins are simple
registered/synchronized GPIO inputs (`IO_TYPE=LVCMOS33`, no special
timing constraint beyond the CDC margin above), and nextpnr-ecp5's
own timing analysis (section 5/6 of `PRE_PCB_VERIFICATION.md`) does
not model an external asynchronous SPI master's edge timing at all.
No FPGA-side P&R-derived limit beyond the CDC margin already found.
- **Board-level electrical limit**: **OPEN — not measured, cannot be
measured without real hardware.** Real trace length, connector/cable
capacitance, SPI master driver rise/fall time, ground bounce, and
actual metastability risk (this RTL simulation is deterministic and
cannot model metastability at all) are all real-world factors this
simulation does not and cannot capture. The 12MHz recommendation
below is a simulation-verified LOGICAL limit with margin, not a
physical hardware guarantee — bring-up step 11 in
`FIRST_POWER_ON.md` should still empirically confirm the real
achievable rate on the actual board.
**RESULT: SPI_MAX_VERIFIED = 12 MHz** (recommended operating point,
simulation-verified with real margin below the exact 12.8MHz
deterministic CDC edge). Do not exceed 12.8MHz under any circumstance;
do not treat 12.8MHz itself as a safe operating margin.
### Exact test commands
```
$ verilator --binary --timing -Wno-fatal -DSIM --top-module tb_spi_freq_sweep -o tb_spi \
-GSPI_FREQ_MHZ=12.0 <all V2 rtl/nms sources + tb_spi_freq_sweep.v>
$ ./obj_dir/tb_spi
=== SPI_FREQ_MHZ=12.000: 10/10 PASS ===
```
---
## POINT 3 — 16MHz oscillator MPN, frozen
**Decision: ECS Inc. International, `ECS-3225MV-160-BN-TR`.**
| Property | Value |
|---|---|
| Manufacturer / MPN | ECS Inc. International, `ECS-3225MV-160-BN-TR` |
| Type | Quartz crystal oscillator (XO), not a bare crystal — provides a direct digital clock output, no external oscillator circuit needed |
| Frequency | 16.000 MHz, matching `osc_clk`'s real ball (H5) and the LPF's `FREQUENCY PORT "osc_clk" 16 MHZ` constraint exactly |
| Package | 3225 SMD, 3.2mm × 2.5mm, 4-pad (standard, small, hand-placeable with a stencil; widely available) |
| Supply voltage | 3.3V — matches `osc_clk`'s LPF `IO_TYPE=LVCMOS33` exactly, no level-shifting needed |
| Output type | HCMOS/CMOS square wave — directly compatible with the ECP5's LVCMOS33 clock input requirement |
| Frequency stability | ±50 ppm (standard grade for this series) — comfortably adequate for an SDR SDRAM/SPI/PLL system with no tight external timing reference requirement |
| Duty cycle | Typically 45/55% to 40/60% (standard for this class of HCMOS XO; confirm exact figure against the current ECS datasheet at BOM lock) |
| Startup time | Typically ≤10ms (standard for a quartz XO of this type) |
| Temperature range | −40°C to +85°C (industrial) |
| Recommended decoupling | One 0.1µF ceramic capacitor directly across VDD/GND, placed as close as possible to the oscillator's supply pin — standard practice for this device class |
| Availability | High — ECS Inc. is a large, long-established oscillator manufacturer stocked at Digi-Key/Mouser; standard frequency/package combination |
Verified against the ECP5's own input-clock requirements: LVCMOS33
input, no minimum/maximum listed frequency constraint that 16MHz would
violate, matches the real, already-verified
`(* FREQUENCY_PIN_CLKI="16" *)`-driven `EHXPLLL` input in
`ecp5_pll_sys_clk.v` exactly.
**Caveat, honestly disclosed**: the exact terminal order-code suffix
(stability/voltage/output-enable option letters, here assumed `BN` for
3.3V HCMOS/standard stability) should be cross-checked against ECS's
current published datasheet at final BOM lock — normal, standard
due-diligence practice at that stage, not an open architectural
question. The manufacturer, series, frequency, package, and supply
voltage are the real, frozen decision.
**RESULT: 16MHz oscillator: `ECS-3225MV-160-BN-TR` (ECS Inc.), FROZEN.**
---
## POINT 4 — Power + JTAG support components
### FPGA power rails and regulators
**Assumption, explicitly flagged**: a 5V board input rail (typical
USB/wall-adapter supply) is assumed as the single external power
source all on-board regulators derive from — this was not specified
by the user and is a reasonable, common default, not a verified fact.
| Rail | Voltage | Regulator MPN | Topology | Current capability | Notes |
|---|---|---|---|---|---|
| FPGA core (VCC) | 1.1V ±5% | Texas Instruments `TPS562201DDCR` | Synchronous buck (switching), adjustable output via feedback resistor divider set for 1.1V | Up to 2A | Real dynamic current draw is OPEN (section 12 of `PRE_PCB_VERIFICATION.md`) — 2A capability is a real-datasheet-based worst-case engineering margin, not a measured requirement; a switching regulator (not an LDO) is used here because a 5V→1.1V LDO would dissipate excessive heat at any non-trivial current |
| FPGA VCCAUX | 2.5V ±5% | Texas Instruments `TLV1117-25IDCYR` | Linear (LDO), fixed 2.5V | 800mA | Fed from the same 5V input rail directly (not from the 3.3V rail) so the LDO retains adequate (~2.5V) dropout headroom |
| FPGA VCCIO (banks 6/7/8) | 3.3V | Texas Instruments `TLV1117-33IDCYR` | Linear (LDO), fixed 3.3V | 800mA | Also supplies the SDRAM, config flash, oscillator, and JTAG reference voltage (all real 3.3V devices per sections 10/11 of `PRE_PCB_VERIFICATION.md`) |
| SDRAM (AS4C4M16SA-6TIN) | 3.3V | Shared with VCCIO rail above | — | — | Real datasheet requirement, already confirmed |
| Config flash (W25Q32JVSSIQ) | 3.3V (within its 2.7-3.6V range) | Shared with VCCIO rail above | — | — | Real datasheet requirement, already confirmed |
| Oscillator (ECS-3225MV-160) | 3.3V | Shared with VCCIO rail above | — | — | Matches Point 3's own decision |
**Design margin**: the 1.1V buck's 2A capability and the 800mA LDOs
are real, datasheet-supported ratings well above any plausible
estimate for this design's actual utilization (7,084 LUT4-equiv,
6,322 FF, 32 MULT18X18D — a mid-size ECP5-45F design, not the whole
device near capacity), but per section 12's own honest disclosure,
the EXACT required current is still not computed from real
implementation data — these regulator choices provide comfortable
headroom against that unknown, not a precisely-sized budget.
### Passive components (frozen only where electrically required)
| Component | Value | Where |
|---|---|---|
| Decoupling (high-frequency) | 100nF (0.1µF) X7R ceramic, 0402/0603 | Distributed, one per VCC/VCCAUX/VCCIO power-pin group around the BGA, per Lattice's own Hardware Checklist guidance (already cited in `docs/pinouts.md`) |
| Decoupling (bulk) | 10µF X5R ceramic or tantalum | One per regulator output, close to each regulator |
| `PROGRAMN` pull-up | 10kΩ to VCCIO8 (3.3V) | Standard ECP5 practice — idle-high, momentary pulse low reconfigures |
| `INITN` pull-up | 4.7kΩ to VCCIO8 (3.3V) | `INITN` is open-drain per ECP5 spec, needs an external pull-up |
| Config flash `WP#`/`HOLD#` pull-ups | 10kΩ each to 3.3V | Per Point 10's own decision (`W25Q32JVSSIQ`, standard single-SPI mode, these pins unused and must be held inactive) |
| JTAG `TMS` pull-up | 4.7-10kΩ to 3.3V | Standard practice so an unconnected/high-impedance JTAG probe leaves TMS idle-high (TAP stays in Test-Logic-Reset) |
Not frozen (correctly left for PCB layout, per "only freeze what's
electrically required"): exact capacitor placement/count beyond the
one-per-pin-group guidance above, trace-length matching, ground-plane
stitching-via count.
### JTAG
| Property | Decision |
|---|---|
| Connector type | Simple unshrouded 2×3 (6-pin), 0.1" (2.54mm) pitch pin header — sufficient for a point-to-point bench connection; no vendor-specific shrouded-connector standard is mandated by Lattice for the ECP5 |
| Pinout | Pin1=3V3 (reference/probe-detect, not a supply to the probe), Pin2=TCK (real ball T5), Pin3=TMS (real ball U5), Pin4=TDI (real ball R5), Pin5=TDO (real ball V4), Pin6=GND |
| Required pull resistor | TMS: 4.7-10kΩ to 3.3V (see passives table above) |
| Required power/reference pin | 3.3V reference pin (Pin1) so a probe can detect target voltage; NOT used to power the board |
| `PROGRAMN`/config-related signals | Real balls W3 (PROGRAMN), V3 (INITN), Y3 (DONE), bank 8 — NOT part of the JTAG connector itself; these remain dedicated ECP5 configuration-control pins, routed separately per Point 14/15 of `PRE_PCB_VERIFICATION.md` |
| Programming/debug path | JTAG connects directly to the ECP5's own real TAP balls (R5/T5/U5/V4); no external JTAG buffer/level-shifter needed since the probe and the FPGA both operate at 3.3V |
**Complete programming/debug path verified**: JTAG header → real TAP
balls → ECP5 TAP controller → SRAM configuration (direct bitstream
download for bring-up/debug) or, separately, the `W25Q32JVSSIQ` config
flash for standalone boot (Point 10 of `PRE_PCB_VERIFICATION.md`) —
both paths coexist without conflict, as already confirmed in that
document's own JTAG-interaction analysis.
**RESULT: Power/JTAG/support components: CLOSED** (sufficient for
schematic capture; exact passive layout/placement remains, correctly,
a PCB-level task).
---
## FINAL 4-POINT STATUS
1. **SDRAM directed boundaries: PASS** (21/21, both 64MHz and 166MHz, zero bugs found)
2. **SPI maximum verified frequency: 12 MHz** (simulation-exact deterministic edge: 12.8MHz = 64MHz/5; one testbench-race bug found and fixed, NOT an RTL defect; board-level electrical limit remains OPEN, requires real hardware)
3. **16MHz oscillator: `ECS-3225MV-160-BN-TR` (ECS Inc.)** — FROZEN
4. **Power/JTAG/support components: CLOSED** (regulator MPNs, passive values, and JTAG connector/pinout frozen; exact PCB placement correctly deferred)
Remaining uncertainty, explicitly documented (not silently dropped):
oscillator order-suffix cross-check against the live ECS datasheet;
real FPGA dynamic current (still requires post-implementation data,
per `PRE_PCB_VERIFICATION.md` section 12); board-level SPI electrical
limit (requires real hardware bring-up); hold-timing tool limitation
(carried over from `PRE_PCB_VERIFICATION.md`, unaffected by this pass).
# PRE-PCB HARDWARE SPECIFICATION: FROZEN
Schematic and PCB layout remain the user's own implementation work.
This status means the four practical items requested are closed
sufficiently for schematic capture — it is NOT a claim of
"SILICON READY."
hardware/v2/nms/sim/tb_sdram_boundary.v
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`timescale 1ns/1ps
// ============================================================
// PRE-PCB CLOSURE, POINT 1 -- directed SDRAM boundary verification.
//
// tb_sdram_controller.v already covers randomized-address and
// pseudo-limit coverage (test I). This testbench is a SEPARATE,
// purpose-built regression targeting EXACT, individually-named
// addresses the randomized sweep does not specifically guarantee to
// hit: address 0/1, the last valid address and its predecessor, an
// explicit row-boundary crossing, explicit bank-boundary crossings
// (all 4 banks), the real V2 memory-map region boundaries
// (weights/activations/results), and every DQM byte-mask combination
// with an explicit read-after-write check. Real Alliance Memory
// AS4C4M16SA-6TIN geometry (confirmed against sdram_controller.v's
// own address decode): word address = {bank[1:0], row[11:0],
// col[7:0]}, 4 banks x 4096 rows x 256 cols x 16 bits = 4M words = 8MB.
//
// BURST_LEN=1 is used throughout (not the default 4) so every address
// in this test names an exact, single physical word -- burst-wrap
// semantics are already covered elsewhere (tb_sdram_controller.v's
// own BURST_LEN=4/8 sweep) and are orthogonal to this test's own
// purpose (address-decode correctness at exact boundaries).
// CLK_FREQ_MHZ=64 is the real board target (default parameter here),
// not one of the legacy 100/133/166MHz sweep points.
// ============================================================
module tb_sdram_boundary #(
parameter CLK_FREQ_MHZ = 64
);
localparam BURST_LEN = 1;
localparam ADDR_WIDTH = 22;
localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
reg clk = 0;
always #(CLK_PERIOD_NS/2.0) clk = ~clk;
reg rst;
reg req, wr;
reg [ADDR_WIDTH-1:0] addr;
reg [15:0] wdata;
reg [1:0] wmask;
wire [15:0] rdata;
wire ready, busy;
wire sdram_cke, sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n;
wire [1:0] sdram_ba;
wire [11:0] sdram_a;
wire [15:0] sdram_dq;
wire [1:0] sdram_dqm;
sdram_controller #(.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)) dut (
.clk(clk), .rst(rst),
.req(req), .wr(wr), .addr(addr), .wdata(wdata), .wmask(wmask), .rdata(rdata), .ready(ready), .busy(busy),
.sdram_cke(sdram_cke), .sdram_cs_n(sdram_cs_n), .sdram_ras_n(sdram_ras_n),
.sdram_cas_n(sdram_cas_n), .sdram_we_n(sdram_we_n),
.sdram_ba(sdram_ba), .sdram_a(sdram_a), .sdram_dq(sdram_dq), .sdram_dqm(sdram_dqm)
);
sdram_model #(.CLK_FREQ_MHZ(CLK_FREQ_MHZ)) mem (
.clk(clk), .cke(sdram_cke), .cs_n(sdram_cs_n), .ras_n(sdram_ras_n),
.cas_n(sdram_cas_n), .we_n(sdram_we_n), .ba(sdram_ba), .a(sdram_a),
.dq(sdram_dq), .dqm(sdram_dqm)
);
integer errors, tests;
task automatic write_word(input [ADDR_WIDTH-1:0] a, input [15:0] d, input [1:0] m);
begin
@(posedge clk);
while (busy) @(posedge clk);
req = 1'b1; wr = 1'b1; addr = a; wdata = d; wmask = m;
@(posedge clk);
req = 1'b0;
while (!ready) @(posedge clk);
end
endtask
task automatic read_word(input [ADDR_WIDTH-1:0] a, output [15:0] d);
begin
@(posedge clk);
while (busy) @(posedge clk);
req = 1'b1; wr = 1'b0; addr = a; wdata = 16'h0000; wmask = 2'b00;
@(posedge clk);
req = 1'b0;
while (!ready) @(posedge clk);
d = rdata;
end
endtask
reg [15:0] got;
task automatic check(input [ADDR_WIDTH-1:0] a, input [15:0] expected, input [255:0] label);
begin
read_word(a, got);
tests = tests + 1;
if (got !== expected) begin
$display("FAIL %0s addr=0x%06h (bank=%0d row=%0d col=%0d): expected=%h actual=%h",
label, a, a[21:20], a[19:8], a[7:0], expected, got);
errors = errors + 1;
end else begin
$display("PASS %0s addr=0x%06h (bank=%0d row=%0d col=%0d): data=%h",
label, a, a[21:20], a[19:8], a[7:0], got);
end
end
endtask
// address-derived pattern: distinct per address, used wherever the
// exact value doesn't matter beyond "must not alias with a
// neighbour" -- classic address-uniqueness memory-test idiom.
function [15:0] addr_pat(input [ADDR_WIDTH-1:0] a);
addr_pat = a[15:0] ^ 16'hC3A5;
endfunction
// ---- the real V2 memory map (BYTE addresses) converted to this
// controller's own WORD addresses (word = byte>>1) ----
localparam [ADDR_WIDTH-1:0] WEIGHTS_BASE_W = 22'h008000; // byte 0x010000
localparam [ADDR_WIDTH-1:0] ACT_BASE_W = 22'h100000; // byte 0x200000
localparam [ADDR_WIDTH-1:0] RESULTS_BASE_W = 22'h180000; // byte 0x300000
localparam [ADDR_WIDTH-1:0] WEIGHTS_LAST_W = ACT_BASE_W - 22'd1; // last word before activations
localparam [ADDR_WIDTH-1:0] ACT_LAST_W = RESULTS_BASE_W - 22'd1; // last word before results
// ---- the 17-address boundary/adjacency set. All written first
// (each a distinct addr_pat value), THEN all read back in a
// DIFFERENT (reversed) order -- if any write had corrupted a
// neighbouring/aliased address, the corresponding readback below
// would mismatch. This single set simultaneously proves address 0/
// 1/last/last-1, the explicit row crossing, all 3 inter-bank
// crossings, and all 3 real memory-map region boundaries cannot
// corrupt each other. ----
localparam N_ADDRS = 17;
reg [ADDR_WIDTH-1:0] a_set [0:N_ADDRS-1];
reg [255:0] a_label [0:N_ADDRS-1];
integer ai;
initial begin
a_set[0] = 22'h000000; a_label[0] = "addr-0";
a_set[1] = 22'h000001; a_label[1] = "addr-1";
a_set[2] = 22'h3FFFFF; a_label[2] = "addr-last";
a_set[3] = 22'h3FFFFE; a_label[3] = "addr-last-1";
a_set[4] = {2'd0, 12'd10, 8'd255}; a_label[4] = "row10-lastcol";
a_set[5] = {2'd0, 12'd11, 8'd0}; a_label[5] = "row11-firstcol";
a_set[6] = {2'd0, 12'd4095, 8'd255}; a_label[6] = "bank0-last";
a_set[7] = {2'd1, 12'd0, 8'd0}; a_label[7] = "bank1-first";
a_set[8] = {2'd1, 12'd4095, 8'd255}; a_label[8] = "bank1-last";
a_set[9] = {2'd2, 12'd0, 8'd0}; a_label[9] = "bank2-first";
a_set[10] = {2'd2, 12'd4095, 8'd255}; a_label[10] = "bank2-last";
a_set[11] = {2'd3, 12'd0, 8'd0}; a_label[11] = "bank3-first";
a_set[12] = WEIGHTS_BASE_W; a_label[12] = "weights-base";
a_set[13] = WEIGHTS_LAST_W; a_label[13] = "weights-last(pre-act)";
a_set[14] = ACT_BASE_W; a_label[14] = "activations-base";
a_set[15] = ACT_LAST_W; a_label[15] = "activations-last(pre-res)";
a_set[16] = RESULTS_BASE_W; a_label[16] = "results-base";
end
initial begin
errors = 0; tests = 0;
rst = 1; req = 0; wr = 0; addr = 0; wdata = 0; wmask = 0;
repeat(5) @(posedge clk);
rst = 0;
while (busy) @(posedge clk); // real power-up/init sequence
// ---- Address/row/bank/memory-map boundary set: write all,
// then read all back in reverse order ----
$display("--- boundary/adjacency set: writing %0d addresses ---", N_ADDRS);
for (ai = 0; ai < N_ADDRS; ai = ai + 1)
write_word(a_set[ai], addr_pat(a_set[ai]), 2'b00);
$display("--- boundary/adjacency set: reading back (reversed order) ---");
for (ai = N_ADDRS-1; ai >= 0; ai = ai - 1)
check(a_set[ai], addr_pat(a_set[ai]), a_label[ai]);
// ---- byte-mask combinations, explicit read-after-write,
// using the requested deterministic patterns (0x0000, 0xFFFF,
// 0xAAAA, 0x5555) ----
begin : mask_tests
localparam [ADDR_WIDTH-1:0] MADDR = 22'h001000;
// lower-byte-only write (wmask=2'b10: upper masked/
// retained, lower written)
write_word(MADDR, 16'hAAAA, 2'b00); // background: 0xAAAA
write_word(MADDR, 16'h1234, 2'b10); // write lower byte only (0x34)
check(MADDR, 16'hAA34, "mask-lower-only");
// upper-byte-only write (wmask=2'b01: lower masked/
// retained, upper written)
write_word(MADDR, 16'h5555, 2'b00); // background: 0x5555
write_word(MADDR, 16'h5678, 2'b01); // write upper byte only (0x56)
check(MADDR, 16'h5655, "mask-upper-only");
// both-bytes write (wmask=2'b00: no masking)
write_word(MADDR, 16'h0000, 2'b00); // background: 0x0000
write_word(MADDR, 16'hFFFF, 2'b00); // write both bytes
check(MADDR, 16'hFFFF, "mask-both-bytes");
// read-after-write with the remaining requested pattern
// (0x5555 alone, both bytes, at a different address) to
// exercise all four requested literal patterns at least
// once each in this test
write_word(MADDR + 22'd1, 16'h5555, 2'b00);
check(MADDR + 22'd1, 16'h5555, "pattern-5555-plain");
end
$display("=== %0d/%0d tests, %0d errors (tb_sdram_boundary, CLK_FREQ_MHZ=%0d) ===",
tests-errors, tests, errors, CLK_FREQ_MHZ);
if (errors == 0) $display("ALL TESTS PASSED (tb_sdram_boundary, CLK_FREQ_MHZ=%0d)", CLK_FREQ_MHZ);
$finish;
end
endmodule
hardware/v2/nms/sim/tb_spi_freq_sweep.v
+345
View File
@@ -0,0 +1,345 @@
`timescale 1ns/1ps
// ================================================================
// PRE-PCB CLOSURE, POINT 2 -- SPI operating-clock frequency sweep.
//
// tb_fpga_neural_v2_top_smoke.v only ever exercises the SPI bus at a
// single, fixed ~2MHz bit rate (500ns/bit: #200/#50/#50/#200). This
// testbench reuses the SAME real board-level top and the SAME job-
// registration protocol, but makes the SPI bit period a runtime
// parameter (SPI_FREQ_MHZ), so a genuine, reproducible frequency
// sweep can determine the highest rate the CDC synchronizer +
// protocol FSM in spi_host_bridge.v actually tolerates -- rather than
// assuming any particular number.
//
// Unlike tb_fpga_neural_v2_top_smoke.v (which parameterizes
// CLK_FREQ_MHZ=80 as a historical leftover), this testbench uses the
// real, frozen CLK_FREQ_MHZ=64 default AND drives osc_clk itself at
// 64MHz -- under the `SIM behavioral PLL bypass (ecp5_pll_sys_clk.v:
// `clk_sys = clk_16mhz` directly, since no open EHXPLLL model exists),
// this makes clk_sys run at the REAL board's actual 64MHz system-
// clock rate, which is the frequency that actually determines the
// synchronizer's real margin against a given SPI rate.
//
// Coverage per swept frequency (matching the mandate's own explicit
// list): job registration (register access), a job run alone, two
// jobs back-to-back (minimal CS gap), two jobs with a realistic gap,
// a raw WRITE_MEM/READ_MEM round trip over SPI (memory read/write +
// result readback via the ACTUAL SPI response path, not just the
// backdoor SDRAM peek), and repeated transactions.
// ================================================================
`define SIM
module tb_spi_freq_sweep #(
parameter real SPI_FREQ_MHZ = 2.0
);
localparam ADDR_WIDTH = 23;
localparam N_SLOTS = 2;
localparam N_NODES = 16;
localparam MAX_DEPS = 4;
// real board system clock: 64MHz, driven directly as osc_clk under
// the `SIM bypass (clk_sys = osc_clk, see ecp5_pll_sys_clk.v)
reg osc_clk = 0;
always #7.8125 osc_clk = ~osc_clk; // 64MHz
reg ext_rst_n = 0;
reg spi_sclk = 0, spi_mosi = 0, spi_cs_n = 1;
wire spi_miso;
wire sdram_cke, sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n;
wire [1:0] sdram_ba;
wire [11:0] sdram_a;
wire [15:0] sdram_dq;
wire [1:0] sdram_dqm;
wire pll_locked;
fpga_neural_v2_top #(
.ADDR_WIDTH(ADDR_WIDTH), .N_SLOTS(N_SLOTS), .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS),
.CLK_FREQ_MHZ(64)
) dut (
.osc_clk(osc_clk), .ext_rst_n(ext_rst_n),
.spi_sclk(spi_sclk), .spi_mosi(spi_mosi), .spi_miso(spi_miso), .spi_cs_n(spi_cs_n),
.sdram_cke(sdram_cke), .sdram_cs_n(sdram_cs_n), .sdram_ras_n(sdram_ras_n),
.sdram_cas_n(sdram_cas_n), .sdram_we_n(sdram_we_n),
.sdram_ba(sdram_ba), .sdram_a(sdram_a), .sdram_dq(sdram_dq), .sdram_dqm(sdram_dqm),
.pll_locked(pll_locked)
);
sdram_model #(.CLK_FREQ_MHZ(64)) u_sdram (
.clk(dut.clk_sys), .cke(sdram_cke), .cs_n(sdram_cs_n), .ras_n(sdram_ras_n),
.cas_n(sdram_cas_n), .we_n(sdram_we_n), .ba(sdram_ba), .a(sdram_a),
.dq(sdram_dq), .dqm(sdram_dqm)
);
function automatic signed [7:0] relu_sat(input signed [31:0] acc);
begin
if (acc < 0) relu_sat = 8'sd0;
else if (acc > 127) relu_sat = 8'sd127;
else relu_sat = acc[7:0];
end
endfunction
task poke_byte(input [ADDR_WIDTH-1:0] byte_addr, input signed [7:0] val);
reg [21:0] word_addr;
begin
word_addr = byte_addr[ADDR_WIDTH-1:1];
if (byte_addr[0] == 1'b0) u_sdram.mem[word_addr][7:0] = val;
else u_sdram.mem[word_addr][15:8] = val;
end
endtask
function automatic signed [7:0] peek_byte(input [ADDR_WIDTH-1:0] byte_addr);
reg [21:0] word_addr;
begin
word_addr = byte_addr[ADDR_WIDTH-1:1];
peek_byte = (byte_addr[0] == 1'b0) ? u_sdram.mem[word_addr][7:0] : u_sdram.mem[word_addr][15:8];
end
endfunction
// ---- runtime-configurable SPI bit timing (mode 0, MSB-first),
// proportioned the same 40/10/10/40 split as the existing fixed-
// rate testbenches' own 200/50/50/200ns convention, scaled to
// whatever bit period SPI_FREQ_MHZ implies ----
real BIT_NS, T_SETUP, T_SAMPLE, T_HOLD;
initial begin
BIT_NS = 1000.0 / SPI_FREQ_MHZ;
T_SETUP = 0.4 * BIT_NS;
T_SAMPLE = 0.1 * BIT_NS;
T_HOLD = 0.1 * BIT_NS;
end
task spi_byte(input [7:0] tx, output [7:0] rx);
integer i;
begin
rx = 8'h00;
for (i = 7; i >= 0; i = i - 1) begin
spi_mosi = tx[i];
#(T_SETUP); spi_sclk = 1; #(T_SAMPLE); rx = {rx[6:0], spi_miso}; #(T_HOLD); spi_sclk = 0; #(T_SETUP);
end
end
endtask
task write_job(input [3:0] node_id, input [2:0] required, input [15:0] producer_ids,
input [22:0] x_base, input [22:0] w_base, input [15:0] n_tiles,
input [22:0] result_addr);
reg [7:0] rxb;
begin
spi_cs_n = 0; #(T_SETUP);
spi_byte(8'h10, rxb);
spi_byte({4'b0, node_id}, rxb);
spi_byte({5'b0, required}, rxb);
spi_byte(producer_ids[15:8], rxb);
spi_byte(producer_ids[7:0], rxb);
spi_byte({1'b0, x_base[22:16]}, rxb);
spi_byte(x_base[15:8], rxb);
spi_byte(x_base[7:0], rxb);
spi_byte({1'b0, w_base[22:16]}, rxb);
spi_byte(w_base[15:8], rxb);
spi_byte(w_base[7:0], rxb);
spi_byte(n_tiles[15:8], rxb);
spi_byte(n_tiles[7:0], rxb);
spi_byte({1'b0, result_addr[22:16]}, rxb);
spi_byte(result_addr[15:8], rxb);
spi_byte(result_addr[7:0], rxb);
// hold CS through the reg_valid/reg_ready handshake -- a
// fixed real-time wait, independent of SPI bit rate (the
// backend handshake runs on clk_sys, not on SCLK)
#2000;
spi_cs_n = 1; #(T_SETUP);
end
endtask
// ---- raw WRITE_MEM / READ_MEM (opcodes 0x01/0x02), single word,
// exercising the ACTUAL SPI response path (not the backdoor SDRAM
// peek), directly testing "memory read/write over SPI" and
// "result readback" at the swept frequency ----
// ST_MEM_ROUT=4'd8, ST_IGNORE=4'd9 (spi_host_bridge.v's own FSM
// localparams) -- polled directly rather than guessing a fixed
// real-time margin, since the real host-arb/SDRAM-controller
// backend latency (unlike the isolated tb_spi_host_bridge.v unit
// test's own directly-driven mem_rdata/mem_ready mock) genuinely
// varies cycle to cycle (e.g. a periodic AUTO REFRESH landing
// during the request). A fixed real-time wait here previously
// produced one real, reproducible failure (mem-word-1 at
// SPI_FREQ_MHZ=2.0: the response's MSB sampled 0 instead of 1)
// when the backend legitimately took longer than the guessed
// margin -- traced to this testbench's own race, NOT a
// spi_host_bridge.v defect (tb_spi_host_bridge.v's own isolated
// regression already proves the FIRST READ_MEM after reset
// delivers all 16 bits correctly when its own mock backend
// responds within ITS OWN test's assumed timing).
task spi_write_mem_word(input [22:0] word_addr, input [15:0] data);
reg [7:0] rxb;
begin
spi_cs_n = 0; #(T_SETUP);
spi_byte(8'h01, rxb);
spi_byte({1'b0, word_addr[22:16]}, rxb);
spi_byte(word_addr[15:8], rxb);
spi_byte(word_addr[7:0], rxb);
spi_byte(16'd1 >> 8, rxb);
spi_byte(16'd1 & 8'hFF, rxb);
spi_byte(data[15:8], rxb);
spi_byte(data[7:0], rxb);
while (dut.u_spi_bridge.state != 4'd9) @(posedge dut.clk_sys); // ST_IGNORE: mem_req/mem_ready handshake done
spi_cs_n = 1; #(T_SETUP);
end
endtask
task spi_read_mem_word(input [22:0] word_addr, output [15:0] data);
reg [7:0] rxb_hi, rxb_lo;
begin
spi_cs_n = 0; #(T_SETUP);
spi_byte(8'h02, rxb_hi);
spi_byte({1'b0, word_addr[22:16]}, rxb_hi);
spi_byte(word_addr[15:8], rxb_hi);
spi_byte(word_addr[7:0], rxb_hi);
spi_byte(16'd1 >> 8, rxb_hi);
spi_byte(16'd1 & 8'hFF, rxb_hi);
while (dut.u_spi_bridge.state != 4'd8) @(posedge dut.clk_sys); // ST_MEM_ROUT: cur_word latched, response bytes ready
spi_byte(8'h00, rxb_hi); // clock out response byte 0 (MSB)
spi_byte(8'h00, rxb_lo); // clock out response byte 1 (LSB)
data = {rxb_hi, rxb_lo};
spi_cs_n = 1; #(T_SETUP);
end
endtask
integer errors, tests;
integer node_ctr;
task check_neuron(input [22:0] x_base, input [22:0] w_base, input [22:0] res_addr,
input [255:0] label);
integer k;
reg signed [31:0] acc;
reg signed [7:0] golden, real_y;
begin
acc = 0;
for (k = 0; k < 8; k = k + 1)
acc = acc + peek_byte(x_base + k) * peek_byte(w_base + k);
golden = relu_sat(acc);
real_y = peek_byte(res_addr);
tests = tests + 1;
if (real_y !== golden) begin
errors = errors + 1;
$display("FAIL %0s: real=%0d golden=%0d", label, real_y, golden);
end else begin
$display("PASS %0s: real=%0d golden=%0d", label, real_y, golden);
end
end
endtask
task run_pair(input [22:0] region, input integer gap_ns, input [255:0] label);
reg [22:0] x_base, w0, w1, res0, res1;
integer k, n;
begin
x_base = region;
w0 = region + 23'h100;
w1 = region + 23'h110;
res0 = region + 23'h200;
res1 = region + 23'h201;
for (k = 0; k < 8; k = k + 1) poke_byte(x_base + k, k[7:0] + 1);
for (n = 0; n < 2; n = n + 1)
for (k = 0; k < 8; k = k + 1)
poke_byte((n == 0 ? w0 : w1) + k, ((n + k) % 4) + 1);
poke_byte(res0, 8'sd0);
poke_byte(res1, 8'sd0);
write_job(node_ctr[3:0], 3'd0, 16'h0000, x_base, w0, 16'd1, res0);
node_ctr = node_ctr + 1;
if (gap_ns > 0) #gap_ns;
write_job(node_ctr[3:0], 3'd0, 16'h0000, x_base, w1, 16'd1, res1);
node_ctr = node_ctr + 1;
repeat (3000) @(posedge dut.clk_sys);
check_neuron(x_base, w0, res0, {label, "-A"});
check_neuron(x_base, w1, res1, {label, "-B"});
end
endtask
task run_single(input [22:0] region, input [255:0] label);
reg [22:0] x_base, w0, res0;
integer k;
begin
x_base = region;
w0 = region + 23'h100;
res0 = region + 23'h200;
for (k = 0; k < 8; k = k + 1) poke_byte(x_base + k, k[7:0] + 3);
for (k = 0; k < 8; k = k + 1) poke_byte(w0 + k, ((k) % 3) + 1);
poke_byte(res0, 8'sd0);
write_job(node_ctr[3:0], 3'd0, 16'h0000, x_base, w0, 16'd1, res0);
node_ctr = node_ctr + 1;
repeat (3000) @(posedge dut.clk_sys);
check_neuron(x_base, w0, res0, label);
end
endtask
task check_mem_word(input [22:0] word_addr, input [15:0] wr_pattern, input [255:0] label);
reg [15:0] rd_pattern;
begin
spi_write_mem_word(word_addr, wr_pattern);
spi_read_mem_word(word_addr, rd_pattern);
tests = tests + 1;
if (rd_pattern !== wr_pattern) begin
errors = errors + 1;
$display("FAIL %0s: wrote=%h read-back=%h", label, wr_pattern, rd_pattern);
end else begin
$display("PASS %0s: wrote=%h read-back=%h (real SPI response path)", label, wr_pattern, rd_pattern);
end
end
endtask
// watchdog: if the CDC/protocol FSM genuinely locks up at a given
// SPI rate (rather than merely corrupting a data bit), a blind
// `while (state != X) @(posedge clk)` poll would hang the
// simulation forever. Report a clean, explicit HANG verdict
// instead of an infinite loop.
initial begin
#2_000_000; // 2ms real time -- generous, real tests finish in <50us
$display("*** WATCHDOG TIMEOUT at SPI_FREQ_MHZ=%0.3f -- protocol FSM HUNG (not merely a data error) ***", SPI_FREQ_MHZ);
$finish;
end
initial begin
errors = 0; tests = 0; node_ctr = 0;
ext_rst_n = 0;
repeat (20) @(posedge osc_clk);
ext_rst_n = 1;
repeat (10) @(posedge osc_clk);
wait (dut.u_sdram_backend.u_sdram_ctrl.state == dut.u_sdram_backend.u_sdram_ctrl.S_IDLE);
@(posedge dut.clk_sys);
$display("--- SPI_FREQ_MHZ=%0.3f (bit period=%0.2fns) ---", SPI_FREQ_MHZ, BIT_NS);
// register access / neural job submission, single job
run_single(23'h001000, "single-neuron0");
// two jobs back-to-back (minimal CS gap) -- register access stress
run_pair(23'h004000, 0, "back-to-back");
// two jobs, realistic gap
run_pair(23'h007000, 20000, "realistic-gap");
// raw memory write/read over the real SPI response path
check_mem_word(23'h00A000, 16'hA55A, "mem-word-1");
check_mem_word(23'h00A001, 16'h1234, "mem-word-2");
// repeated transactions (stress the framing/CDC over many
// back-to-back opcodes, not just one pair)
run_single(23'h00D000, "repeat-1");
run_single(23'h00E000, "repeat-2");
run_single(23'h00F000, "repeat-3");
$display("=== SPI_FREQ_MHZ=%0.3f: %0d/%0d PASS ===", SPI_FREQ_MHZ, tests-errors, tests);
if (errors != 0) $display("*** %0d FAILURES at SPI_FREQ_MHZ=%0.3f ***", errors, SPI_FREQ_MHZ);
$finish;
end
endmodule