micheleandClaude Sonnet 5
c4763aab10
PRE-PCB CLOSURE Point 1: adds tb_sdram_boundary.v, a directed (not randomized) regression covering address 0/1/last/last-1, an explicit row-boundary crossing, all 3 inter-bank boundary crossings, the real V2 memory-map region boundaries (weights/activations/results), and every DQM byte-mask combination with explicit read-after-write. 21/21 PASS at both 64MHz and 166MHz, zero bugs found. PRE-PCB CLOSURE Point 2: adds tb_spi_freq_sweep.v, a reproducible SPI bit-rate sweep against the real fpga_neural_v2_top (osc_clk driven at the real 64MHz clk_sys rate via the SIM PLL bypass). Found and fixed a race in the new test harness itself (a fixed-time wait before reading a WRITE_MEM/READ_MEM response, too short whenever a periodic AUTO REFRESH delayed the backend) -- not a spi_host_bridge.v defect, confirmed against tb_spi_host_bridge.v's own isolated regression. Determined the real, deterministic CDC margin: the synchronizer requires >=5 system-clock cycles per SPI bit (exactly 64MHz/5 = 12.8MHz); recommends SPI_MAX_VERIFIED=12MHz with real margin below that hard edge. Full writeup: hardware/v2/docs/PRE_PCB_CLOSURE_4POINT.md. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
346 lines
14 KiB
Verilog
346 lines
14 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// PRE-PCB CLOSURE, POINT 2 -- SPI operating-clock frequency sweep.
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//
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// tb_fpga_neural_v2_top_smoke.v only ever exercises the SPI bus at a
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// single, fixed ~2MHz bit rate (500ns/bit: #200/#50/#50/#200). This
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// testbench reuses the SAME real board-level top and the SAME job-
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// registration protocol, but makes the SPI bit period a runtime
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// parameter (SPI_FREQ_MHZ), so a genuine, reproducible frequency
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// sweep can determine the highest rate the CDC synchronizer +
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// protocol FSM in spi_host_bridge.v actually tolerates -- rather than
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// assuming any particular number.
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//
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// Unlike tb_fpga_neural_v2_top_smoke.v (which parameterizes
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// CLK_FREQ_MHZ=80 as a historical leftover), this testbench uses the
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// real, frozen CLK_FREQ_MHZ=64 default AND drives osc_clk itself at
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// 64MHz -- under the `SIM behavioral PLL bypass (ecp5_pll_sys_clk.v:
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// `clk_sys = clk_16mhz` directly, since no open EHXPLLL model exists),
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// this makes clk_sys run at the REAL board's actual 64MHz system-
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// clock rate, which is the frequency that actually determines the
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// synchronizer's real margin against a given SPI rate.
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//
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// Coverage per swept frequency (matching the mandate's own explicit
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// list): job registration (register access), a job run alone, two
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// jobs back-to-back (minimal CS gap), two jobs with a realistic gap,
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// a raw WRITE_MEM/READ_MEM round trip over SPI (memory read/write +
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// result readback via the ACTUAL SPI response path, not just the
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// backdoor SDRAM peek), and repeated transactions.
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// ================================================================
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`define SIM
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module tb_spi_freq_sweep #(
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parameter real SPI_FREQ_MHZ = 2.0
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);
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localparam ADDR_WIDTH = 23;
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localparam N_SLOTS = 2;
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localparam N_NODES = 16;
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localparam MAX_DEPS = 4;
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// real board system clock: 64MHz, driven directly as osc_clk under
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// the `SIM bypass (clk_sys = osc_clk, see ecp5_pll_sys_clk.v)
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reg osc_clk = 0;
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always #7.8125 osc_clk = ~osc_clk; // 64MHz
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reg ext_rst_n = 0;
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reg spi_sclk = 0, spi_mosi = 0, spi_cs_n = 1;
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wire spi_miso;
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wire sdram_cke, sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n;
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wire [1:0] sdram_ba;
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wire [11:0] sdram_a;
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wire [15:0] sdram_dq;
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wire [1:0] sdram_dqm;
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wire pll_locked;
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fpga_neural_v2_top #(
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.ADDR_WIDTH(ADDR_WIDTH), .N_SLOTS(N_SLOTS), .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS),
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.CLK_FREQ_MHZ(64)
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) dut (
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.osc_clk(osc_clk), .ext_rst_n(ext_rst_n),
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.spi_sclk(spi_sclk), .spi_mosi(spi_mosi), .spi_miso(spi_miso), .spi_cs_n(spi_cs_n),
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.sdram_cke(sdram_cke), .sdram_cs_n(sdram_cs_n), .sdram_ras_n(sdram_ras_n),
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.sdram_cas_n(sdram_cas_n), .sdram_we_n(sdram_we_n),
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.sdram_ba(sdram_ba), .sdram_a(sdram_a), .sdram_dq(sdram_dq), .sdram_dqm(sdram_dqm),
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.pll_locked(pll_locked)
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);
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sdram_model #(.CLK_FREQ_MHZ(64)) u_sdram (
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.clk(dut.clk_sys), .cke(sdram_cke), .cs_n(sdram_cs_n), .ras_n(sdram_ras_n),
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.cas_n(sdram_cas_n), .we_n(sdram_we_n), .ba(sdram_ba), .a(sdram_a),
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.dq(sdram_dq), .dqm(sdram_dqm)
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);
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function automatic signed [7:0] relu_sat(input signed [31:0] acc);
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begin
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if (acc < 0) relu_sat = 8'sd0;
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else if (acc > 127) relu_sat = 8'sd127;
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else relu_sat = acc[7:0];
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end
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endfunction
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task poke_byte(input [ADDR_WIDTH-1:0] byte_addr, input signed [7:0] val);
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reg [21:0] word_addr;
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begin
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word_addr = byte_addr[ADDR_WIDTH-1:1];
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if (byte_addr[0] == 1'b0) u_sdram.mem[word_addr][7:0] = val;
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else u_sdram.mem[word_addr][15:8] = val;
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end
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endtask
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function automatic signed [7:0] peek_byte(input [ADDR_WIDTH-1:0] byte_addr);
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reg [21:0] word_addr;
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begin
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word_addr = byte_addr[ADDR_WIDTH-1:1];
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peek_byte = (byte_addr[0] == 1'b0) ? u_sdram.mem[word_addr][7:0] : u_sdram.mem[word_addr][15:8];
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end
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endfunction
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// ---- runtime-configurable SPI bit timing (mode 0, MSB-first),
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// proportioned the same 40/10/10/40 split as the existing fixed-
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// rate testbenches' own 200/50/50/200ns convention, scaled to
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// whatever bit period SPI_FREQ_MHZ implies ----
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real BIT_NS, T_SETUP, T_SAMPLE, T_HOLD;
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initial begin
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BIT_NS = 1000.0 / SPI_FREQ_MHZ;
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T_SETUP = 0.4 * BIT_NS;
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T_SAMPLE = 0.1 * BIT_NS;
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T_HOLD = 0.1 * BIT_NS;
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end
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task spi_byte(input [7:0] tx, output [7:0] rx);
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integer i;
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begin
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rx = 8'h00;
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for (i = 7; i >= 0; i = i - 1) begin
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spi_mosi = tx[i];
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#(T_SETUP); spi_sclk = 1; #(T_SAMPLE); rx = {rx[6:0], spi_miso}; #(T_HOLD); spi_sclk = 0; #(T_SETUP);
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end
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end
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endtask
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task write_job(input [3:0] node_id, input [2:0] required, input [15:0] producer_ids,
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input [22:0] x_base, input [22:0] w_base, input [15:0] n_tiles,
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input [22:0] result_addr);
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reg [7:0] rxb;
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begin
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spi_cs_n = 0; #(T_SETUP);
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spi_byte(8'h10, rxb);
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spi_byte({4'b0, node_id}, rxb);
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spi_byte({5'b0, required}, rxb);
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spi_byte(producer_ids[15:8], rxb);
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spi_byte(producer_ids[7:0], rxb);
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spi_byte({1'b0, x_base[22:16]}, rxb);
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spi_byte(x_base[15:8], rxb);
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spi_byte(x_base[7:0], rxb);
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spi_byte({1'b0, w_base[22:16]}, rxb);
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spi_byte(w_base[15:8], rxb);
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spi_byte(w_base[7:0], rxb);
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spi_byte(n_tiles[15:8], rxb);
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spi_byte(n_tiles[7:0], rxb);
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spi_byte({1'b0, result_addr[22:16]}, rxb);
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spi_byte(result_addr[15:8], rxb);
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spi_byte(result_addr[7:0], rxb);
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// hold CS through the reg_valid/reg_ready handshake -- a
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// fixed real-time wait, independent of SPI bit rate (the
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// backend handshake runs on clk_sys, not on SCLK)
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#2000;
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spi_cs_n = 1; #(T_SETUP);
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end
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endtask
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// ---- raw WRITE_MEM / READ_MEM (opcodes 0x01/0x02), single word,
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// exercising the ACTUAL SPI response path (not the backdoor SDRAM
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// peek), directly testing "memory read/write over SPI" and
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// "result readback" at the swept frequency ----
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// ST_MEM_ROUT=4'd8, ST_IGNORE=4'd9 (spi_host_bridge.v's own FSM
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// localparams) -- polled directly rather than guessing a fixed
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// real-time margin, since the real host-arb/SDRAM-controller
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// backend latency (unlike the isolated tb_spi_host_bridge.v unit
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// test's own directly-driven mem_rdata/mem_ready mock) genuinely
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// varies cycle to cycle (e.g. a periodic AUTO REFRESH landing
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// during the request). A fixed real-time wait here previously
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// produced one real, reproducible failure (mem-word-1 at
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// SPI_FREQ_MHZ=2.0: the response's MSB sampled 0 instead of 1)
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// when the backend legitimately took longer than the guessed
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// margin -- traced to this testbench's own race, NOT a
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// spi_host_bridge.v defect (tb_spi_host_bridge.v's own isolated
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// regression already proves the FIRST READ_MEM after reset
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// delivers all 16 bits correctly when its own mock backend
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// responds within ITS OWN test's assumed timing).
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task spi_write_mem_word(input [22:0] word_addr, input [15:0] data);
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reg [7:0] rxb;
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begin
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spi_cs_n = 0; #(T_SETUP);
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spi_byte(8'h01, rxb);
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spi_byte({1'b0, word_addr[22:16]}, rxb);
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spi_byte(word_addr[15:8], rxb);
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spi_byte(word_addr[7:0], rxb);
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spi_byte(16'd1 >> 8, rxb);
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spi_byte(16'd1 & 8'hFF, rxb);
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spi_byte(data[15:8], rxb);
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spi_byte(data[7:0], rxb);
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while (dut.u_spi_bridge.state != 4'd9) @(posedge dut.clk_sys); // ST_IGNORE: mem_req/mem_ready handshake done
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spi_cs_n = 1; #(T_SETUP);
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end
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endtask
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task spi_read_mem_word(input [22:0] word_addr, output [15:0] data);
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reg [7:0] rxb_hi, rxb_lo;
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begin
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spi_cs_n = 0; #(T_SETUP);
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spi_byte(8'h02, rxb_hi);
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spi_byte({1'b0, word_addr[22:16]}, rxb_hi);
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spi_byte(word_addr[15:8], rxb_hi);
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spi_byte(word_addr[7:0], rxb_hi);
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spi_byte(16'd1 >> 8, rxb_hi);
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spi_byte(16'd1 & 8'hFF, rxb_hi);
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while (dut.u_spi_bridge.state != 4'd8) @(posedge dut.clk_sys); // ST_MEM_ROUT: cur_word latched, response bytes ready
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spi_byte(8'h00, rxb_hi); // clock out response byte 0 (MSB)
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spi_byte(8'h00, rxb_lo); // clock out response byte 1 (LSB)
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data = {rxb_hi, rxb_lo};
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spi_cs_n = 1; #(T_SETUP);
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end
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endtask
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integer errors, tests;
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integer node_ctr;
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task check_neuron(input [22:0] x_base, input [22:0] w_base, input [22:0] res_addr,
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input [255:0] label);
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integer k;
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reg signed [31:0] acc;
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reg signed [7:0] golden, real_y;
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begin
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acc = 0;
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for (k = 0; k < 8; k = k + 1)
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acc = acc + peek_byte(x_base + k) * peek_byte(w_base + k);
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golden = relu_sat(acc);
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real_y = peek_byte(res_addr);
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tests = tests + 1;
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if (real_y !== golden) begin
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errors = errors + 1;
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$display("FAIL %0s: real=%0d golden=%0d", label, real_y, golden);
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end else begin
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$display("PASS %0s: real=%0d golden=%0d", label, real_y, golden);
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end
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end
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endtask
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task run_pair(input [22:0] region, input integer gap_ns, input [255:0] label);
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reg [22:0] x_base, w0, w1, res0, res1;
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integer k, n;
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begin
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x_base = region;
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w0 = region + 23'h100;
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w1 = region + 23'h110;
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res0 = region + 23'h200;
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res1 = region + 23'h201;
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for (k = 0; k < 8; k = k + 1) poke_byte(x_base + k, k[7:0] + 1);
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for (n = 0; n < 2; n = n + 1)
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for (k = 0; k < 8; k = k + 1)
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poke_byte((n == 0 ? w0 : w1) + k, ((n + k) % 4) + 1);
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poke_byte(res0, 8'sd0);
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poke_byte(res1, 8'sd0);
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write_job(node_ctr[3:0], 3'd0, 16'h0000, x_base, w0, 16'd1, res0);
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node_ctr = node_ctr + 1;
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if (gap_ns > 0) #gap_ns;
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write_job(node_ctr[3:0], 3'd0, 16'h0000, x_base, w1, 16'd1, res1);
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node_ctr = node_ctr + 1;
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repeat (3000) @(posedge dut.clk_sys);
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check_neuron(x_base, w0, res0, {label, "-A"});
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check_neuron(x_base, w1, res1, {label, "-B"});
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end
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endtask
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task run_single(input [22:0] region, input [255:0] label);
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reg [22:0] x_base, w0, res0;
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integer k;
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begin
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x_base = region;
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w0 = region + 23'h100;
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res0 = region + 23'h200;
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for (k = 0; k < 8; k = k + 1) poke_byte(x_base + k, k[7:0] + 3);
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for (k = 0; k < 8; k = k + 1) poke_byte(w0 + k, ((k) % 3) + 1);
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poke_byte(res0, 8'sd0);
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write_job(node_ctr[3:0], 3'd0, 16'h0000, x_base, w0, 16'd1, res0);
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node_ctr = node_ctr + 1;
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repeat (3000) @(posedge dut.clk_sys);
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check_neuron(x_base, w0, res0, label);
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end
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endtask
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task check_mem_word(input [22:0] word_addr, input [15:0] wr_pattern, input [255:0] label);
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reg [15:0] rd_pattern;
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begin
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spi_write_mem_word(word_addr, wr_pattern);
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spi_read_mem_word(word_addr, rd_pattern);
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tests = tests + 1;
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if (rd_pattern !== wr_pattern) begin
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errors = errors + 1;
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$display("FAIL %0s: wrote=%h read-back=%h", label, wr_pattern, rd_pattern);
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end else begin
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$display("PASS %0s: wrote=%h read-back=%h (real SPI response path)", label, wr_pattern, rd_pattern);
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end
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end
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endtask
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// watchdog: if the CDC/protocol FSM genuinely locks up at a given
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// SPI rate (rather than merely corrupting a data bit), a blind
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// `while (state != X) @(posedge clk)` poll would hang the
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// simulation forever. Report a clean, explicit HANG verdict
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// instead of an infinite loop.
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initial begin
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#2_000_000; // 2ms real time -- generous, real tests finish in <50us
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$display("*** WATCHDOG TIMEOUT at SPI_FREQ_MHZ=%0.3f -- protocol FSM HUNG (not merely a data error) ***", SPI_FREQ_MHZ);
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$finish;
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end
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initial begin
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errors = 0; tests = 0; node_ctr = 0;
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ext_rst_n = 0;
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repeat (20) @(posedge osc_clk);
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ext_rst_n = 1;
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repeat (10) @(posedge osc_clk);
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wait (dut.u_sdram_backend.u_sdram_ctrl.state == dut.u_sdram_backend.u_sdram_ctrl.S_IDLE);
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@(posedge dut.clk_sys);
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$display("--- SPI_FREQ_MHZ=%0.3f (bit period=%0.2fns) ---", SPI_FREQ_MHZ, BIT_NS);
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// register access / neural job submission, single job
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run_single(23'h001000, "single-neuron0");
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// two jobs back-to-back (minimal CS gap) -- register access stress
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run_pair(23'h004000, 0, "back-to-back");
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// two jobs, realistic gap
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run_pair(23'h007000, 20000, "realistic-gap");
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// raw memory write/read over the real SPI response path
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check_mem_word(23'h00A000, 16'hA55A, "mem-word-1");
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check_mem_word(23'h00A001, 16'h1234, "mem-word-2");
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// repeated transactions (stress the framing/CDC over many
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// back-to-back opcodes, not just one pair)
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run_single(23'h00D000, "repeat-1");
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run_single(23'h00E000, "repeat-2");
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run_single(23'h00F000, "repeat-3");
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$display("=== SPI_FREQ_MHZ=%0.3f: %0d/%0d PASS ===", SPI_FREQ_MHZ, tests-errors, tests);
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if (errors != 0) $display("*** %0d FAILURES at SPI_FREQ_MHZ=%0.3f ***", errors, SPI_FREQ_MHZ);
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$finish;
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end
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endmodule
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