fix: add missing sdram_clk output port -- real chip never had a clock pin

Found while helping verify the user's own schematic: clk_sys (the PLL-
generated 64MHz system clock) was purely internal to
fpga_neural_v2_top.v -- never reached a physical output pin. The real
external SDRAM chip cannot function without its own CLK input driven
from the board; this was missing from every prior P&R run this
session, none of which ever routed a real clock to the SDRAM interface.

Added `sdram_clk` output port (driven directly by clk_sys), assigned
to J4 (bank 6, GR_PCLK6_0 -- a real clock-capable ball, confirmed free
via Trellis iodb.json). Verified via real synthesis (0 errors) and
nextpnr-ecp5 place&route: the pad-forwarded clock merges with the
existing internal clock net (as expected, both are the same clk_sys
signal), achieving 66.61 MHz post-route -- PASS at the 64 MHz target
(the pre-route estimate of 49.73 MHz was a placement-only pessimistic
number, superseded by the real post-route result). Smoke test
re-verified (tb_fpga_neural_v2_top_smoke.v, 11/11 PASS).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/nms/rtl/fpga_neural_v2_top.v

@@ -56,6 +56,12 @@ module fpga_neural_v2_top #(
     input  wire spi_cs_n,
 
     // ---- single physical SDRAM (weights + activations + results) ----
+    // sdram_clk: the real SDRAM chip's own CLK pin -- an external
+    // chip, it needs this driven from a real output ball, NOT just
+    // internal routing. Found missing entirely during this session's
+    // schematic review (clk_sys was purely internal, never reached a
+    // pad) -- added here, real free clock-capable ball (bank 6).
+    output wire        sdram_clk,
     output wire        sdram_cke,
     output wire        sdram_cs_n,
     output wire        sdram_ras_n,
@@ -82,6 +88,8 @@ module fpga_neural_v2_top #(
         .clk_16mhz(osc_clk), .clk_sys(clk_sys), .locked(pll_locked)
     );
 
+    assign sdram_clk = clk_sys;
+
     wire clk = clk_sys;
     wire rst;
     reset_sync u_reset_sync (