From b4f33388a9edd099363cf66589023474dc50400e Mon Sep 17 00:00:00 2001 From: Michele Bigi Date: Mon, 7 Sep 2026 17:55:23 +0200 Subject: [PATCH] fix: add missing sdram_clk output port -- real chip never had a clock pin Found while helping verify the user's own schematic: clk_sys (the PLL- generated 64MHz system clock) was purely internal to fpga_neural_v2_top.v -- never reached a physical output pin. The real external SDRAM chip cannot function without its own CLK input driven from the board; this was missing from every prior P&R run this session, none of which ever routed a real clock to the SDRAM interface. Added `sdram_clk` output port (driven directly by clk_sys), assigned to J4 (bank 6, GR_PCLK6_0 -- a real clock-capable ball, confirmed free via Trellis iodb.json). Verified via real synthesis (0 errors) and nextpnr-ecp5 place&route: the pad-forwarded clock merges with the existing internal clock net (as expected, both are the same clk_sys signal), achieving 66.61 MHz post-route -- PASS at the 64 MHz target (the pre-route estimate of 49.73 MHz was a placement-only pessimistic number, superseded by the real post-route result). Smoke test re-verified (tb_fpga_neural_v2_top_smoke.v, 11/11 PASS). Co-Authored-By: Claude Sonnet 5 Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v --- hardware/v2/constraints/v2_board_top.lpf | 3 +++ hardware/v2/nms/rtl/fpga_neural_v2_top.v | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/hardware/v2/constraints/v2_board_top.lpf b/hardware/v2/constraints/v2_board_top.lpf index 216c330..f3233d9 100644 --- a/hardware/v2/constraints/v2_board_top.lpf +++ b/hardware/v2/constraints/v2_board_top.lpf @@ -49,6 +49,9 @@ LOCATE COMP "pll_locked" SITE "L1"; IOBUF PORT "pll_locked" IO_TYPE=LVCMOS33; // ---- SDRAM interface (37 signals), unchanged from v2_unified.lpf, // real balls, banks 6/7 ---- +// sdram_clk: real clock-capable ball (GR_PCLK6_0, bank 6), found +// missing entirely during schematic review -- see fpga_neural_v2_top.v. +LOCATE COMP "sdram_clk" SITE "J4"; IOBUF PORT "sdram_clk" IO_TYPE=LVCMOS33; LOCATE COMP "sdram_cke" SITE "B5"; IOBUF PORT "sdram_cke" IO_TYPE=LVCMOS33; LOCATE COMP "sdram_cs_n" SITE "C5"; IOBUF PORT "sdram_cs_n" IO_TYPE=LVCMOS33; LOCATE COMP "sdram_ras_n" SITE "C4"; IOBUF PORT "sdram_ras_n" IO_TYPE=LVCMOS33; diff --git a/hardware/v2/nms/rtl/fpga_neural_v2_top.v b/hardware/v2/nms/rtl/fpga_neural_v2_top.v index 15a3688..6d2fd59 100644 --- a/hardware/v2/nms/rtl/fpga_neural_v2_top.v +++ b/hardware/v2/nms/rtl/fpga_neural_v2_top.v @@ -56,6 +56,12 @@ module fpga_neural_v2_top #( input wire spi_cs_n, // ---- single physical SDRAM (weights + activations + results) ---- + // sdram_clk: the real SDRAM chip's own CLK pin -- an external + // chip, it needs this driven from a real output ball, NOT just + // internal routing. Found missing entirely during this session's + // schematic review (clk_sys was purely internal, never reached a + // pad) -- added here, real free clock-capable ball (bank 6). + output wire sdram_clk, output wire sdram_cke, output wire sdram_cs_n, output wire sdram_ras_n, @@ -82,6 +88,8 @@ module fpga_neural_v2_top #( .clk_16mhz(osc_clk), .clk_sys(clk_sys), .locked(pll_locked) ); + assign sdram_clk = clk_sys; + wire clk = clk_sys; wire rst; reset_sync u_reset_sync (