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exp: N=8 packed-core array real P&R, isolates placement density from interconnect (EXP-0060)

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New hardware/v3/rtl/np_packed_array.v: flat array of 8 unmodified
neural_processor_packed.v instances, fully independent I/O, zero
shared arbiter/Director logic -- isolates exactly one variable
(DSP/placement density) from EXP-0059's single-core baseline.

Real Vivado post-route: 64/240 DSP48E1 (26.67%), WNS -2.592ns @
200MHz -> Fmax ~131.7MHz, only -2.4% vs the single-core 134.9MHz.
Placement density alone is NOT the main driver of the ECP5-era gap
between isolated-core and full-system Fmax -- narrows the question
for the still-unbuilt real Director/arbiter/memory integration.

Full writeup in hardware/v2/logs/experiments.log EXP-0060.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-16 23:29:54 +02:00
co-authored by Claude Sonnet 5
parent 34b15cc0a7
commit 94b63705be
3 changed files with 139 additions and 0 deletions
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hardware/v3/synth/synth_np_packed_array_n8.tcl
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/neural_processor_packed.v
read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/np_packed_array.v
synth_design -top np_packed_array -part xc7a100tcsg324-1 -mode out_of_context -generic N_CORES=8
create_clock -name clk -period 5.000 [get_ports clk]
opt_design
report_utilization -file /tmp/util_np_array_n8_postsynth.rpt
place_design
route_design
report_utilization -file /tmp/util_np_array_n8_postroute.rpt
report_timing_summary -file /tmp/timing_np_array_n8_postroute.rpt
write_checkpoint -force /tmp/np_array_n8_postroute.dcp