feat(v2): M6 Dependency Manager, multi-dependency wake-up
Implements M6: dependency_manager.v tracks a table of node
descriptors (node_id/state/required_dependencies/resolved_
dependencies/producer_ids -- §10's exact field list), incrementing a
waiting node's resolved count whenever one of its listed producers
completes, transitioning it to READY once resolved==required, and
dispatching ready nodes to the Neural Director (M5) one at a time via
a backpressure-safe valid/ready interface.
Verified with Verilator on a small hand-built DAG: node0/node1 have no
dependencies (dispatch immediately); node2 depends on BOTH node0 AND
node1 ("dipendenze multiple") and stays WAITING until both complete,
confirmed via an explicit negative check after only one resolves;
node3 depends on node0 ALONE, demonstrating a single producer
("node0") satisfying two different consumers' dependencies
("risultati condivisi... piu' consumer") -- node3 fully, node2
partially. 4/4 tests pass.
Scope for this milestone (decisions.log DEC-0008): dependency
COUNTING/readiness only, no direct producer-to-consumer value
forwarding (§11 frames that as a "quando possibile" optimization, not
a correctness requirement -- deferred until real bandwidth
measurements justify it) and no node-slot reclamation after dispatch
(not exercised by any scenario built so far).
Real synthesis: 0 CHECK problems, 763 LUT4/474 FF/0 DSP/0 CCU2C. Real
place&route (module fits the TRELLIS_IO budget as a bare top-level
this time, no harness needed): Fmax 155.30 MHz, PASS at 80MHz.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
@@ -81,3 +81,10 @@ timing harness -- see errors.log ERR-0005)
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| Module | Fmax (POST-P&R) | LUT | FF | DSP | CCU2C |
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|------------------|------------------|-----|-----|-----|-------|
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| neural_director (N_SLOTS=4) | 250.50 MHz | 382 | 366 | 0 | 4 |
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[2026-09-05] M6 Dependency Manager (real standalone synthesis + P&R,
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no harness needed)
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| Module | Fmax (POST-P&R) | LUT | FF | DSP | CCU2C |
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|----------------------|------------------|-----|-----|-----|-------|
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| dependency_manager (N_NODES=16) | 155.30 MHz | 763 | 474 | 0 | 0 |
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@@ -389,3 +389,69 @@ experimentally-driven milestone per §9's own text.
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STATUS:
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ACCEPTED
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---
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DEC-0008
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DATE: 2026-09-05
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DECISION:
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dependency_manager.v (M6) does NOT implement §11's direct producer-
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to-consumer VALUE forwarding (bypassing the Result Buffer/external-
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memory round-trip). It tracks dependency COUNTS and READINESS only --
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"has this node's data become available", resolved via a
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producer_done_node_id tag matched against each waiting node's own
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producer_ids list. A ready node's job descriptor still points at
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result_addr (wherever the Memory Manager, M4, wrote the producer's
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actual result), which is how a consumer finds its real input data
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today. Additionally, node table slots are NOT reclaimed after
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dispatch (ST_DISPATCHED is terminal) -- a full graph run allocates its
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N_NODES once, not a reusable pool.
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WHY:
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§11 itself frames forwarding as an optimization ("quando possibile"),
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not a correctness requirement -- the dependency-COUNTING mechanism
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(§10's actual explicit field list: node_id/state/required_dependencies/
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resolved_dependencies/producer_information) is what gates correct
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scheduling; forwarding is a bandwidth/latency optimization on top of
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an already-correct base. Implementing real value forwarding would
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require reworking the Neural Processor's operand path (M1) and Memory
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Manager's fetch path (M4) to support a bypass source in addition to
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PSRAM -- a bigger change that should be justified by real measured
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data (§22/§30: no invented results) showing memory bandwidth is
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actually the bottleneck, not assumed now. Slot non-reclamation is
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similarly a scope choice: reclaiming/reusing node table entries mid-run
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only matters for graphs that run longer than N_NODES distinct node
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launches, or that need dynamic re-registration -- not exercised by
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this milestone's own test (a bounded DAG, registered once, run once).
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EVIDENCE:
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hardware/v2/sim/tb_dependency_manager.v -- 4/4 tests pass demonstrating
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multi-dependency (node2 needs both node0 AND node1) and shared-
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producer/multi-consumer wake-up (node0's single completion correctly
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satisfies both node3 fully and node2 partially) using ONLY the
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counting mechanism, no forwarded values -- confirming the counting-
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only design is sufficient for correct scheduling.
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ALTERNATIVES:
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1. Implement value forwarding now (Producer -> Consumer FIFO directly,
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per §11's diagram). Rejected: no measured evidence yet that the
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PSRAM round-trip is a real bottleneck (§22 measurements are M9's
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job); adding it now would be exactly the kind of unmeasured,
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assumption-driven change §30 warns against.
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2. Reclaim/reuse node table slots after dispatch. Rejected: adds
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real complexity (a free-list, or requiring producer_done for a
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DISPATCHED node to also clear it) for a scenario (graphs needing
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more distinct node launches than N_NODES, or dynamic re-
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registration) this milestone's test doesn't exercise -- revisit if
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a real M7+ integration scenario needs it.
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RESULT:
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dependency_manager.v as implemented: pure dependency-count tracking,
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first-found-ready dispatch to the Director (M5), no value forwarding,
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no slot reclamation. Both explicitly noted as deferred, not silently
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missing.
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STATUS:
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ACCEPTED
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@@ -159,3 +159,25 @@ errors: nessun bug RTL, solo 2 bug di testbench (vedi experiments.log
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EXP-0006).
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decision: vedi decisions.log DEC-0007.
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next_action: M6 -- dependency_manager.v.
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[2026-09-05T18:00:00Z] commit=2e4cedc session=v2-M6-dependency-manager
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module: hardware/v2/rtl/dependency_manager.v
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action: implementato M6 -- tabella di dipendenze (node_id/state/
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required/resolved/producer_ids, campi esatti §10), wake-up su
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completamento produttore, dispatch first-found-ready verso il
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Director (M5).
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reason: roadmap M6.
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result: 4/4 test PASS su un piccolo DAG a mano (node2 dipende da
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ENTRAMBI node0+node1 -- dipendenze multiple; node3 dipende solo da
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node0 -- risultato condiviso/piu' consumer). Confermato: node3 pronto
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subito dopo node0, node2 resta WAITING finche' anche node1 non
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completa. Sintesi reale: 0 problemi, 763 LUT4/474 FF/0 DSP/0 CCU2C.
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Fmax reale (nessun harness necessario stavolta): 155.30 MHz.
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errors: un errore di sintassi nel testbench (nested replication senza
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livello di parentesi extra), non un bug RTL.
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decision: vedi decisions.log DEC-0008 (nessun forwarding di valori
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ancora, nessun riuso degli slot ancora -- entrambi rimandati
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esplicitamente).
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next_action: M7 -- dataflow_core.v, prima integrazione di
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Director+Dependency Manager+Memory Manager+Processor Array+Buffer
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in un unico top-level.
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@@ -322,3 +322,46 @@ next_action: M6 -- dependency_manager.v (ready/waiting queue,
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dependency counters, wake-up, producer tracking) -- the first
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milestone where job READINESS itself, not just free-slot dispatch,
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becomes the Director's actual gating condition.
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EXP-0007
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timestamp: 2026-09-05T18:00:00Z
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git_commit: 2e4cedc (+ uncommitted M6 work)
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session: v2-M6-dependency-manager
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module: hardware/v2/rtl/dependency_manager.v
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configuration: N_NODES=8 (sim), N_NODES=16 (synth default),
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MAX_DEPS=4, ADDR_WIDTH=23
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action: M6 -- dependency-count tracking table (node_id/state/
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required_dependencies/resolved_dependencies/producer_ids, §10
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exact field list), first-found-ready dispatch to the Director.
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command (sim, Verilator): verilator --binary --timing -j 0 -Wno-fatal
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--top-module tb -o /tmp/vtb_dep hardware/v2/rtl/dependency_manager.v
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hardware/v2/sim/tb_dependency_manager.v && /tmp/vtb_dep
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command (synth/timing): yosys -p "synth_ecp5 -json .../top.json -top
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dependency_manager" hardware/v2/rtl/dependency_manager.v;
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nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80
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--lpf-allow-unconstrained (no timing harness needed this time --
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module's ports fit within the TRELLIS_IO budget as a bare top-level).
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result:
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SIMULATED: 4/4 tests PASS on a small hand-built DAG (node0, node1:
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no dependencies; node2: depends on BOTH node0 and node1 --
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"dipendenze multiple"; node3: depends on node0 ALONE -- "risultati
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condivisi... piu' consumer"): node0/node1 dispatch immediately;
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node3 becomes READY the cycle node0's producer_done arrives (before
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node1 completes); node2 stays WAITING until BOTH node0 AND node1
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have completed, confirmed by an explicit negative check (still
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WAITING after only one of its two dependencies resolved).
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SYNTHESIZED: 0 CHECK problems, 763 LUT4, 474 TRELLIS_FF, 0 DSP,
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0 CCU2C.
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POST-P&R (real, no harness needed): Fmax = 155.30 MHz, PASS at
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80MHz.
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errors: one testbench syntax error (nested nonblocking nested-
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replication `{(N){M{1'b0}}}` needs an extra brace level, Verilator
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correctly rejected it) -- fixed by building reg_producer_ids via
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explicit bit-slice assignment instead of one big concatenation
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expression. Not an RTL bug.
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decision: see decisions.log DEC-0008 (no value forwarding yet, no
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slot reclamation yet -- both explicitly deferred, not missing by
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oversight).
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next_action: M7 -- dataflow_core.v, integrating Director + Dependency
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Manager + Memory Manager + Processor Array + Buffers into one top-
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level module for the first time.
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@@ -54,3 +54,9 @@ test: 4 cases (3-jobs-2-slots first-free dispatch + queueing,
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backpressure fill/recover)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS
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[2026-09-05] EXP-0007 -- hardware/v2/sim/tb_dependency_manager.v
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test: 4 cases on a 4-node DAG (2 independent + 1 dual-dependency +
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1 single-dependency-shared-producer)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS
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@@ -43,3 +43,6 @@ LUT4=851 TRELLIS_FF=789 CCU2C=108 MULT18X18D=0 (expected, no
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[2026-09-05] EXP-0006 -- neural_director (N_SLOTS=4, standalone)
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LUT4=382 TRELLIS_FF=366 CCU2C=4 DSP=0. CHECK: 0 problems.
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[2026-09-05] EXP-0007 -- dependency_manager (N_NODES=16, MAX_DEPS=4)
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LUT4=763 TRELLIS_FF=474 CCU2C=0 DSP=0. CHECK: 0 problems.
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@@ -49,3 +49,8 @@ Fmax: 165.86 MHz -- PASS at 80MHz (real place&route measurement)
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see errors.log ERR-0005 for why), real nextpnr-ecp5 --45k --package
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CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 250.50 MHz -- PASS at 80MHz (real place&route measurement)
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[2026-09-05] EXP-0007 -- dependency_manager (N_NODES=16, standalone,
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no harness needed), real nextpnr-ecp5 --45k --package CABGA381
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--speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 155.30 MHz -- PASS at 80MHz (real place&route measurement)
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