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docs: real P&R signoff for the result-writeback engine (EXP-0088)

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Real in-context P&R confirms the result-writeback engine (EXP-0088)
closes timing with essentially zero cost: WNS=+0.099962ns (vs
EXP-0086's +0.095707ns), WHS=+0.036275ns, 0 failing endpoints. 6642
LUTs (+260 for the new engine), 16 DSP48E1 unchanged. This is now the
current, trustworthy signoff, promoted over EXP-0086/0087's own
pointers in both docs.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
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michele
2026-09-20 19:27:00 +02:00
co-authored by Claude Sonnet 5
parent ccaf3ee059
commit 7f9ece12dc
3 changed files with 53 additions and 12 deletions
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@@ -5918,3 +5918,33 @@ disturb the closed EXP-0086 timing), then real N=2/4/8/16 core-count
scaling tests (each with its own real P&R signoff, per the user's own
standing directive), then the 4x4 hybrid systolic architecture
(docs/ARCHITECTURE_ANALYSIS.md S5.6, currently exploratory/not built).
EXP-0088 (continued) -- real P&R signoff for the result-writeback
engine: CLOSED, no regression
Real, in-context P&R (synth_design + opt_design + place_design +
route_design, xc7a100tcsg324-2, EXP-0088's real committed RTL/XDC):
**WNS = +0.099962ns, WHS = +0.036275ns**, 0 failing endpoints out of
27868 (setup) / 27865 (hold) / 10529 (pulse width). "All user specified
timing constraints are met." Real utilization: 6642 LUTs (vs EXP-0086's
6382, +260, expected for the new result_writeback.v logic added to
both slots), 16 DSP48E1 (unchanged, writeback adds no DSP usage).
Essentially unchanged margin from EXP-0086's own +0.095707ns (tiny
+0.004ns difference, normal P&R placement-seed variance, not a real
effect of this change) -- the real, hard N-scaling pin blocker is now
closed with ZERO real timing cost.
DECISION: confirmed keep. This is now the real, current, trustworthy
P&R signoff, superseding EXP-0086/0087's own (which didn't yet include
result_writeback.v).
next_action: real N=2/4/8/16 core-count scaling tests (each with its
own real P&R signoff) OR the 4x4 hybrid systolic architecture
(docs/ARCHITECTURE_ANALYSIS.md S5.6) -- per the user's own explicit
reprioritization (2026-09-20), the systolic architecture is next,
scoped to a first, isolated, standalone-verified deliverable
(systolic_group.v: one group of 4 weight-sharing PEs, broadcast
design confirmed by the user -- NOT a literal PE-to-PE systolic shift
register -- verified in isolation before any Director/SPI-protocol
integration, matching this project's own "one variable at a time"
discipline).