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docs: real P&R signoff for the result-writeback engine (EXP-0088)

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Real in-context P&R confirms the result-writeback engine (EXP-0088)
closes timing with essentially zero cost: WNS=+0.099962ns (vs
EXP-0086's +0.095707ns), WHS=+0.036275ns, 0 failing endpoints. 6642
LUTs (+260 for the new engine), 16 DSP48E1 unchanged. This is now the
current, trustworthy signoff, promoted over EXP-0086/0087's own
pointers in both docs.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
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michele
2026-09-20 19:27:00 +02:00
co-authored by Claude Sonnet 5
parent ccaf3ee059
commit 7f9ece12dc
3 changed files with 53 additions and 12 deletions
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docs/PHYSICAL_REALIZATION.md
+7 -6
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@@ -165,7 +165,7 @@ these from an ESP32 doing real JTAG bit-banging (TAP state machine, IR/DR
shifting) rather than a bench programmer — that firmware is separate,
software-side work, not covered here.
## 3. Real timing signoff (EXP-0086, the current, trustworthy number — real 32-bit DDR3 channel, CLOSED)
## 3. Real timing signoff (EXP-0088, the current, trustworthy number — real 32-bit DDR3 channel + result-writeback engine, CLOSED)
Real in-context Vivado place-and-route (not out-of-context, not estimated):
@@ -173,16 +173,16 @@ Real in-context Vivado place-and-route (not out-of-context, not estimated):
|---|---|
| DDR3 PHY clock (sys_clk_p/n) | **310.078 MHz** (3.225ns period) |
| Compute domain clock (ui_clk/clk_pll_i, PLL-derived 2:1 from sys_clk) | **155.039 MHz** |
| WNS (setup slack) | **+0.095707 ns** — real, closed. Re-verify with a fresh P&R after ANY further logic addition. |
| WNS (setup slack) | **+0.099962 ns** — real, closed. Re-verify with a fresh P&R after ANY further logic addition. |
| WHS (hold slack) | +0.036275 ns |
| Failing endpoints | 0 of 25172 (setup), 0 of 25169 (hold), 0 of 9505 (pulse width) |
| LUTs used | 6382 / 63400 (10.07%) |
| Failing endpoints | 0 of 27868 (setup), 0 of 27865 (hold), 0 of 10529 (pulse width) |
| LUTs used | 6642 / 63400 (10.48%) |
| DSP48E1 used | 16 / 240 (6.67%) — 8 per compute core × 2 cores, unchanged since EXP-0059 |
| Bonded IOB used | 119 / 207 (57.49%) |
| Block RAM used | 0 |
| STARTUPE2 used | 1 / 1 (100%) — the config-flash bridge |
| DDR3 channel width | **32-bit real physical channel** (two MT41J128M16JT-125:K chips) — see §3.1 |
| Real physical bandwidth ceiling | **~2.48 GB/s** (2× EXP-0083's 16-bit ~1.24 GB/s, real, closed timing — not a projection) |
| Result writeback | **real, into DDR3** (EXP-0088, `result_writeback.v`) — no longer literal top-level pins, see §4.6/§5.3 of `docs/ARCHITECTURE_ANALYSIS.md` |
Signoff history (every real change, same target, in-context P&R):
@@ -195,7 +195,8 @@ Signoff history (every real change, same target, in-context P&R):
| 0082 (+denser activation packing) | +0.068 | 5437 | 16 |
| 0083 (+DDRManager phase 1, `ddr_prefetch_mgr.v`, 16-bit) | +0.073 | 5644 | 16 |
| 0084 (32-bit DDR3 widening, 2900ps/172.414MHz) | -0.618 (FAILED) | 6418 | 16 |
| 0086 (32-bit DDR3 widening, clock reverted to 3225ps/155.039MHz) | **+0.096 (CLOSED)** | 6382 | 16 |
| 0086 (32-bit DDR3 widening, clock reverted to 3225ps/155.039MHz) | +0.096 (CLOSED) | 6382 | 16 |
| 0088 (+result-writeback engine, `result_writeback.v`) | **+0.100 (CLOSED)** | 6642 | 16 |
### 3.1 Real 32-bit DDR3 widening — functionally verified AND timing CLOSED (EXP-0084 → EXP-0086)