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docs: real P&R signoff for the result-writeback engine (EXP-0088)

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Real in-context P&R confirms the result-writeback engine (EXP-0088)
closes timing with essentially zero cost: WNS=+0.099962ns (vs
EXP-0086's +0.095707ns), WHS=+0.036275ns, 0 failing endpoints. 6642
LUTs (+260 for the new engine), 16 DSP48E1 unchanged. This is now the
current, trustworthy signoff, promoted over EXP-0086/0087's own
pointers in both docs.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
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michele
2026-09-20 19:27:00 +02:00
co-authored by Claude Sonnet 5
parent ccaf3ee059
commit 7f9ece12dc
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docs/ARCHITECTURE_ANALYSIS.md
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@@ -1,10 +1,11 @@
# FPGA-Neural V3 — Architecture Analysis: Timing, Bottlenecks, and Recommended Interventions
Scope: the current, real, P&R-verified V3 design (`hardware/v3/`, branch
`v3-artix7`), updated through EXP-0086 (32-bit DDR3 widening, functionally
complete AND real timing CLOSED). The current real, trustworthy *timing*
signoff is now EXP-0086 (32-bit, 155.039MHz, WNS +0.096ns), replacing the
prior EXP-0083 16-bit-era pointer. Every number in this document is either
`v3-artix7`), updated through EXP-0088 (result-writeback engine, real,
closed timing). The current real, trustworthy *timing* signoff is now
EXP-0088 (32-bit, 155.039MHz, WNS +0.100ns), replacing EXP-0086's own
pointer (which itself replaced EXP-0083's 16-bit-era one). Every number
in this document is either
directly measured (real simulation trace, real P&R report) or a calculation
built from directly-measured building blocks — the two are labeled
explicitly throughout. Nothing here is guessed.
@@ -81,7 +82,8 @@ absorbed the gap the look-ahead used to hide.
| 0082 | + denser activation packing (2 tiles/burst, EXP-0081) | +0.068 | 5437 | 16 | pre-DDRManager baseline |
| 0083 | + DDRManager phase 1 (`ddr_prefetch_mgr.v`, single-slot look-ahead prefetch) | +0.073 | 5644 | 16 | 16-bit/155.039MHz — superseded by EXP-0086 below |
| 0084 | 32-bit DDR3 widening (2 chips) + clock speedup to 172.414MHz | -0.618 (FAILED) | 6418 | 16 | functionally verified (real xsim), real timing NOT closed — root cause is the clock speedup, not the width; see §5.4.1. |
| 0086 | 32-bit DDR3 widening, clock period reverted to 3225ps/155.039MHz | **+0.096 (CLOSED)** | 6382 | 16 | **current, trustworthy signoff** — real, closed timing, full 2× real bandwidth (§5.4.1). Also uncovered and fixed a real recurrence of the stale-import bug (whole-tree, triggered by MIG regeneration) — see CLAUDE.md. |
| 0086 | 32-bit DDR3 widening, clock period reverted to 3225ps/155.039MHz | +0.096 (CLOSED) | 6382 | 16 | real, closed timing, full 2× real bandwidth (§5.4.1). Also uncovered and fixed a real recurrence of the stale-import bug (whole-tree, triggered by MIG regeneration) — see CLAUDE.md. Superseded by 0088 below. |
| 0088 | + result-writeback engine (`result_writeback.v`, removes the last hard N-scaling pin blocker, §4.6/§5.3) | **+0.100 (CLOSED)** | 6642 | 16 | **current, trustworthy signoff** — essentially unchanged margin, zero real timing cost for closing the pin-scaling blocker. |
**Observation**: WNS does not move monotonically with LUT count (0.056 →
0.013 → 0.030 → 0.068 → 0.073 while LUTs only ever grow) — this is normal P&R behavior
@@ -495,7 +497,15 @@ against `burst_mem_model32.v`. Also re-verified at the full N=2 system
level (`tb_n2_system_ddr3.v`, real xsim against the real, closed
32-bit/3225ps DDR3 model) to confirm the writeback engine behaves
correctly under real shared-bus arbitration contention between 2 slots
— see `hardware/v2/logs/experiments.log` EXP-0088 for the real result.
— **8/8 PASS, 0 errors**.
**Real P&R signoff**: **WNS = +0.099962ns, WHS = +0.036275ns**, 0
failing endpoints, "All user specified timing constraints are met" —
essentially unchanged from EXP-0086's own +0.095707ns (real, closed,
not a regression). 6642 LUTs (+260 vs EXP-0086, expected), 16 DSP48E1
(unchanged). This is now the current, trustworthy P&R signoff,
superseding EXP-0086/0087. See `hardware/v2/logs/experiments.log`
EXP-0088 for the full real result.
### 5.4 [DONE] Widening the physical DDR3 channel: 32-bit single channel vs. a second independent 16-bit channel — **functionally complete AND real timing closed (EXP-0084 → EXP-0086)**