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feat: widen ADDR_WIDTH to 23 bits for full 8MB PSRAM addressing

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Bumps ADDR_WIDTH's default from 22 to 23 bits across every RTL
module (neuron_memory, layer_sequencer, spi_engine, spi_neuron_top,
mem_arbiter, int8_memory_access, memory_interface, psram_controller,
memory_model) and every testbench that mirrors it, so the system's
byte-address space reaches the full 8 MiB the recommended PSRAM part
(ISSI IS66WVE4M16EBLL-70BLI, docs/FPGA-Neural-Hardware-Design.md §3)
actually provides -- previously only 4 MiB (half the chip) was
reachable, since int8_memory_access.v's byte->word address shift
(addr >> 1) turned the old 22-bit byte address into only 21 real word
bits, one short of the chip's real 22-bit word address (A0-A21). At
23 bits, that same shift lands exactly on all 22 chip address lines,
so the whole part is usable now instead of deferred to a future
widening.

Also fixes a stray 22'd11-sized literal in layer_sequencer.v's
descriptor-table address increment (numerically already safe via
Verilog's zero-extension, but now correctly unsized so it always
matches ADDR_WIDTH instead of silently assuming 22).

Updated docs/FPGA-NeuralNetwork-Engine.md's SPI protocol address-field
note (23 bits, top 1 reserved bit instead of 2) and
docs/FPGA-Neural-Hardware-Design.md's PSRAM section (the "chip has
one spare address line" framing is gone now that all 22 are wired
and used).

Full regression (all 11 ADDR_WIDTH-touching testbenches, plus a
Yosys elaboration check of spi_neuron_top with the new default and
no override) passes clean.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
This commit is contained in:
michele
2026-09-02 21:00:46 +02:00
co-authored by Claude Sonnet 5
parent f6edc01613
commit 7e2711fa27
35 changed files with 1745 additions and 1764 deletions
Download Patch File Download Diff File Expand all files Collapse all files
sim/neuron_memory.vcd
+39 -39
View File
@@ -1,5 +1,5 @@
$date
Wed Sep 2 20:14:05 2026
Wed Sep 2 20:58:09 2026
$end
$version
Icarus Verilog
@@ -21,12 +21,12 @@ $var wire 1 * psram_mem_ready $end
$var wire 16 + psram_mem_rdata [15:0] $end
$var wire 1 , psram_lb_n $end
$var wire 1 - psram_ce_n $end
$var wire 22 . psram_a [21:0] $end
$var wire 23 . psram_a [22:0] $end
$var wire 1 / neuron_mem_wr $end
$var wire 8 0 neuron_mem_wdata [7:0] $end
$var wire 1 1 neuron_mem_req $end
$var wire 8 2 neuron_mem_rdata [7:0] $end
$var wire 22 3 neuron_mem_addr [21:0] $end
$var wire 23 3 neuron_mem_addr [22:0] $end
$var wire 1 4 memory_ready $end
$var wire 16 5 memory_rdata [15:0] $end
$var wire 1 6 memory_mem_wr $end
@@ -34,38 +34,38 @@ $var wire 16 7 memory_mem_wdata [15:0] $end
$var wire 1 8 memory_mem_ub_n $end
$var wire 1 9 memory_mem_req $end
$var wire 1 : memory_mem_lb_n $end
$var wire 22 ; memory_mem_addr [21:0] $end
$var wire 23 ; memory_mem_addr [22:0] $end
$var wire 1 < master_wr $end
$var wire 16 = master_wdata [15:0] $end
$var wire 1 > master_ub_n $end
$var wire 1 ? master_req $end
$var wire 1 @ master_lb_n $end
$var wire 22 A master_addr [21:0] $end
$var wire 23 A master_addr [22:0] $end
$var wire 1 B done $end
$var wire 1 C busy $end
$var parameter 32 D ADDR_WIDTH $end
$var real 1 E CLK_PERIOD $end
$var parameter 32 F DATA_WIDTH $end
$var reg 22 G bias_addr [21:0] $end
$var reg 23 G bias_addr [22:0] $end
$var reg 1 H clk $end
$var reg 16 I n_inputs_real [15:0] $end
$var reg 1 J rst $end
$var reg 1 K start $end
$var reg 22 L tb_mem_addr [21:0] $end
$var reg 23 L tb_mem_addr [22:0] $end
$var reg 1 M tb_mem_lb_n $end
$var reg 1 N tb_mem_req $end
$var reg 1 O tb_mem_ub_n $end
$var reg 16 P tb_mem_wdata [15:0] $end
$var reg 1 Q tb_mem_wr $end
$var reg 1 R use_neuron_master $end
$var reg 22 S w_base [21:0] $end
$var reg 22 T x_base [21:0] $end
$var reg 23 S w_base [22:0] $end
$var reg 23 T x_base [22:0] $end
$var integer 32 U cycles_full_nm [31:0] $end
$var integer 32 V cycles_reduced_nm [31:0] $end
$var integer 32 W t_done_nm [31:0] $end
$var integer 32 X t_start_nm [31:0] $end
$scope module u_memory_if $end
$var wire 22 Y addr [21:0] $end
$var wire 23 Y addr [22:0] $end
$var wire 1 H clk $end
$var wire 1 @ lb_n $end
$var wire 1 ? req $end
@@ -79,7 +79,7 @@ $var parameter 32 \ ADDR_WIDTH $end
$var parameter 32 ] DATA_WIDTH $end
$var parameter 2 ^ STATE_IDLE $end
$var parameter 2 _ STATE_WAIT $end
$var reg 22 ` mem_addr [21:0] $end
$var reg 23 ` mem_addr [22:0] $end
$var reg 1 : mem_lb_n $end
$var reg 1 9 mem_req $end
$var reg 1 8 mem_ub_n $end
@@ -91,9 +91,9 @@ $var reg 2 c state [1:0] $end
$upscope $end
$scope module u_neuron $end
$var wire 2 d activation [1:0] $end
$var wire 22 e bias_addr [21:0] $end
$var wire 23 e bias_addr [22:0] $end
$var wire 1 H clk $end
$var wire 22 f mem_addr [21:0] $end
$var wire 23 f mem_addr [22:0] $end
$var wire 8 g mem_rdata [7:0] $end
$var wire 1 ! mem_ready $end
$var wire 1 1 mem_req $end
@@ -103,8 +103,8 @@ $var wire 16 i n_inputs_real [15:0] $end
$var wire 16 j n_neurons_real [15:0] $end
$var wire 1 J rst $end
$var wire 1 K start $end
$var wire 22 k w_base [21:0] $end
$var wire 22 l x_base [21:0] $end
$var wire 23 k w_base [22:0] $end
$var wire 23 l x_base [22:0] $end
$var wire 8 m y_bus [7:0] $end
$var wire 256 n x_bus [255:0] $end
$var wire 256 o w_bus [255:0] $end
@@ -119,7 +119,7 @@ $var wire 1 w access_mem_ub_n $end
$var wire 1 x access_mem_req $end
$var wire 16 y access_mem_rdata [15:0] $end
$var wire 1 z access_mem_lb_n $end
$var wire 22 { access_mem_addr [21:0] $end
$var wire 23 { access_mem_addr [22:0] $end
$var parameter 32 | ACC_WIDTH $end
$var parameter 32 } ADDR_WIDTH $end
$var parameter 32 ~ DATA_WIDTH $end
@@ -133,11 +133,11 @@ $var parameter 4 '" STATE_READ_W $end
$var parameter 4 (" STATE_READ_X $end
$var parameter 4 )" STATE_START_N $end
$var parameter 4 *" STATE_WAIT_N $end
$var reg 22 +" access_addr [21:0] $end
$var reg 23 +" access_addr [22:0] $end
$var reg 1 ," access_req $end
$var reg 8 -" access_wdata [7:0] $end
$var reg 1 ." access_wr $end
$var reg 22 /" bias_group_addr [21:0] $end
$var reg 23 /" bias_group_addr [22:0] $end
$var reg 8 0" bias_reg [7:0] $end
$var reg 1 C busy $end
$var reg 1 B done $end
@@ -145,7 +145,7 @@ $var reg 6 1" index [5:0] $end
$var reg 1 2" neuron_index $end
$var reg 1 3" neuron_start $end
$var reg 4 4" state [3:0] $end
$var reg 22 5" w_group_base [21:0] $end
$var reg 23 5" w_group_base [22:0] $end
$var integer 32 6" rst_i [31:0] $end
$scope begin GEN_BUS[0] $end
$var parameter 2 7" i $end
@@ -247,7 +247,7 @@ $scope begin GEN_Y_BUS[0] $end
$var parameter 2 W" j $end
$upscope $end
$scope module u_mem $end
$var wire 22 X" addr [21:0] $end
$var wire 23 X" addr [22:0] $end
$var wire 1 H clk $end
$var wire 16 Y" mem_rdata [15:0] $end
$var wire 1 ! mem_ready $end
@@ -258,8 +258,8 @@ $var wire 1 ." wr $end
$var parameter 32 [" ADDR_WIDTH $end
$var parameter 2 \" STATE_IDLE $end
$var parameter 2 ]" STATE_WAIT $end
$var reg 22 ^" addr_reg [21:0] $end
$var reg 22 _" mem_addr [21:0] $end
$var reg 23 ^" addr_reg [22:0] $end
$var reg 23 _" mem_addr [22:0] $end
$var reg 1 z mem_lb_n $end
$var reg 1 x mem_req $end
$var reg 1 w mem_ub_n $end
@@ -484,7 +484,7 @@ $var wire 1 ( ub_n $end
$var wire 1 ) oe_n $end
$var wire 1 , lb_n $end
$var wire 1 - ce_n $end
$var wire 22 ($ a [21:0] $end
$var wire 23 ($ a [22:0] $end
$var parameter 32 )$ ADDR_WIDTH $end
$var parameter 32 *$ DATA_WIDTH $end
$var parameter 32 +$ DEPTH $end
@@ -503,7 +503,7 @@ $var real 1 7$ TWC_NS $end
$var real 1 8$ TWPH_NS $end
$var real 1 9$ TWP_NS $end
$var real 1 :$ TWR_NS $end
$var reg 22 ;$ active_addr [21:0] $end
$var reg 23 ;$ active_addr [22:0] $end
$var reg 16 <$ active_wdata [15:0] $end
$var reg 1 =$ dq_oe $end
$var reg 16 >$ dq_out [15:0] $end
@@ -531,7 +531,7 @@ $upscope $end
$upscope $end
$scope module u_psram_ctrl $end
$var wire 1 H clk $end
$var wire 22 P$ mem_addr [21:0] $end
$var wire 23 P$ mem_addr [22:0] $end
$var wire 1 : mem_lb_n $end
$var wire 1 9 mem_req $end
$var wire 1 8 mem_ub_n $end
@@ -550,14 +550,14 @@ $var parameter 3 Z$ STATE_INIT $end
$var parameter 3 [$ STATE_READ $end
$var parameter 3 \$ STATE_WRITE $end
$var parameter 3 ]$ STATE_WRITE_WAIT $end
$var reg 22 ^$ address_reg [21:0] $end
$var reg 23 ^$ address_reg [22:0] $end
$var reg 14 _$ counter [13:0] $end
$var reg 1 `$ dq_oe $end
$var reg 16 a$ dq_out [15:0] $end
$var reg 1 b$ lb_reg $end
$var reg 16 c$ mem_rdata [15:0] $end
$var reg 1 * mem_ready $end
$var reg 22 d$ psram_a [21:0] $end
$var reg 23 d$ psram_a [22:0] $end
$var reg 1 - psram_ce_n $end
$var reg 1 , psram_lb_n $end
$var reg 1 ) psram_oe_n $end
@@ -570,27 +570,27 @@ $var reg 16 g$ wdata_reg [15:0] $end
$var reg 1 h$ wr_reg $end
$upscope $end
$scope task preload_bias $end
$var reg 22 i$ addr_i [21:0] $end
$var reg 23 i$ addr_i [22:0] $end
$var reg 8 j$ value [7:0] $end
$upscope $end
$scope task preload_vector $end
$var reg 22 k$ base [21:0] $end
$var reg 23 k$ base [22:0] $end
$var reg 8 l$ value [7:0] $end
$var integer 32 m$ k [31:0] $end
$upscope $end
$scope task preload_vector_n $end
$var reg 22 n$ base [21:0] $end
$var reg 23 n$ base [22:0] $end
$var reg 8 o$ value [7:0] $end
$var integer 32 p$ k [31:0] $end
$var integer 32 q$ len [31:0] $end
$upscope $end
$scope task preload_weights $end
$var reg 22 r$ base [21:0] $end
$var reg 23 r$ base [22:0] $end
$var reg 8 s$ value [7:0] $end
$var integer 32 t$ k [31:0] $end
$upscope $end
$scope task preload_x_pattern $end
$var reg 22 u$ base [21:0] $end
$var reg 23 u$ base [22:0] $end
$var reg 8 v$ v0 [7:0] $end
$var reg 8 w$ v1 [7:0] $end
$var integer 32 x$ k [31:0] $end
@@ -605,7 +605,7 @@ $var reg 128 |$ test_name [127:0] $end
$var integer 32 }$ elapsed_cycles [31:0] $end
$upscope $end
$scope task tb_write_word $end
$var reg 22 ~$ addr_i [21:0] $end
$var reg 23 ~$ addr_i [22:0] $end
$var reg 16 !% data_i [15:0] $end
$upscope $end
$upscope $end
@@ -621,7 +621,7 @@ b10111011100000 X$
b10000 W$
b1110 V$
b1010000 U$
b10110 T$
b10111 T$
b110 S$
r0 :$
r46 9$
@@ -640,7 +640,7 @@ r70 -$
r70 ,$
b100000000000000 +$
b10000 *$
b10110 )$
b10111 )$
b0 &$
b10 %$
b1 $$
@@ -705,7 +705,7 @@ b0 o"
b100000 n"
b1 ]"
b0 \"
b10110 ["
b10111 ["
b0 W"
b11111 V"
b11110 U"
@@ -750,15 +750,15 @@ b1 #"
b100000 ""
b1 !"
b1000 ~
b10110 }
b10111 }
b100000 |
b1 _
b0 ^
b10000 ]
b10110 \
b10111 \
b10000 F
r12.5 E
b10110 D
b10111 D
$end
#0
$dumpvars