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feat: widen ADDR_WIDTH to 23 bits for full 8MB PSRAM addressing

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Bumps ADDR_WIDTH's default from 22 to 23 bits across every RTL
module (neuron_memory, layer_sequencer, spi_engine, spi_neuron_top,
mem_arbiter, int8_memory_access, memory_interface, psram_controller,
memory_model) and every testbench that mirrors it, so the system's
byte-address space reaches the full 8 MiB the recommended PSRAM part
(ISSI IS66WVE4M16EBLL-70BLI, docs/FPGA-Neural-Hardware-Design.md §3)
actually provides -- previously only 4 MiB (half the chip) was
reachable, since int8_memory_access.v's byte->word address shift
(addr >> 1) turned the old 22-bit byte address into only 21 real word
bits, one short of the chip's real 22-bit word address (A0-A21). At
23 bits, that same shift lands exactly on all 22 chip address lines,
so the whole part is usable now instead of deferred to a future
widening.

Also fixes a stray 22'd11-sized literal in layer_sequencer.v's
descriptor-table address increment (numerically already safe via
Verilog's zero-extension, but now correctly unsized so it always
matches ADDR_WIDTH instead of silently assuming 22).

Updated docs/FPGA-NeuralNetwork-Engine.md's SPI protocol address-field
note (23 bits, top 1 reserved bit instead of 2) and
docs/FPGA-Neural-Hardware-Design.md's PSRAM section (the "chip has
one spare address line" framing is gone now that all 22 are wired
and used).

Full regression (all 11 ADDR_WIDTH-touching testbenches, plus a
Yosys elaboration check of spi_neuron_top with the new default and
no override) passes clean.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
This commit is contained in:
michele
2026-09-02 21:00:46 +02:00
co-authored by Claude Sonnet 5
parent f6edc01613
commit 7e2711fa27
35 changed files with 1745 additions and 1764 deletions
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rtl/layer_sequencer.v
+2 -2
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@@ -45,7 +45,7 @@
// ================================================================
module layer_sequencer #(
parameter ADDR_WIDTH = 22,
parameter ADDR_WIDTH = 23,
parameter DATA_WIDTH = 8,
parameter N_WIDTH = 256, // = neuron_memory's N_INPUTS = N_NEURONS
parameter N_LAYERS = 4
@@ -314,7 +314,7 @@ module layer_sequencer #(
cur_sel <= write_sel;
write_sel <= ~write_sel;
layer_idx <= layer_idx + 8'd1;
desc_table_addr <= desc_table_addr + 22'd11;
desc_table_addr <= desc_table_addr + 11;
desc_byte_idx <= 4'd0;
state <= ST_READ_DESC;