feat: widen ADDR_WIDTH to 23 bits for full 8MB PSRAM addressing

Bumps ADDR_WIDTH's default from 22 to 23 bits across every RTL
module (neuron_memory, layer_sequencer, spi_engine, spi_neuron_top,
mem_arbiter, int8_memory_access, memory_interface, psram_controller,
memory_model) and every testbench that mirrors it, so the system's
byte-address space reaches the full 8 MiB the recommended PSRAM part
(ISSI IS66WVE4M16EBLL-70BLI, docs/FPGA-Neural-Hardware-Design.md §3)
actually provides -- previously only 4 MiB (half the chip) was
reachable, since int8_memory_access.v's byte->word address shift
(addr >> 1) turned the old 22-bit byte address into only 21 real word
bits, one short of the chip's real 22-bit word address (A0-A21). At
23 bits, that same shift lands exactly on all 22 chip address lines,
so the whole part is usable now instead of deferred to a future
widening.

Also fixes a stray 22'd11-sized literal in layer_sequencer.v's
descriptor-table address increment (numerically already safe via
Verilog's zero-extension, but now correctly unsized so it always
matches ADDR_WIDTH instead of silently assuming 22).

Updated docs/FPGA-NeuralNetwork-Engine.md's SPI protocol address-field
note (23 bits, top 1 reserved bit instead of 2) and
docs/FPGA-Neural-Hardware-Design.md's PSRAM section (the "chip has
one spare address line" framing is gone now that all 22 are wired
and used).

Full regression (all 11 ADDR_WIDTH-touching testbenches, plus a
Yosys elaboration check of spi_neuron_top with the new default and
no override) passes clean.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt

docs/FPGA-NeuralNetwork-Engine.md

@@ -400,9 +400,10 @@ here). The FPGA is always SPI slave. One command per CS-low period;
 byte 0 of every transaction is the opcode.
 
 **Multi-byte fields** are big-endian (most significant byte first).
-Byte addresses are `ADDR_WIDTH`-bit (22 bits today, from
-`rtl/neuron_memory.v`), carried in a 3-byte field with the top 2 bits
-reserved as 0.
+Byte addresses are `ADDR_WIDTH`-bit (23 bits today, from
+`rtl/neuron_memory.v` — sized for a full 8 MiB PSRAM, see
+`docs/FPGA-Neural-Hardware-Design.md` §3), carried in a 3-byte field
+with the top bit reserved as 0.
 
 **Length is explicit**, not CS-edge-delimited: `WRITE_RAM`/`READ_RAM`
 carry a 2-byte length field, so the SPI controller only needs a byte