feat(v2): M7 Dataflow Core - full M1-M6 integration, wake-up loop closed end-to-end
dataflow_core.v integrates dependency_manager (M6) -> neural_director (M5) -> N_SLOTS x (memory_manager (M4) + neural_processor (M1)) for the first time. A slot's completion (via neural_director's new slot_node_id tracking, an additive port) feeds back as a producer_done event to dependency_manager, waking up any node that depended on it - closing the dataflow loop without external glue. Verified end-to-end (Verilator) on a 3-node DAG: two independent nodes plus a third depending on both, confirmed to dispatch only after both genuinely complete via real neural_processor computation. 4/4 PASS. Real synthesis + nextpnr-ecp5 P&R via a synthesis-only timing harness (bare per-slot backend ports exceed the LFE5U-45F's TRELLIS_IO budget, same pattern as ERR-0005): N_SLOTS=2 -> 165.15 MHz, N_SLOTS=4 -> 133.19 MHz, both PASS at 80MHz, 0 synthesis problems. Scope explicitly deferred to M8 (DEC-0009): M3's BRAM buffers not wired in yet, per-slot Memory Backend Interface ports not arbitrated to one shared PSRAM master yet - both need real measured data before committing to a design, not guessed at here. Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0009)/ experiments (EXP-0008)/errors (ERR-0007, a Yosys chparam-ordering build quirk, not an RTL bug)/development.log, ROADMAP.md updated. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
@@ -36,7 +36,16 @@ reali, non solo scritto).
|
||||
PASS (dipendenze multiple + produttore condiviso/piu' consumer).
|
||||
Fmax 155.30 MHz. Forwarding di valori e riuso slot rimandati
|
||||
(`logs/decisions.log` DEC-0008).
|
||||
- [ ] **M7 — Dataflow Core** (`dataflow_core.v`), integrazione completa.
|
||||
- [x] **M7 — Dataflow Core** (`dataflow_core.v`), prima integrazione
|
||||
completa: Dependency Manager (M6) -> Neural Director (M5) ->
|
||||
N_SLOTS x (Memory Manager (M4) + Neural Processor (M1)), loop di
|
||||
wake-up chiuso end-to-end. 4/4 test PASS su un DAG a 3 nodi (node2
|
||||
dipende da entrambi node0+node1, dispatch confermato solo dopo che
|
||||
ENTRAMBI completano davvero). Sintesi reale 0 problemi a
|
||||
N_SLOTS=2 e N_SLOTS=4. Fmax reale (harness): 165.15 MHz
|
||||
(N_SLOTS=2), 133.19 MHz (N_SLOTS=4). Buffer M3 e arbitraggio PSRAM
|
||||
condiviso rimandati esplicitamente a M8 (`logs/decisions.log`
|
||||
DEC-0009).
|
||||
- [ ] **M8 — PSRAM integration**, controller V1 non modificato, misura reale.
|
||||
- [ ] **M9 — Full benchmark**, tabella V1 vs V2 (§32 del mandato).
|
||||
- [ ] **M10 — Optimization**, solo sulla base dei dati raccolti in M1-M9.
|
||||
|
||||
@@ -88,3 +88,18 @@ no harness needed)
|
||||
| Module | Fmax (POST-P&R) | LUT | FF | DSP | CCU2C |
|
||||
|----------------------|------------------|-----|-----|-----|-------|
|
||||
| dependency_manager (N_NODES=16) | 155.30 MHz | 763 | 474 | 0 | 0 |
|
||||
|
||||
[2026-09-05] M7 Dataflow Core (full M1-M6 integration; resources via
|
||||
real standalone synthesis, Fmax via timing harness -- see errors.log
|
||||
ERR-0005)
|
||||
|
||||
| Module (config) | Fmax (POST-P&R) | LUT4 | CCU2C | FF | DSP | BRAM |
|
||||
|-------------------------------|------------------|------|-------|------|-----|------|
|
||||
| dataflow_core (N_SLOTS=2) | 165.15 MHz | 2127 | 248 | 2505 | 16 | 0 |
|
||||
| dataflow_core (N_SLOTS=4) | 133.19 MHz | 3953 | 500 | 4688 | 32 | 0 |
|
||||
|
||||
DSP budget on the LFE5U-45F is 72 MULT18X18D total: N_SLOTS=4 already
|
||||
uses 32/72 (44%), consistent with DEC-0005's finding that DSP, not
|
||||
LUT/FF, is the first resource to saturate as concurrency grows (M2's
|
||||
own N_PROCESSORS=8 measurement: 88%). BRAM=0 on both is expected --
|
||||
M3's buffers are not wired into dataflow_core yet (DEC-0009).
|
||||
|
||||
@@ -455,3 +455,69 @@ missing.
|
||||
|
||||
STATUS:
|
||||
ACCEPTED
|
||||
DEC-0009
|
||||
|
||||
DATE: 2026-09-05
|
||||
|
||||
DECISION:
|
||||
dataflow_core.v (M7) integrates dependency_manager (M6) -> neural_director
|
||||
(M5) -> N_SLOTS x (memory_manager (M4) + neural_processor (M1)), closing
|
||||
the wake-up loop end-to-end for the first time. Two things are
|
||||
deliberately NOT done in this module: (1) M3's BRAM-backed buffers
|
||||
(activation_buffer/weight_buffer/result_buffer) are not instantiated
|
||||
anywhere inside it; (2) each slot's byte-level Memory Backend Interface
|
||||
is exposed as its own SEPARATE port (slot_mem_req/wr/addr/wdata/rdata/
|
||||
ready, arrayed by N_SLOTS) rather than arbitrated down to one shared
|
||||
PSRAM master.
|
||||
|
||||
WHY:
|
||||
(1) §15's own diagram places the Memory Manager -> Memory Backend
|
||||
Interface -> PSRAM Controller path on one side, with M3's buffers
|
||||
belonging as an on-chip cache concept, not a mandatory pass-through --
|
||||
each memory_manager instance already owns its own prefetch double
|
||||
buffer (M4) for the fast path it actually needs, and no measured
|
||||
benchmark yet shows a real need for an additional shared cache layer
|
||||
(§22/§30: no invented results/optimizations). (2) real PSRAM has
|
||||
exactly ONE physical port; N_SLOTS>1 memory_manager instances wanting
|
||||
concurrent access is fundamentally an arbitration problem, and building
|
||||
an arbiter now, before M8's real-toolchain measurement of what
|
||||
contention actually looks like end-to-end with the real (unmodified)
|
||||
V1 PSRAM chain, risks designing to a guess instead of to data.
|
||||
|
||||
EVIDENCE:
|
||||
hardware/v2/sim/tb_dataflow_core.v -- 4/4 tests PASS on a 3-node DAG
|
||||
run through the full stack with each slot backed by its own
|
||||
independent behavioral memory (deliberately NOT the real shared V1
|
||||
PSRAM chain, for exactly the reason above): node0 and node1 (no
|
||||
dependencies) both complete correctly via real neural_processor
|
||||
computation, and node2 (depends on BOTH) is only dispatched after
|
||||
BOTH genuinely finish -- continuously polled every cycle, not just
|
||||
checked at the end -- proving the producer_done wake-up loop closes
|
||||
correctly with real M1/M4/M5/M6 hardware in between, not just
|
||||
between M5 and M6 in isolation (already proven separately by their
|
||||
own testbenches).
|
||||
|
||||
ALTERNATIVES:
|
||||
1. Wire a naive round-robin N-port arbiter in front of one shared
|
||||
PSRAM master now. Rejected: M8's own roadmap text is explicit
|
||||
("Integrare il controller V1 senza modificarlo inizialmente.
|
||||
Misurare il comportamento reale.") -- arbitration design should
|
||||
follow a real measurement of contention under the real PSRAM
|
||||
latency model, not be guessed at during M7's own scope (proving
|
||||
the dependency/scheduling loop closes, not memory sharing).
|
||||
2. Instantiate M3's buffers as a shared cache in front of each slot's
|
||||
Memory Backend Interface now. Rejected: no benchmark yet shows
|
||||
PSRAM bandwidth or latency is actually a bottleneck for the
|
||||
dependency-graph workloads this module targets -- premature
|
||||
without measured justification.
|
||||
|
||||
RESULT:
|
||||
dataflow_core.v as implemented: N_SLOTS independent Memory Backend
|
||||
Interface ports, no M3 buffers wired in. Both explicitly deferred to
|
||||
M8 (shared PSRAM integration/arbitration) and a future
|
||||
measurement-driven decision (M3 buffer reuse), not missing by
|
||||
oversight.
|
||||
|
||||
STATUS:
|
||||
ACCEPTED
|
||||
|
||||
|
||||
@@ -181,3 +181,28 @@ decision: vedi decisions.log DEC-0008 (nessun forwarding di valori
|
||||
next_action: M7 -- dataflow_core.v, prima integrazione di
|
||||
Director+Dependency Manager+Memory Manager+Processor Array+Buffer
|
||||
in un unico top-level.
|
||||
|
||||
[2026-09-05] M7 -- hardware/v2/rtl/dataflow_core.v
|
||||
reason: roadmap M7 -- first full integration of dependency_manager
|
||||
(M6) + neural_director (M5) + N_SLOTS x (memory_manager (M4) +
|
||||
neural_processor (M1)) into one top-level module, closing the
|
||||
producer-completion -> dependency-wake-up loop end-to-end for the
|
||||
first time. Additive extension to neural_director.v: added a
|
||||
slot_node_id output port (which node_id occupies each slot) so a
|
||||
caller can map a completed slot back to the node_id that just
|
||||
finished -- re-verified M5's own testbench still passes 4/4
|
||||
unaffected.
|
||||
result: 4/4 test PASS on a 3-node DAG (node2 depends on BOTH node0 and
|
||||
node1; confirmed it does NOT dispatch until both genuinely complete,
|
||||
polled every cycle). Real synthesis: 0 problems at both N_SLOTS=2
|
||||
(LUT4=2127/CCU2C=248/FF=2505/DSP=16) and N_SLOTS=4
|
||||
(LUT4=3953/CCU2C=500/FF=4688/DSP=32). Real Fmax (via
|
||||
harness_dataflow_core.v): 165.15 MHz (N_SLOTS=2), 133.19 MHz
|
||||
(N_SLOTS=4), both PASS at 80MHz.
|
||||
errors: one Yosys build-script usage quirk (errors.log ERR-0007,
|
||||
chparam target ordering), not an RTL bug.
|
||||
decision: see decisions.log DEC-0009 (M3 buffers not wired in yet, no
|
||||
shared-PSRAM arbitration across slots yet -- both deferred to M8).
|
||||
next_action: M8 -- PSRAM integration. Wire the real (unmodified) V1
|
||||
PSRAM backend chain through dataflow_core end-to-end and measure/
|
||||
design whatever N_SLOTS>1 arbitration real contention requires.
|
||||
|
||||
@@ -176,3 +176,30 @@ VERIFICATION: hardware/v2/sim/tb_memory_manager.v -- 3/3 tests PASS
|
||||
signal inspection).
|
||||
STATUS: FIXED, verified end-to-end with the real (unmodified) V1
|
||||
PSRAM backend chain and a real M1 neural_processor.
|
||||
|
||||
ERR-0007 (Yosys usage quirk, WORKED AROUND, not an RTL bug)
|
||||
DATE: 2026-09-05
|
||||
MODULE: hardware/v2/synthesis/harness_dataflow_core.v (build script)
|
||||
SYMPTOM: `chparam -set N_SLOTS 2 dataflow_core` (setting the parameter
|
||||
directly on the NON-top child module, before running `synth_ecp5
|
||||
-top harness_dataflow_core`) synthesizes with no visible error from
|
||||
the chparam/hierarchy commands themselves, but `synth_ecp5` then
|
||||
fails with "Module `\dataflow_core' referenced in module
|
||||
`\harness_dataflow_core' in cell `\dut' is not part of the design" --
|
||||
even though a standalone `hierarchy -top harness_dataflow_core` run
|
||||
(no synth_ecp5) with the exact same chparam succeeds.
|
||||
ROOT CAUSE: harness_dataflow_core.v's own instantiation of
|
||||
dataflow_core explicitly overrides N_SLOTS via its own local
|
||||
parameter (`.N_SLOTS(N_SLOTS)`) -- chparam on the child module's
|
||||
DEFAULT is therefore always shadowed at that instantiation site
|
||||
regardless of its value, and synth_ecp5's own internal re-hierarchy
|
||||
pass (distinct from a standalone `hierarchy` call) does not
|
||||
reconcile a chparam'd-but-never-actually-used child default the
|
||||
same way, dropping the generic module reference instead.
|
||||
WORKAROUND: set the parameter on the TOP module being synthesized
|
||||
instead (`chparam -set N_SLOTS 2 harness_dataflow_core`), letting
|
||||
its own instantiation forward the value down to dataflow_core as
|
||||
designed. Confirmed working for both N_SLOTS=2 and N_SLOTS=4.
|
||||
STATUS: WORKED AROUND. A build-script ordering detail, not a defect in
|
||||
dataflow_core.v or harness_dataflow_core.v themselves -- noted here
|
||||
so a future N_SLOTS sweep (M9/M10) does not re-trip over it.
|
||||
|
||||
@@ -365,3 +365,39 @@ decision: see decisions.log DEC-0008 (no value forwarding yet, no
|
||||
next_action: M7 -- dataflow_core.v, integrating Director + Dependency
|
||||
Manager + Memory Manager + Processor Array + Buffers into one top-
|
||||
level module for the first time.
|
||||
|
||||
[2026-09-05] EXP-0008 -- hardware/v2/rtl/dataflow_core.v (M7, full
|
||||
M1-M6 integration)
|
||||
test: hardware/v2/sim/tb_dataflow_core.v -- a 3-node DAG (node0/node1
|
||||
independent, node2 depends on BOTH) run through the REAL
|
||||
dependency_manager -> neural_director -> N_SLOTS x (memory_manager +
|
||||
neural_processor) chain end-to-end for the first time, each slot
|
||||
backed by its own independent behavioral byte memory (shared real
|
||||
PSRAM arbitration explicitly deferred to M8, decisions.log DEC-0009)
|
||||
simulator: Verilator 5.050 (--binary --timing)
|
||||
PASS/FAIL:
|
||||
SIMULATED: 4/4 PASS -- node0=48, node1=8 (correct real
|
||||
neural_processor computations via the full stack), node2=40
|
||||
dispatched only after BOTH node0 and node1 genuinely completed
|
||||
(continuously polled every cycle, not just checked at the end).
|
||||
SYNTHESIZED (via harness_dataflow_core.v -- see errors.log ERR-0005):
|
||||
N_SLOTS=2: 0 CHECK problems, LUT4=2127, CCU2C=248, TRELLIS_FF=2505,
|
||||
MULT18X18D=16, DP16KD=0.
|
||||
N_SLOTS=4: 0 CHECK problems, LUT4=3953, CCU2C=500, TRELLIS_FF=4688,
|
||||
MULT18X18D=32, DP16KD=0.
|
||||
POST-P&R (real, harness-based): N_SLOTS=2 Fmax=165.15 MHz,
|
||||
N_SLOTS=4 Fmax=133.19 MHz -- both PASS at 80MHz.
|
||||
errors: one Yosys build-script usage quirk (chparam ordering against
|
||||
a non-top module vs synth_ecp5's own internal re-hierarchy pass) --
|
||||
see errors.log ERR-0007. Not an RTL bug; no dataflow_core.v or
|
||||
harness_dataflow_core.v source change needed, only the build command
|
||||
itself.
|
||||
decision: see decisions.log DEC-0009 (no M3 buffers wired in yet, no
|
||||
shared-PSRAM arbitration across slots yet -- both explicitly
|
||||
deferred to M8/a future measurement-driven decision, not missing by
|
||||
oversight).
|
||||
next_action: M8 -- PSRAM integration. Wire the real (unmodified) V1
|
||||
PSRAM backend chain (int8_memory_access -> memory_interface ->
|
||||
psram_controller) end-to-end through dataflow_core, and design/
|
||||
measure whatever N_SLOTS>1 arbitration across ONE physical PSRAM
|
||||
port actually requires.
|
||||
|
||||
@@ -60,3 +60,18 @@ test: 4 cases on a 4-node DAG (2 independent + 1 dual-dependency +
|
||||
1 single-dependency-shared-producer)
|
||||
simulator: Verilator 5.050 (--binary --timing)
|
||||
PASS/FAIL: 4/4 PASS
|
||||
|
||||
[2026-09-05] EXP-0008 -- hardware/v2/sim/tb_dataflow_core.v
|
||||
test: full end-to-end M1-M6 integration through dataflow_core.v (M7),
|
||||
a 3-node DAG (node0/node1 independent, node2 depends on BOTH) run
|
||||
through the REAL dependency_manager -> neural_director -> N_SLOTS x
|
||||
(memory_manager + neural_processor) chain for the first time, each
|
||||
slot backed by its own independent behavioral byte memory
|
||||
simulator: Verilator 5.050 (--binary --timing)
|
||||
PASS/FAIL: 4/4 PASS -- node0=48, node1=8 (both real neural_processor
|
||||
computations via the full stack), node2=40 dispatched only after
|
||||
BOTH node0 and node1 genuinely completed (continuously polled every
|
||||
cycle up to completion, not just checked at the end) -- the
|
||||
dependency-manager-to-director wake-up loop closes correctly
|
||||
end-to-end with real hardware in between, not just in isolation
|
||||
(M6's own testbench already proved the wake-up logic alone)
|
||||
|
||||
@@ -46,3 +46,20 @@ LUT4=382 TRELLIS_FF=366 CCU2C=4 DSP=0. CHECK: 0 problems.
|
||||
|
||||
[2026-09-05] EXP-0007 -- dependency_manager (N_NODES=16, MAX_DEPS=4)
|
||||
LUT4=763 TRELLIS_FF=474 CCU2C=0 DSP=0. CHECK: 0 problems.
|
||||
|
||||
[2026-09-05] EXP-0008 -- dataflow_core (M7 full integration, via
|
||||
harness_dataflow_core.v -- see errors.log ERR-0005 for why a harness
|
||||
is needed: bare per-slot Memory Backend Interface ports alone total
|
||||
280 bits at N_SLOTS=4, exceeding the LFE5U-45F-8BG381's ~245 TRELLIS_IO
|
||||
budget)
|
||||
N_SLOTS=2: LUT4=2127 CCU2C=248 TRELLIS_FF=2505 MULT18X18D=16 DP16KD=0
|
||||
N_SLOTS=4: LUT4=3953 CCU2C=500 TRELLIS_FF=4688 MULT18X18D=32 DP16KD=0
|
||||
CHECK: 0 problems on both configs (same 32 benign "multiple conflicting
|
||||
drivers for ...neural_processor.\gi" warnings per neural_processor
|
||||
instance already documented in EXP-0001 -- an `integer` for-loop
|
||||
index shared across two of neural_processor's own always blocks, not
|
||||
a real multi-driver conflict). DP16KD=0 on both is expected: M3's
|
||||
BRAM-backed buffers (activation/weight/result_buffer) are
|
||||
deliberately NOT instantiated inside dataflow_core yet (decisions.log
|
||||
DEC-0009). DSP scales exactly 8/slot (matches P_IN=8, consistent with
|
||||
every prior per-processor DSP measurement since M1/M2).
|
||||
|
||||
@@ -54,3 +54,14 @@ Fmax: 250.50 MHz -- PASS at 80MHz (real place&route measurement)
|
||||
no harness needed), real nextpnr-ecp5 --45k --package CABGA381
|
||||
--speed 8 --freq 80 --lpf-allow-unconstrained
|
||||
Fmax: 155.30 MHz -- PASS at 80MHz (real place&route measurement)
|
||||
|
||||
[2026-09-05] EXP-0008 -- dataflow_core (via harness_dataflow_core.v,
|
||||
see errors.log ERR-0005 for why a harness was needed), real
|
||||
nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80
|
||||
--lpf-allow-unconstrained
|
||||
N_SLOTS=2: Fmax = 165.15 MHz -- PASS at 80MHz (real place&route)
|
||||
N_SLOTS=4: Fmax = 133.19 MHz -- PASS at 80MHz (real place&route)
|
||||
Fmax drops as N_SLOTS grows (more concurrent memory_manager+
|
||||
neural_processor instances competing for the same routing fabric
|
||||
around the shared neural_director/dependency_manager hub) -- both
|
||||
configs still clear the 80MHz target with real margin.
|
||||
|
||||
@@ -0,0 +1,213 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
// ================================================================
|
||||
// FPGA-Neural V2 -- Dataflow Core (M7, docs/v2-description.md §17)
|
||||
//
|
||||
// First full integration: Dependency Manager (M6) -> Neural Director
|
||||
// (M5) -> N_SLOTS x (Memory Manager (M4) + Neural Processor (M1)).
|
||||
//
|
||||
// JOBS (node registration)
|
||||
// |
|
||||
// +-----------------+
|
||||
// | Dependency |
|
||||
// | Manager (M6) |
|
||||
// +--------+--------+
|
||||
// | ready_valid/ready (a node whose deps resolved)
|
||||
// +--------v--------+
|
||||
// | Neural Director |
|
||||
// | (M5) |
|
||||
// +--------+--------+
|
||||
// | slot_job_start/x_base/w_base/n_tiles/result_addr
|
||||
// +----------+----------+
|
||||
// v v v
|
||||
// Memory Memory Memory (one per slot, M4)
|
||||
// Manager Manager Manager
|
||||
// | | |
|
||||
// Neural Neural Neural (one per slot, M1)
|
||||
// Processor Processor Processor
|
||||
//
|
||||
// A slot's job_done feeds back to the Director (frees the slot) AND,
|
||||
// via the node_id the Director itself tracked for that slot
|
||||
// (slot_node_id), becomes a producer_done event fed to the
|
||||
// Dependency Manager -- closing the loop: a node's completion can now
|
||||
// wake up every OTHER node that depended on it, without any external
|
||||
// component gluing the two together.
|
||||
//
|
||||
// Scope (see hardware/v2/logs/decisions.log DEC-0009):
|
||||
// - activation_buffer.v/weight_buffer.v/result_buffer.v (M3) are NOT
|
||||
// instantiated inside dataflow_core yet -- they belong on the OTHER
|
||||
// side of the Memory Backend Interface (§15's own diagram: Memory
|
||||
// Manager -> Memory Backend Interface -> PSRAM Controller), and
|
||||
// each memory_manager instance already owns its own prefetch double
|
||||
// buffer (M4) for the fast path. Wiring the M3 buffers in as a
|
||||
// shared on-chip cache in front of PSRAM is real future work, not
|
||||
// done here (no measured need for it yet, §22/§30).
|
||||
// - each slot's byte-level Memory Backend Interface port is exposed
|
||||
// SEPARATELY (N_SLOTS independent ports) rather than arbitrated
|
||||
// down to one shared PSRAM master -- real PSRAM integration
|
||||
// (including whatever arbitration N_SLOTS>1 requires) is explicitly
|
||||
// M8's job, not this one's.
|
||||
// ================================================================
|
||||
|
||||
module dataflow_core #(
|
||||
parameter DATA_WIDTH = 8,
|
||||
parameter P_IN = 8,
|
||||
parameter ACC_WIDTH = 32,
|
||||
parameter ADDR_WIDTH = 23,
|
||||
parameter N_SLOTS = 4,
|
||||
parameter N_NODES = 16,
|
||||
parameter MAX_DEPS = 4,
|
||||
parameter QUEUE_DEPTH = 8
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
// ---- node registration (host / graph loader -> Dependency Manager) ----
|
||||
input wire reg_valid,
|
||||
output wire reg_ready,
|
||||
input wire [$clog2(N_NODES)-1:0] reg_node_id,
|
||||
input wire [$clog2(MAX_DEPS+1)-1:0] reg_required,
|
||||
input wire [MAX_DEPS*$clog2(N_NODES)-1:0] reg_producer_ids,
|
||||
input wire [ADDR_WIDTH-1:0] reg_x_base,
|
||||
input wire [ADDR_WIDTH-1:0] reg_w_base,
|
||||
input wire [15:0] reg_n_tiles,
|
||||
input wire [ADDR_WIDTH-1:0] reg_result_addr,
|
||||
|
||||
// ---- per-slot Memory Backend Interface (arrayed, one per slot --
|
||||
// see file header on why arbitration to one shared PSRAM port is
|
||||
// NOT done here) ----
|
||||
output wire [N_SLOTS-1:0] slot_mem_req,
|
||||
output wire [N_SLOTS-1:0] slot_mem_wr,
|
||||
output wire [ADDR_WIDTH*N_SLOTS-1:0] slot_mem_addr,
|
||||
output wire signed [8*N_SLOTS-1:0] slot_mem_wdata,
|
||||
input wire signed [8*N_SLOTS-1:0] slot_mem_rdata,
|
||||
input wire [N_SLOTS-1:0] slot_mem_ready
|
||||
);
|
||||
|
||||
localparam NODE_IDW = $clog2(N_NODES);
|
||||
|
||||
// ---- Dependency Manager (M6) ----
|
||||
wire dm_ready_valid;
|
||||
wire dm_ready_ready;
|
||||
wire [NODE_IDW-1:0] dm_ready_node_id;
|
||||
wire [ADDR_WIDTH-1:0] dm_ready_x_base, dm_ready_w_base, dm_ready_result_addr;
|
||||
wire [15:0] dm_ready_n_tiles;
|
||||
|
||||
wire dm_producer_done_valid;
|
||||
wire [NODE_IDW-1:0] dm_producer_done_node_id;
|
||||
|
||||
dependency_manager #(
|
||||
.N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS), .ADDR_WIDTH(ADDR_WIDTH)
|
||||
) u_dep_mgr (
|
||||
.clk(clk), .rst(rst),
|
||||
.reg_valid(reg_valid), .reg_ready(reg_ready), .reg_node_id(reg_node_id),
|
||||
.reg_required(reg_required), .reg_producer_ids(reg_producer_ids),
|
||||
.reg_x_base(reg_x_base), .reg_w_base(reg_w_base), .reg_n_tiles(reg_n_tiles),
|
||||
.reg_result_addr(reg_result_addr),
|
||||
.producer_done_valid(dm_producer_done_valid), .producer_done_node_id(dm_producer_done_node_id),
|
||||
.ready_valid(dm_ready_valid), .ready_ready(dm_ready_ready), .ready_node_id(dm_ready_node_id),
|
||||
.ready_x_base(dm_ready_x_base), .ready_w_base(dm_ready_w_base),
|
||||
.ready_n_tiles(dm_ready_n_tiles), .ready_result_addr(dm_ready_result_addr)
|
||||
);
|
||||
|
||||
// node_id is 16 bits on the Director/Memory Manager side (matches
|
||||
// neural_processor.v's own job_node_id width) but NODE_IDW bits on
|
||||
// the Dependency Manager side (sized to N_NODES) -- zero-extended
|
||||
// crossing the boundary, truncated coming back (safe as long as
|
||||
// N_NODES <= 65536, always true for any NODE_IDW <= 16).
|
||||
wire [15:0] dm_ready_node_id_ext = {{(16-NODE_IDW){1'b0}}, dm_ready_node_id};
|
||||
|
||||
// ---- Neural Director (M5) ----
|
||||
wire [N_SLOTS-1:0] dir_slot_job_start;
|
||||
wire [ADDR_WIDTH*N_SLOTS-1:0] dir_slot_x_base, dir_slot_w_base, dir_slot_result_addr;
|
||||
wire [16*N_SLOTS-1:0] dir_slot_n_tiles, dir_slot_node_id;
|
||||
wire [N_SLOTS-1:0] dir_slot_job_done;
|
||||
wire dir_job_out_done;
|
||||
wire [$clog2(N_SLOTS)-1:0] dir_job_out_slot;
|
||||
wire [3:0] dir_state;
|
||||
wire dir_error;
|
||||
|
||||
neural_director #(
|
||||
.ADDR_WIDTH(ADDR_WIDTH), .N_SLOTS(N_SLOTS), .QUEUE_DEPTH(QUEUE_DEPTH)
|
||||
) u_director (
|
||||
.clk(clk), .rst(rst),
|
||||
.job_in_valid(dm_ready_valid), .job_in_ready(dm_ready_ready),
|
||||
.job_in_x_base(dm_ready_x_base), .job_in_w_base(dm_ready_w_base),
|
||||
.job_in_n_tiles(dm_ready_n_tiles), .job_in_result_addr(dm_ready_result_addr),
|
||||
.job_in_node_id(dm_ready_node_id_ext),
|
||||
.slot_job_start(dir_slot_job_start), .slot_x_base(dir_slot_x_base), .slot_w_base(dir_slot_w_base),
|
||||
.slot_n_tiles(dir_slot_n_tiles), .slot_result_addr(dir_slot_result_addr),
|
||||
.slot_node_id(dir_slot_node_id), .slot_job_done(dir_slot_job_done),
|
||||
.job_out_done(dir_job_out_done), .job_out_slot(dir_job_out_slot),
|
||||
.dir_state(dir_state), .dir_error(dir_error)
|
||||
);
|
||||
|
||||
// job_out_slot indexes slot_node_id to recover which node just
|
||||
// completed -- this becomes the Dependency Manager's own
|
||||
// producer_done event, closing the wake-up loop.
|
||||
wire [15:0] completed_node_id_16 = dir_slot_node_id[dir_job_out_slot*16 +: 16];
|
||||
assign dm_producer_done_valid = dir_job_out_done;
|
||||
assign dm_producer_done_node_id = completed_node_id_16[NODE_IDW-1:0];
|
||||
|
||||
// ---- N_SLOTS x (Memory Manager (M4) + Neural Processor (M1)) ----
|
||||
genvar g;
|
||||
generate
|
||||
for (g = 0; g < N_SLOTS; g = g + 1) begin : GEN_SLOT
|
||||
|
||||
wire mm_operand_valid, mm_operand_ready;
|
||||
wire signed [DATA_WIDTH*P_IN-1:0] mm_input_data, mm_weight_data;
|
||||
wire mm_tile_last;
|
||||
wire mm_result_valid, mm_result_ready;
|
||||
wire signed [DATA_WIDTH-1:0] mm_result_data;
|
||||
|
||||
memory_manager #(
|
||||
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ADDR_WIDTH(ADDR_WIDTH)
|
||||
) u_mm (
|
||||
.clk(clk), .rst(rst),
|
||||
.job_start(dir_slot_job_start[g]),
|
||||
.x_base(dir_slot_x_base[g*ADDR_WIDTH +: ADDR_WIDTH]),
|
||||
.w_base(dir_slot_w_base[g*ADDR_WIDTH +: ADDR_WIDTH]),
|
||||
.n_tiles(dir_slot_n_tiles[g*16 +: 16]),
|
||||
.result_addr(dir_slot_result_addr[g*ADDR_WIDTH +: ADDR_WIDTH]),
|
||||
.job_done(dir_slot_job_done[g]),
|
||||
.operand_valid(mm_operand_valid), .operand_ready(mm_operand_ready),
|
||||
.input_data(mm_input_data), .weight_data(mm_weight_data), .tile_last(mm_tile_last),
|
||||
.result_valid(mm_result_valid), .result_ready(mm_result_ready), .result_data(mm_result_data),
|
||||
.mem_req(slot_mem_req[g]), .mem_wr(slot_mem_wr[g]),
|
||||
.mem_addr(slot_mem_addr[g*ADDR_WIDTH +: ADDR_WIDTH]),
|
||||
.mem_wdata(slot_mem_wdata[g*8 +: 8]),
|
||||
.mem_rdata(slot_mem_rdata[g*8 +: 8]), .mem_ready(slot_mem_ready[g])
|
||||
);
|
||||
|
||||
reg job_valid_np;
|
||||
wire job_ready_np;
|
||||
wire result_valid_np;
|
||||
wire signed [DATA_WIDTH-1:0] result_data_np;
|
||||
wire [3:0] np_state;
|
||||
wire np_error;
|
||||
|
||||
neural_processor #(
|
||||
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH)
|
||||
) u_np (
|
||||
.clk(clk), .rst(rst),
|
||||
.job_valid(job_valid_np), .job_ready(job_ready_np),
|
||||
.job_node_id(16'h0), .job_bias(8'sd0), .job_activation(2'd1),
|
||||
.operand_valid(mm_operand_valid), .operand_ready(mm_operand_ready),
|
||||
.input_data(mm_input_data), .weight_data(mm_weight_data), .tile_last(mm_tile_last),
|
||||
.result_valid(result_valid_np), .result_ready(mm_result_ready),
|
||||
.result_data(result_data_np), .result_node_id(),
|
||||
.np_state(np_state), .np_error(np_error)
|
||||
);
|
||||
assign mm_result_valid = result_valid_np;
|
||||
assign mm_result_data = result_data_np;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) job_valid_np <= 1'b0;
|
||||
else if (dir_slot_job_start[g]) job_valid_np <= 1'b1;
|
||||
else if (job_valid_np && job_ready_np) job_valid_np <= 1'b0;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -53,6 +53,14 @@ module neural_director #(
|
||||
output reg [ADDR_WIDTH*N_SLOTS-1:0] slot_w_base,
|
||||
output reg [16*N_SLOTS-1:0] slot_n_tiles,
|
||||
output reg [ADDR_WIDTH*N_SLOTS-1:0] slot_result_addr,
|
||||
// slot_node_id: which node_id is currently occupying each slot --
|
||||
// not needed by memory_manager itself (it has no notion of node
|
||||
// ids), but needed by a caller (dataflow_core.v, M7) that must
|
||||
// map a slot's job_done back to the node_id that just completed,
|
||||
// to notify the Dependency Manager (M6). Purely additive: existing
|
||||
// callers (hardware/v2/sim/tb_neural_director.v, M5) that don't
|
||||
// connect it are unaffected.
|
||||
output reg [16*N_SLOTS-1:0] slot_node_id,
|
||||
input wire [N_SLOTS-1:0] slot_job_done,
|
||||
|
||||
// ---- completion notification (§9 "rilevamento dei completamenti") ----
|
||||
@@ -133,6 +141,7 @@ module neural_director #(
|
||||
slot_w_base <= {(ADDR_WIDTH*N_SLOTS){1'b0}};
|
||||
slot_n_tiles <= {(16*N_SLOTS){1'b0}};
|
||||
slot_result_addr <= {(ADDR_WIDTH*N_SLOTS){1'b0}};
|
||||
slot_node_id <= {(16*N_SLOTS){1'b0}};
|
||||
job_out_done <= 1'b0;
|
||||
job_out_slot <= {$clog2(N_SLOTS){1'b0}};
|
||||
end else begin
|
||||
@@ -192,6 +201,7 @@ module neural_director #(
|
||||
slot_w_base[free_slot_idx*ADDR_WIDTH +: ADDR_WIDTH] <= q_w_base[q_head];
|
||||
slot_n_tiles[free_slot_idx*16 +: 16] <= q_n_tiles[q_head];
|
||||
slot_result_addr[free_slot_idx*ADDR_WIDTH +: ADDR_WIDTH] <= q_result_addr[q_head];
|
||||
slot_node_id[free_slot_idx*16 +: 16] <= q_node_id[q_head];
|
||||
slot_busy[free_slot_idx] <= 1'b1;
|
||||
q_head <= (q_head == QUEUE_DEPTH[Q_ADDR_WIDTH-1:0]-1'b1) ? {Q_ADDR_WIDTH{1'b0}} : q_head + 1'b1;
|
||||
dir_state <= DIR_SCAN_READY;
|
||||
|
||||
@@ -0,0 +1,236 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
// ============================================================
|
||||
// M7 testbench (docs/v2-description.md §17/§19/§20): dataflow_core.v
|
||||
// -- the FULL loop, end-to-end, for the first time: node registration
|
||||
// -> Dependency Manager -> Neural Director -> (Memory Manager +
|
||||
// Neural Processor) per slot -> completion -> wake-up of dependent
|
||||
// nodes -> repeat, with NO external component gluing any of these
|
||||
// stages together (all internal to dataflow_core.v).
|
||||
//
|
||||
// DAG (same shape as tb_dependency_manager.v's own §10-focused test,
|
||||
// now driven through the WHOLE system instead of dependency_manager
|
||||
// in isolation): node0 and node1 have no dependencies and run
|
||||
// concurrently on the 2 available slots; node2 depends on BOTH and
|
||||
// must not be dispatched until both have genuinely completed their
|
||||
// real neural_processor computation (not just been "marked done" --
|
||||
// its own result is checked too).
|
||||
//
|
||||
// node0 (x=2,w=3,8in -> acc=48) --+
|
||||
// +--> node2 (x=1,w=5,8in -> acc=40)
|
||||
// node1 (x=1,w=1,8in -> acc=8) --+
|
||||
//
|
||||
// Verified with Verilator (decisions.log DEC-0004). Each slot gets
|
||||
// its own independent behavioral memory (sim_byte_mem, same as
|
||||
// tb_neural_director.v/tb_memory_manager.v's own scope decisions --
|
||||
// DEC-0006/DEC-0007: shared-PSRAM arbitration across slots is
|
||||
// explicitly M8's job, not exercised here).
|
||||
// ============================================================
|
||||
|
||||
module sim_byte_mem #(
|
||||
parameter ADDR_WIDTH = 23,
|
||||
parameter DEPTH = 4096
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire req,
|
||||
input wire wr,
|
||||
input wire [ADDR_WIDTH-1:0] addr,
|
||||
input wire signed [7:0] wdata,
|
||||
output reg signed [7:0] rdata,
|
||||
output reg ready
|
||||
);
|
||||
reg signed [7:0] mem [0:DEPTH-1];
|
||||
reg [1:0] state;
|
||||
reg [ADDR_WIDTH-1:0] addr_reg;
|
||||
localparam ST_IDLE = 0, ST_WAIT = 1;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
state <= ST_IDLE; ready <= 1'b0; rdata <= 8'sd0;
|
||||
end else begin
|
||||
ready <= 1'b0;
|
||||
case (state)
|
||||
ST_IDLE: if (req) begin
|
||||
addr_reg <= addr;
|
||||
if (wr) mem[addr] <= wdata;
|
||||
state <= ST_WAIT;
|
||||
end
|
||||
ST_WAIT: begin
|
||||
rdata <= mem[addr_reg];
|
||||
ready <= 1'b1;
|
||||
state <= ST_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module tb;
|
||||
|
||||
localparam ADDR_WIDTH = 23;
|
||||
localparam DATA_WIDTH = 8;
|
||||
localparam P_IN = 8;
|
||||
localparam ACC_WIDTH = 32;
|
||||
localparam N_SLOTS = 2;
|
||||
localparam N_NODES = 8;
|
||||
localparam MAX_DEPS = 4;
|
||||
localparam QUEUE_DEPTH = 4;
|
||||
localparam NODE_IDW = $clog2(N_NODES);
|
||||
|
||||
reg clk, rst;
|
||||
initial begin clk = 0; forever #5 clk = ~clk; end
|
||||
|
||||
reg reg_valid;
|
||||
wire reg_ready;
|
||||
reg [NODE_IDW-1:0] reg_node_id;
|
||||
reg [$clog2(MAX_DEPS+1)-1:0] reg_required;
|
||||
reg [MAX_DEPS*NODE_IDW-1:0] reg_producer_ids;
|
||||
reg [ADDR_WIDTH-1:0] reg_x_base, reg_w_base, reg_result_addr;
|
||||
reg [15:0] reg_n_tiles;
|
||||
|
||||
wire [N_SLOTS-1:0] slot_mem_req, slot_mem_wr;
|
||||
wire [ADDR_WIDTH*N_SLOTS-1:0] slot_mem_addr;
|
||||
wire signed [8*N_SLOTS-1:0] slot_mem_wdata, slot_mem_rdata;
|
||||
wire [N_SLOTS-1:0] slot_mem_ready;
|
||||
|
||||
dataflow_core #(
|
||||
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
|
||||
.N_SLOTS(N_SLOTS), .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS), .QUEUE_DEPTH(QUEUE_DEPTH)
|
||||
) u_core (
|
||||
.clk(clk), .rst(rst),
|
||||
.reg_valid(reg_valid), .reg_ready(reg_ready), .reg_node_id(reg_node_id),
|
||||
.reg_required(reg_required), .reg_producer_ids(reg_producer_ids),
|
||||
.reg_x_base(reg_x_base), .reg_w_base(reg_w_base), .reg_n_tiles(reg_n_tiles),
|
||||
.reg_result_addr(reg_result_addr),
|
||||
.slot_mem_req(slot_mem_req), .slot_mem_wr(slot_mem_wr), .slot_mem_addr(slot_mem_addr),
|
||||
.slot_mem_wdata(slot_mem_wdata), .slot_mem_rdata(slot_mem_rdata), .slot_mem_ready(slot_mem_ready)
|
||||
);
|
||||
|
||||
genvar g;
|
||||
generate
|
||||
for (g = 0; g < N_SLOTS; g = g + 1) begin : GEN_MEM
|
||||
sim_byte_mem #(.ADDR_WIDTH(ADDR_WIDTH), .DEPTH(4096)) u_mem (
|
||||
.clk(clk), .rst(rst),
|
||||
.req(slot_mem_req[g]), .wr(slot_mem_wr[g]),
|
||||
.addr(slot_mem_addr[g*ADDR_WIDTH +: ADDR_WIDTH]),
|
||||
.wdata(slot_mem_wdata[g*8 +: 8]),
|
||||
.rdata(slot_mem_rdata[g*8 +: 8]), .ready(slot_mem_ready[g])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
task automatic poke(input integer slot, input [ADDR_WIDTH-1:0] addr, input [7:0] val);
|
||||
begin
|
||||
case (slot)
|
||||
0: tb.GEN_MEM[0].u_mem.mem[addr] = val;
|
||||
1: tb.GEN_MEM[1].u_mem.mem[addr] = val;
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
function automatic signed [7:0] peek(input integer slot, input [ADDR_WIDTH-1:0] addr);
|
||||
begin
|
||||
case (slot)
|
||||
0: peek = tb.GEN_MEM[0].u_mem.mem[addr];
|
||||
1: peek = tb.GEN_MEM[1].u_mem.mem[addr];
|
||||
default: peek = 8'sdx;
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
|
||||
task automatic register_node(
|
||||
input [NODE_IDW-1:0] nid,
|
||||
input [$clog2(MAX_DEPS+1)-1:0] required,
|
||||
input [NODE_IDW-1:0] p0, input [NODE_IDW-1:0] p1,
|
||||
input [ADDR_WIDTH-1:0] xb, input [ADDR_WIDTH-1:0] wb,
|
||||
input [15:0] nt, input [ADDR_WIDTH-1:0] resaddr
|
||||
);
|
||||
begin
|
||||
@(posedge clk);
|
||||
reg_node_id = nid;
|
||||
reg_required = required;
|
||||
reg_producer_ids = {NODE_IDW*MAX_DEPS{1'b0}};
|
||||
reg_producer_ids[0*NODE_IDW +: NODE_IDW] = p0;
|
||||
reg_producer_ids[1*NODE_IDW +: NODE_IDW] = p1;
|
||||
reg_x_base = xb; reg_w_base = wb; reg_n_tiles = nt; reg_result_addr = resaddr;
|
||||
reg_valid = 1'b1;
|
||||
while (!reg_ready) @(posedge clk);
|
||||
@(posedge clk);
|
||||
reg_valid = 1'b0;
|
||||
end
|
||||
endtask
|
||||
|
||||
integer errors, tests;
|
||||
integer i, wd;
|
||||
|
||||
initial begin
|
||||
errors = 0; tests = 0;
|
||||
rst = 1; reg_valid = 0; reg_node_id = 0; reg_required = 0; reg_producer_ids = 0;
|
||||
reg_x_base = 0; reg_w_base = 0; reg_n_tiles = 0; reg_result_addr = 0;
|
||||
repeat(4) @(posedge clk);
|
||||
rst = 0;
|
||||
@(posedge clk);
|
||||
|
||||
// Pre-load PSRAM-equivalent memory for both slots (a job could
|
||||
// land on either slot, first-free, so both need the data).
|
||||
for (i = 0; i < 8; i = i + 1) begin
|
||||
poke(0, 23'h10+i, 8'sd2); poke(0, 23'h20+i, 8'sd3); // node0: x=2,w=3
|
||||
poke(1, 23'h10+i, 8'sd2); poke(1, 23'h20+i, 8'sd3);
|
||||
poke(0, 23'h30+i, 8'sd1); poke(0, 23'h40+i, 8'sd1); // node1: x=1,w=1
|
||||
poke(1, 23'h30+i, 8'sd1); poke(1, 23'h40+i, 8'sd1);
|
||||
poke(0, 23'h50+i, 8'sd1); poke(0, 23'h60+i, 8'sd5); // node2: x=1,w=5
|
||||
poke(1, 23'h50+i, 8'sd1); poke(1, 23'h60+i, 8'sd5);
|
||||
end
|
||||
|
||||
// node0, node1: no dependencies. node2: depends on BOTH.
|
||||
register_node(0, 0, 0, 0, 23'h10, 23'h20, 16'd1, 23'h70);
|
||||
register_node(1, 0, 0, 0, 23'h30, 23'h40, 16'd1, 23'h71);
|
||||
register_node(2, 2, 0, 1, 23'h50, 23'h60, 16'd1, 23'h72);
|
||||
|
||||
// node2 must not complete before node0/node1 do -- checked by
|
||||
// polling: as soon as EITHER result byte at 0x70/0x71 is still
|
||||
// zero, 0x72 must also still be zero (node2 cannot have run).
|
||||
tests = tests + 1;
|
||||
wd = 0;
|
||||
while ((peek(0,23'h70)==0 && peek(1,23'h70)==0 ||
|
||||
peek(0,23'h71)==0 && peek(1,23'h71)==0) && wd < 3000) begin
|
||||
if ((peek(0,23'h72) !== 8'sd0) || (peek(1,23'h72) !== 8'sd0)) begin
|
||||
$display("FAIL: node2 completed before both node0 and node1 finished");
|
||||
errors = errors + 1;
|
||||
end
|
||||
@(posedge clk); wd = wd + 1;
|
||||
end
|
||||
$display("PASS: node2 did not complete before both its dependencies did (checked every cycle up to wd=%0d)", wd);
|
||||
|
||||
// Now wait for node2 itself to complete.
|
||||
wd = 0;
|
||||
while ((peek(0,23'h72)==0 && peek(1,23'h72)==0) && wd < 3000) begin @(posedge clk); wd = wd + 1; end
|
||||
repeat(5) @(posedge clk);
|
||||
|
||||
tests = tests + 3;
|
||||
if (peek(0,23'h70) !== 8'sd48 && peek(1,23'h70) !== 8'sd48) begin
|
||||
$display("FAIL node0: result=%0d/%0d expected 48 on one slot", peek(0,23'h70), peek(1,23'h70));
|
||||
errors = errors + 1;
|
||||
end else $display("PASS node0: result=48 (real neural_processor computation, via full dataflow_core)");
|
||||
|
||||
if (peek(0,23'h71) !== 8'sd8 && peek(1,23'h71) !== 8'sd8) begin
|
||||
$display("FAIL node1: result=%0d/%0d expected 8 on one slot", peek(0,23'h71), peek(1,23'h71));
|
||||
errors = errors + 1;
|
||||
end else $display("PASS node1: result=8 (real neural_processor computation, via full dataflow_core)");
|
||||
|
||||
if (peek(0,23'h72) !== 8'sd40 && peek(1,23'h72) !== 8'sd40) begin
|
||||
$display("FAIL node2: result=%0d/%0d expected 40 on one slot", peek(0,23'h72), peek(1,23'h72));
|
||||
errors = errors + 1;
|
||||
end else $display("PASS node2: result=40, dispatched only after BOTH node0 and node1 genuinely completed (full wake-up loop closed end-to-end)");
|
||||
|
||||
$display("========================================");
|
||||
if (errors == 0)
|
||||
$display("ALL %0d TESTS PASSED (dataflow_core, full M1-M6 integration end-to-end)", tests);
|
||||
else
|
||||
$display("FAILED: %0d/%0d test(s) had errors -- see messages above", errors, tests);
|
||||
$display("========================================");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,117 @@
|
||||
// ================================================================
|
||||
// SYNTHESIS-ONLY TIMING HARNESS -- NOT a functional deliverable.
|
||||
// Same rationale/pattern as harness_neural_processor_array.v and
|
||||
// harness_memory_manager.v (see their headers, and
|
||||
// hardware/v2/logs/errors.log ERR-0005): dataflow_core's own ports
|
||||
// (per-slot mem_addr/wdata/rdata buses, node registration fields)
|
||||
// exceed the LFE5U-45F's ~245 TRELLIS_IO budget as a bare top-level
|
||||
// module well before N_SLOTS=2 (measured: N_SLOTS=4 alone needs 280
|
||||
// bits just for the per-slot Memory Backend Interface arrays).
|
||||
//
|
||||
// dataflow_core.v additionally instantiates N_SLOTS REAL copies of
|
||||
// (memory_manager + neural_processor) via `generate` -- exactly the
|
||||
// same CSE risk already hit and fixed once in
|
||||
// harness_neural_processor_array.v (giving every instance IDENTICAL
|
||||
// LFSR data lets Yosys collapse all N_SLOTS copies down to 1). This
|
||||
// harness reuses that fix: each slot's mem_rdata/mem_ready input gets
|
||||
// its own distinct bit-rotated LFSR slice, and the checksum folds in
|
||||
// a real bit from EVERY slot's own outputs, not just slot 0's.
|
||||
//
|
||||
// Only clk/rst/seed/checksum are exposed as real top-level pins.
|
||||
// ================================================================
|
||||
|
||||
module harness_dataflow_core #(
|
||||
parameter DATA_WIDTH = 8,
|
||||
parameter P_IN = 8,
|
||||
parameter ACC_WIDTH = 32,
|
||||
parameter ADDR_WIDTH = 23,
|
||||
parameter N_SLOTS = 4,
|
||||
parameter N_NODES = 16,
|
||||
parameter MAX_DEPS = 4,
|
||||
parameter QUEUE_DEPTH = 8
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [7:0] seed,
|
||||
output wire [7:0] checksum
|
||||
);
|
||||
|
||||
localparam NODE_IDW = $clog2(N_NODES);
|
||||
|
||||
reg [31:0] lfsr;
|
||||
always @(posedge clk) begin
|
||||
if (rst) lfsr <= {24'h0, seed} | 32'h1;
|
||||
else lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]};
|
||||
end
|
||||
|
||||
// ---- node-registration side: a single port, no per-instance
|
||||
// CSE risk -- plain LFSR slices are enough. ----
|
||||
wire reg_valid = lfsr[0];
|
||||
wire [NODE_IDW-1:0] reg_node_id = lfsr[NODE_IDW-1:0];
|
||||
wire [$clog2(MAX_DEPS+1)-1:0] reg_required = lfsr[$clog2(MAX_DEPS+1)-1:0];
|
||||
wire [MAX_DEPS*NODE_IDW-1:0] reg_producer_ids;
|
||||
wire [ADDR_WIDTH-1:0] reg_x_base = lfsr[ADDR_WIDTH-1:0];
|
||||
wire [ADDR_WIDTH-1:0] reg_w_base = {lfsr[3:0], lfsr[ADDR_WIDTH-5:0]};
|
||||
wire [15:0] reg_n_tiles = lfsr[15:0];
|
||||
wire [ADDR_WIDTH-1:0] reg_result_addr = {lfsr[6:0], lfsr[ADDR_WIDTH-8:0]};
|
||||
genvar pgi;
|
||||
generate
|
||||
for (pgi = 0; pgi < MAX_DEPS; pgi = pgi + 1) begin : GEN_PID
|
||||
wire [31:0] prot = {lfsr[pgi:0], lfsr[31:pgi+1]};
|
||||
assign reg_producer_ids[pgi*NODE_IDW +: NODE_IDW] = prot[NODE_IDW-1:0];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// ---- per-slot Memory Backend Interface inputs: EACH slot needs
|
||||
// a DISTINCT rotated slice (see file header) so the N_SLOTS
|
||||
// memory_manager+neural_processor pairs stay N_SLOTS real,
|
||||
// distinguishable instances instead of collapsing to 1. ----
|
||||
wire signed [8*N_SLOTS-1:0] slot_mem_rdata;
|
||||
wire [N_SLOTS-1:0] slot_mem_ready;
|
||||
genvar sgi;
|
||||
generate
|
||||
for (sgi = 0; sgi < N_SLOTS; sgi = sgi + 1) begin : GEN_SLOT_DRIVE
|
||||
wire [31:0] srot = {lfsr[sgi:0], lfsr[31:sgi+1]};
|
||||
assign slot_mem_rdata[sgi*8 +: 8] = srot[7:0];
|
||||
assign slot_mem_ready[sgi] = srot[8];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire reg_ready;
|
||||
wire [N_SLOTS-1:0] slot_mem_req, slot_mem_wr;
|
||||
wire [ADDR_WIDTH*N_SLOTS-1:0] slot_mem_addr;
|
||||
wire signed [8*N_SLOTS-1:0] slot_mem_wdata;
|
||||
|
||||
dataflow_core #(
|
||||
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
|
||||
.N_SLOTS(N_SLOTS), .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS), .QUEUE_DEPTH(QUEUE_DEPTH)
|
||||
) dut (
|
||||
.clk(clk), .rst(rst),
|
||||
.reg_valid(reg_valid), .reg_ready(reg_ready), .reg_node_id(reg_node_id),
|
||||
.reg_required(reg_required), .reg_producer_ids(reg_producer_ids),
|
||||
.reg_x_base(reg_x_base), .reg_w_base(reg_w_base), .reg_n_tiles(reg_n_tiles),
|
||||
.reg_result_addr(reg_result_addr),
|
||||
.slot_mem_req(slot_mem_req), .slot_mem_wr(slot_mem_wr), .slot_mem_addr(slot_mem_addr),
|
||||
.slot_mem_wdata(slot_mem_wdata), .slot_mem_rdata(slot_mem_rdata), .slot_mem_ready(slot_mem_ready)
|
||||
);
|
||||
|
||||
// Fold in a real bit from EVERY slot's own outputs (not just slot
|
||||
// 0's) -- otherwise all slots but one have no observable output
|
||||
// path and Yosys correctly strips them as dead logic.
|
||||
wire [N_SLOTS-1:0] addr_lsb, wdata_lsb;
|
||||
generate
|
||||
for (sgi = 0; sgi < N_SLOTS; sgi = sgi + 1) begin : GEN_CHK_LANE
|
||||
assign addr_lsb[sgi] = slot_mem_addr[sgi*ADDR_WIDTH];
|
||||
assign wdata_lsb[sgi] = slot_mem_wdata[sgi*8];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
reg [7:0] chk;
|
||||
always @(posedge clk) begin
|
||||
if (rst) chk <= 8'h0;
|
||||
else chk <= chk ^ {7'h0, reg_ready} ^ slot_mem_req ^ slot_mem_wr
|
||||
^ addr_lsb ^ wdata_lsb;
|
||||
end
|
||||
assign checksum = chk;
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user