feat(v2): M7 Dataflow Core - full M1-M6 integration, wake-up loop closed end-to-end
dataflow_core.v integrates dependency_manager (M6) -> neural_director (M5) -> N_SLOTS x (memory_manager (M4) + neural_processor (M1)) for the first time. A slot's completion (via neural_director's new slot_node_id tracking, an additive port) feeds back as a producer_done event to dependency_manager, waking up any node that depended on it - closing the dataflow loop without external glue. Verified end-to-end (Verilator) on a 3-node DAG: two independent nodes plus a third depending on both, confirmed to dispatch only after both genuinely complete via real neural_processor computation. 4/4 PASS. Real synthesis + nextpnr-ecp5 P&R via a synthesis-only timing harness (bare per-slot backend ports exceed the LFE5U-45F's TRELLIS_IO budget, same pattern as ERR-0005): N_SLOTS=2 -> 165.15 MHz, N_SLOTS=4 -> 133.19 MHz, both PASS at 80MHz, 0 synthesis problems. Scope explicitly deferred to M8 (DEC-0009): M3's BRAM buffers not wired in yet, per-slot Memory Backend Interface ports not arbitrated to one shared PSRAM master yet - both need real measured data before committing to a design, not guessed at here. Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0009)/ experiments (EXP-0008)/errors (ERR-0007, a Yosys chparam-ordering build quirk, not an RTL bug)/development.log, ROADMAP.md updated. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
@@ -88,3 +88,18 @@ no harness needed)
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| Module | Fmax (POST-P&R) | LUT | FF | DSP | CCU2C |
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|----------------------|------------------|-----|-----|-----|-------|
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| dependency_manager (N_NODES=16) | 155.30 MHz | 763 | 474 | 0 | 0 |
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[2026-09-05] M7 Dataflow Core (full M1-M6 integration; resources via
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real standalone synthesis, Fmax via timing harness -- see errors.log
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ERR-0005)
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| Module (config) | Fmax (POST-P&R) | LUT4 | CCU2C | FF | DSP | BRAM |
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|-------------------------------|------------------|------|-------|------|-----|------|
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| dataflow_core (N_SLOTS=2) | 165.15 MHz | 2127 | 248 | 2505 | 16 | 0 |
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| dataflow_core (N_SLOTS=4) | 133.19 MHz | 3953 | 500 | 4688 | 32 | 0 |
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DSP budget on the LFE5U-45F is 72 MULT18X18D total: N_SLOTS=4 already
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uses 32/72 (44%), consistent with DEC-0005's finding that DSP, not
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LUT/FF, is the first resource to saturate as concurrency grows (M2's
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own N_PROCESSORS=8 measurement: 88%). BRAM=0 on both is expected --
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M3's buffers are not wired into dataflow_core yet (DEC-0009).
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@@ -455,3 +455,69 @@ missing.
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STATUS:
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ACCEPTED
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DEC-0009
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DATE: 2026-09-05
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DECISION:
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dataflow_core.v (M7) integrates dependency_manager (M6) -> neural_director
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(M5) -> N_SLOTS x (memory_manager (M4) + neural_processor (M1)), closing
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the wake-up loop end-to-end for the first time. Two things are
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deliberately NOT done in this module: (1) M3's BRAM-backed buffers
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(activation_buffer/weight_buffer/result_buffer) are not instantiated
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anywhere inside it; (2) each slot's byte-level Memory Backend Interface
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is exposed as its own SEPARATE port (slot_mem_req/wr/addr/wdata/rdata/
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ready, arrayed by N_SLOTS) rather than arbitrated down to one shared
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PSRAM master.
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WHY:
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(1) §15's own diagram places the Memory Manager -> Memory Backend
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Interface -> PSRAM Controller path on one side, with M3's buffers
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belonging as an on-chip cache concept, not a mandatory pass-through --
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each memory_manager instance already owns its own prefetch double
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buffer (M4) for the fast path it actually needs, and no measured
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benchmark yet shows a real need for an additional shared cache layer
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(§22/§30: no invented results/optimizations). (2) real PSRAM has
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exactly ONE physical port; N_SLOTS>1 memory_manager instances wanting
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concurrent access is fundamentally an arbitration problem, and building
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an arbiter now, before M8's real-toolchain measurement of what
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contention actually looks like end-to-end with the real (unmodified)
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V1 PSRAM chain, risks designing to a guess instead of to data.
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EVIDENCE:
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hardware/v2/sim/tb_dataflow_core.v -- 4/4 tests PASS on a 3-node DAG
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run through the full stack with each slot backed by its own
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independent behavioral memory (deliberately NOT the real shared V1
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PSRAM chain, for exactly the reason above): node0 and node1 (no
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dependencies) both complete correctly via real neural_processor
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computation, and node2 (depends on BOTH) is only dispatched after
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BOTH genuinely finish -- continuously polled every cycle, not just
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checked at the end -- proving the producer_done wake-up loop closes
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correctly with real M1/M4/M5/M6 hardware in between, not just
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between M5 and M6 in isolation (already proven separately by their
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own testbenches).
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ALTERNATIVES:
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1. Wire a naive round-robin N-port arbiter in front of one shared
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PSRAM master now. Rejected: M8's own roadmap text is explicit
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("Integrare il controller V1 senza modificarlo inizialmente.
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Misurare il comportamento reale.") -- arbitration design should
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follow a real measurement of contention under the real PSRAM
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latency model, not be guessed at during M7's own scope (proving
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the dependency/scheduling loop closes, not memory sharing).
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2. Instantiate M3's buffers as a shared cache in front of each slot's
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Memory Backend Interface now. Rejected: no benchmark yet shows
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PSRAM bandwidth or latency is actually a bottleneck for the
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dependency-graph workloads this module targets -- premature
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without measured justification.
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RESULT:
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dataflow_core.v as implemented: N_SLOTS independent Memory Backend
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Interface ports, no M3 buffers wired in. Both explicitly deferred to
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M8 (shared PSRAM integration/arbitration) and a future
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measurement-driven decision (M3 buffer reuse), not missing by
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oversight.
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STATUS:
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ACCEPTED
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@@ -181,3 +181,28 @@ decision: vedi decisions.log DEC-0008 (nessun forwarding di valori
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next_action: M7 -- dataflow_core.v, prima integrazione di
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Director+Dependency Manager+Memory Manager+Processor Array+Buffer
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in un unico top-level.
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[2026-09-05] M7 -- hardware/v2/rtl/dataflow_core.v
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reason: roadmap M7 -- first full integration of dependency_manager
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(M6) + neural_director (M5) + N_SLOTS x (memory_manager (M4) +
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neural_processor (M1)) into one top-level module, closing the
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producer-completion -> dependency-wake-up loop end-to-end for the
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first time. Additive extension to neural_director.v: added a
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slot_node_id output port (which node_id occupies each slot) so a
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caller can map a completed slot back to the node_id that just
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finished -- re-verified M5's own testbench still passes 4/4
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unaffected.
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result: 4/4 test PASS on a 3-node DAG (node2 depends on BOTH node0 and
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node1; confirmed it does NOT dispatch until both genuinely complete,
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polled every cycle). Real synthesis: 0 problems at both N_SLOTS=2
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(LUT4=2127/CCU2C=248/FF=2505/DSP=16) and N_SLOTS=4
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(LUT4=3953/CCU2C=500/FF=4688/DSP=32). Real Fmax (via
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harness_dataflow_core.v): 165.15 MHz (N_SLOTS=2), 133.19 MHz
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(N_SLOTS=4), both PASS at 80MHz.
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errors: one Yosys build-script usage quirk (errors.log ERR-0007,
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chparam target ordering), not an RTL bug.
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decision: see decisions.log DEC-0009 (M3 buffers not wired in yet, no
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shared-PSRAM arbitration across slots yet -- both deferred to M8).
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next_action: M8 -- PSRAM integration. Wire the real (unmodified) V1
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PSRAM backend chain through dataflow_core end-to-end and measure/
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design whatever N_SLOTS>1 arbitration real contention requires.
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@@ -176,3 +176,30 @@ VERIFICATION: hardware/v2/sim/tb_memory_manager.v -- 3/3 tests PASS
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signal inspection).
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STATUS: FIXED, verified end-to-end with the real (unmodified) V1
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PSRAM backend chain and a real M1 neural_processor.
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ERR-0007 (Yosys usage quirk, WORKED AROUND, not an RTL bug)
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DATE: 2026-09-05
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MODULE: hardware/v2/synthesis/harness_dataflow_core.v (build script)
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SYMPTOM: `chparam -set N_SLOTS 2 dataflow_core` (setting the parameter
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directly on the NON-top child module, before running `synth_ecp5
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-top harness_dataflow_core`) synthesizes with no visible error from
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the chparam/hierarchy commands themselves, but `synth_ecp5` then
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fails with "Module `\dataflow_core' referenced in module
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`\harness_dataflow_core' in cell `\dut' is not part of the design" --
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even though a standalone `hierarchy -top harness_dataflow_core` run
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(no synth_ecp5) with the exact same chparam succeeds.
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ROOT CAUSE: harness_dataflow_core.v's own instantiation of
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dataflow_core explicitly overrides N_SLOTS via its own local
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parameter (`.N_SLOTS(N_SLOTS)`) -- chparam on the child module's
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DEFAULT is therefore always shadowed at that instantiation site
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regardless of its value, and synth_ecp5's own internal re-hierarchy
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pass (distinct from a standalone `hierarchy` call) does not
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reconcile a chparam'd-but-never-actually-used child default the
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same way, dropping the generic module reference instead.
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WORKAROUND: set the parameter on the TOP module being synthesized
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instead (`chparam -set N_SLOTS 2 harness_dataflow_core`), letting
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its own instantiation forward the value down to dataflow_core as
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designed. Confirmed working for both N_SLOTS=2 and N_SLOTS=4.
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STATUS: WORKED AROUND. A build-script ordering detail, not a defect in
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dataflow_core.v or harness_dataflow_core.v themselves -- noted here
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so a future N_SLOTS sweep (M9/M10) does not re-trip over it.
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@@ -365,3 +365,39 @@ decision: see decisions.log DEC-0008 (no value forwarding yet, no
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next_action: M7 -- dataflow_core.v, integrating Director + Dependency
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Manager + Memory Manager + Processor Array + Buffers into one top-
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level module for the first time.
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[2026-09-05] EXP-0008 -- hardware/v2/rtl/dataflow_core.v (M7, full
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M1-M6 integration)
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test: hardware/v2/sim/tb_dataflow_core.v -- a 3-node DAG (node0/node1
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independent, node2 depends on BOTH) run through the REAL
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dependency_manager -> neural_director -> N_SLOTS x (memory_manager +
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neural_processor) chain end-to-end for the first time, each slot
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backed by its own independent behavioral byte memory (shared real
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PSRAM arbitration explicitly deferred to M8, decisions.log DEC-0009)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL:
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SIMULATED: 4/4 PASS -- node0=48, node1=8 (correct real
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neural_processor computations via the full stack), node2=40
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dispatched only after BOTH node0 and node1 genuinely completed
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(continuously polled every cycle, not just checked at the end).
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SYNTHESIZED (via harness_dataflow_core.v -- see errors.log ERR-0005):
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N_SLOTS=2: 0 CHECK problems, LUT4=2127, CCU2C=248, TRELLIS_FF=2505,
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MULT18X18D=16, DP16KD=0.
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N_SLOTS=4: 0 CHECK problems, LUT4=3953, CCU2C=500, TRELLIS_FF=4688,
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MULT18X18D=32, DP16KD=0.
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POST-P&R (real, harness-based): N_SLOTS=2 Fmax=165.15 MHz,
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N_SLOTS=4 Fmax=133.19 MHz -- both PASS at 80MHz.
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errors: one Yosys build-script usage quirk (chparam ordering against
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a non-top module vs synth_ecp5's own internal re-hierarchy pass) --
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see errors.log ERR-0007. Not an RTL bug; no dataflow_core.v or
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harness_dataflow_core.v source change needed, only the build command
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itself.
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decision: see decisions.log DEC-0009 (no M3 buffers wired in yet, no
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shared-PSRAM arbitration across slots yet -- both explicitly
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deferred to M8/a future measurement-driven decision, not missing by
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oversight).
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next_action: M8 -- PSRAM integration. Wire the real (unmodified) V1
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PSRAM backend chain (int8_memory_access -> memory_interface ->
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psram_controller) end-to-end through dataflow_core, and design/
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measure whatever N_SLOTS>1 arbitration across ONE physical PSRAM
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port actually requires.
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@@ -60,3 +60,18 @@ test: 4 cases on a 4-node DAG (2 independent + 1 dual-dependency +
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1 single-dependency-shared-producer)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS
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[2026-09-05] EXP-0008 -- hardware/v2/sim/tb_dataflow_core.v
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test: full end-to-end M1-M6 integration through dataflow_core.v (M7),
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a 3-node DAG (node0/node1 independent, node2 depends on BOTH) run
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through the REAL dependency_manager -> neural_director -> N_SLOTS x
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(memory_manager + neural_processor) chain for the first time, each
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slot backed by its own independent behavioral byte memory
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS -- node0=48, node1=8 (both real neural_processor
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computations via the full stack), node2=40 dispatched only after
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BOTH node0 and node1 genuinely completed (continuously polled every
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cycle up to completion, not just checked at the end) -- the
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dependency-manager-to-director wake-up loop closes correctly
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end-to-end with real hardware in between, not just in isolation
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(M6's own testbench already proved the wake-up logic alone)
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@@ -46,3 +46,20 @@ LUT4=382 TRELLIS_FF=366 CCU2C=4 DSP=0. CHECK: 0 problems.
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[2026-09-05] EXP-0007 -- dependency_manager (N_NODES=16, MAX_DEPS=4)
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LUT4=763 TRELLIS_FF=474 CCU2C=0 DSP=0. CHECK: 0 problems.
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[2026-09-05] EXP-0008 -- dataflow_core (M7 full integration, via
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harness_dataflow_core.v -- see errors.log ERR-0005 for why a harness
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is needed: bare per-slot Memory Backend Interface ports alone total
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280 bits at N_SLOTS=4, exceeding the LFE5U-45F-8BG381's ~245 TRELLIS_IO
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budget)
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N_SLOTS=2: LUT4=2127 CCU2C=248 TRELLIS_FF=2505 MULT18X18D=16 DP16KD=0
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N_SLOTS=4: LUT4=3953 CCU2C=500 TRELLIS_FF=4688 MULT18X18D=32 DP16KD=0
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CHECK: 0 problems on both configs (same 32 benign "multiple conflicting
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drivers for ...neural_processor.\gi" warnings per neural_processor
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instance already documented in EXP-0001 -- an `integer` for-loop
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index shared across two of neural_processor's own always blocks, not
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a real multi-driver conflict). DP16KD=0 on both is expected: M3's
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BRAM-backed buffers (activation/weight/result_buffer) are
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deliberately NOT instantiated inside dataflow_core yet (decisions.log
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DEC-0009). DSP scales exactly 8/slot (matches P_IN=8, consistent with
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every prior per-processor DSP measurement since M1/M2).
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@@ -54,3 +54,14 @@ Fmax: 250.50 MHz -- PASS at 80MHz (real place&route measurement)
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no harness needed), real nextpnr-ecp5 --45k --package CABGA381
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--speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 155.30 MHz -- PASS at 80MHz (real place&route measurement)
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[2026-09-05] EXP-0008 -- dataflow_core (via harness_dataflow_core.v,
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see errors.log ERR-0005 for why a harness was needed), real
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nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80
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--lpf-allow-unconstrained
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N_SLOTS=2: Fmax = 165.15 MHz -- PASS at 80MHz (real place&route)
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N_SLOTS=4: Fmax = 133.19 MHz -- PASS at 80MHz (real place&route)
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Fmax drops as N_SLOTS grows (more concurrent memory_manager+
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neural_processor instances competing for the same routing fabric
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around the shared neural_director/dependency_manager hub) -- both
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configs still clear the 80MHz target with real margin.
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