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feat(v2): M3 activation/weight/result buffers, real BRAM mapping

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Implements M3: three parametric dual-port buffers for the §12
data-plane (Input/Weight/Result), reusing the proven BRAM-inference
idiom from the frozen hardware/v1/rtl/act_buffer.v (synchronous write,
synchronous REGISTERED read, no reset on the read register -- keeps
Yosys off the LUT-RAM path).

Verified with Verilator: 10/10 tests pass (write-then-read
correctness, extreme INT8 round-tripping, weight_buffer's full 64-bit
tile width round-tripping, undisturbed re-reads).

Real synthesis at two depths per module (6 configs total): 0 CHECK
problems, every configuration correctly infers DP16KD (never
LUT-RAM). Non-obvious real finding: weight_buffer's BRAM cost is
driven by its P_IN*DATA_WIDTH tile width, not its DEPTH -- an 8x depth
reduction (512->64) left DP16KD usage unchanged at 2, while
activation_buffer/result_buffer (byte-wide) scale as naively expected
(2->1). All default-depth configs PASS at 80MHz with large margin
(287-367 MHz) via real nextpnr-ecp5 place&route.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 14:19:11 +02:00
co-authored by Claude Sonnet 5
parent 3026dcd997
commit 5f0d7f101c
29 changed files with 178330 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v2/docs/ROADMAP.md
+4 -2
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@@ -18,8 +18,10 @@ reali, non solo scritto).
Fmax sempre PASS a 80MHz (159.11→134.70 MHz). Scoperta: il DSP
(MULT18X18D), non LUT/FF, satura per primo (88% a N=8) — vedi
`logs/decisions.log` DEC-0005.
- [ ] **M3 — Buffers** (`activation_buffer.v`, `weight_buffer.v`,
`result_buffer.v`).
- [x] **M3 — Buffers** (`activation_buffer.v`, `weight_buffer.v`,
`result_buffer.v`). Tutti inferiscono DP16KD reale (10/10 test,
6/6 config sintetizzate 0 problemi). Scoperta: il costo BRAM di
weight_buffer e' guidato da P_IN (larghezza), non da DEPTH.
- [ ] **M4 — Memory Manager** (`memory_manager.v`, `prefetch_engine.v`),
backend PSRAM V1 riusato senza modifiche.
- [ ] **M5 — Neural Director** (`neural_director.v`), scheduling first-free.
hardware/v2/logs/benchmark.log
+19
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@@ -40,3 +40,22 @@ until M9): N_PROCESSORS * P_IN MACs/cycle when all processors are
simultaneously streaming tiles (8, 16, 32, 64 for N=1/2/4/8 -- verified
achievable in principle by EXP-0003's concurrent/staggered simulation,
not yet measured as a sustained throughput number).
[2026-09-05] M3 buffers -- BRAM cost vs DEPTH (real Yosys synth_ecp5)
| Module | DEPTH | DP16KD | LUT4 | FF |
|--------------------|-------|--------|------|-----|
| activation_buffer | 4096 | 2 | 37 | 30 |
| activation_buffer | 256 | 1 | 21 | 26 |
| weight_buffer | 512 | 2 | 88 | 139 |
| weight_buffer | 64 | 2 | 73 | 136 |
| result_buffer | 4096 | 2 | 37 | 30 |
| result_buffer | 256 | 1 | 21 | 26 |
weight_buffer's DP16KD count is flat across an 8x depth reduction --
its 64-bit TILE_WIDTH (P_IN=8 * DATA_WIDTH=8), not DEPTH, determines
BRAM count for this module. activation_buffer/result_buffer (byte-
wide) scale as expected with depth. Confirms §14's warning literally:
"non assumere che buffer piu' grandi siano automaticamente migliori"
-- here, smaller was not cheaper either, because depth was the wrong
lever for this specific buffer's cost.
hardware/v2/logs/development.log
+22
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@@ -88,3 +88,25 @@ errors: ERR-0005 (artefatto di sintesi da pin-count, non un bug RTL --
decision: vedi decisions.log DEC-0005.
next_action: M3 -- activation_buffer.v / weight_buffer.v /
result_buffer.v (profondita' parametrica, valutare BRAM mapping).
[2026-09-05T15:15:00Z] commit=3026dcd session=v2-M3-buffers
module: hardware/v2/rtl/activation_buffer.v, weight_buffer.v,
result_buffer.v
action: implementato M3 -- tre buffer paramentrici (profondita'
parametrica) che inferiscono DP16KD reale, riusando l'idioma gia'
validato in hardware/v1/rtl/act_buffer.v (porta A scrittura sync,
porta B lettura sync REGISTRATA, nessun reset sulla porta di lettura
per restare fuori dal percorso LUT-RAM).
reason: roadmap M3.
result: 10/10 test PASS (Verilator). Sintesi reale a 2 profondita'
ciascuno: 0 problemi CHECK, DP16KD reale confermato in tutte le 6
configurazioni (mai LUT-RAM). Scoperta reale non assunta: il costo
BRAM di weight_buffer e' determinato dalla LARGHEZZA (P_IN*DATA_
WIDTH=64 bit), non dalla profondita' -- 512->64 di profondita' non
ha ridotto il conteggio DP16KD (resta 2). Place&route reale sui
default: tutti PASS a 80MHz con ampio margine (287-367 MHz).
errors: nessuno.
decision: vedi benchmark.log -- il dimensionamento di weight_buffer
andra' guidato da P_IN, non solo da DEPTH, quando si arrivera' a
M4/M9.
next_action: M4 -- memory_manager.v + prefetch_engine.v.
hardware/v2/logs/experiments.log
+59
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@@ -159,3 +159,62 @@ decision: see decisions.log DEC-0005 (DSP is the binding constraint,
be explored going forward).
next_action: M3 -- activation_buffer.v / weight_buffer.v /
result_buffer.v.
EXP-0004
timestamp: 2026-09-05T15:15:00Z
git_commit: 3026dcd (+ uncommitted M3 work)
session: v2-M3-buffers
module: hardware/v2/rtl/activation_buffer.v, weight_buffer.v,
result_buffer.v
configuration: activation_buffer/result_buffer DEPTH in {4096, 256};
weight_buffer DEPTH (in tiles) in {512, 64}, P_IN=8, DATA_WIDTH=8
(TILE_WIDTH=64 bits)
action: M3 -- three parametric dual-port BRAM-inferring buffers
(Input/Weight/Result of the §12 data-plane diagram), reusing the
proven inference idiom from hardware/v1/rtl/act_buffer.v (sync
write, sync REGISTERED read, no reset on the read register).
command (sim, Verilator): verilator --binary --timing -j 0 -Wno-fatal
--top-module tb -o /tmp/vtb_buffers hardware/v2/rtl/
activation_buffer.v hardware/v2/rtl/weight_buffer.v
hardware/v2/rtl/result_buffer.v hardware/v2/sim/tb_buffers.v &&
/tmp/vtb_buffers
command (synth): yosys -p "read_verilog <file>; chparam -set DEPTH
<N> <module>; synth_ecp5 -json .../top.json -top <module>" for each
of the 6 (module, depth) combinations.
command (timing): nextpnr-ecp5 --45k --package CABGA381 --speed 8
--freq 80 --lpf-allow-unconstrained, default-depth configs only.
result:
SIMULATED: 10/10 tests PASS -- write-then-read correctness incl.
extreme INT8 (-128/127) round-tripping exactly, back-to-back
writes to different addresses not disturbing earlier entries, and
weight_buffer's full 64-bit TILE_WIDTH round-tripping (not just
one lane).
SYNTHESIZED (real BRAM mapping, not assumed):
activation_buffer DEPTH=4096: 2 DP16KD, 37 LUT4, 30 FF
activation_buffer DEPTH=256: 1 DP16KD, 21 LUT4, 26 FF
weight_buffer DEPTH=512: 2 DP16KD, 88 LUT4, 139 FF
weight_buffer DEPTH=64: 2 DP16KD, 73 LUT4, 136 FF
result_buffer DEPTH=4096: 2 DP16KD, 37 LUT4, 30 FF
result_buffer DEPTH=256: 1 DP16KD, 21 LUT4, 26 FF
0 CHECK problems in all 6 configurations -- every one correctly
inferred DP16KD block RAM, none fell back to LUT-RAM.
REAL, NON-OBVIOUS FINDING (§14: "non assumere che buffer piu' grandi
siano automaticamente migliori"): shrinking weight_buffer's DEPTH
8x (512->64) did NOT reduce DP16KD usage at all (2->2) -- its
64-bit TILE_WIDTH (P_IN*DATA_WIDTH), not its depth, is what forces
2 physical block RAMs (a single DP16KD's usable port width in the
density this needs is narrower than 64 bits). Depth-only buffer
sizing decisions are the wrong lever for THIS buffer; width
(P_IN) is. activation_buffer/result_buffer, being byte-wide, DO
show the expected depth-proportional DP16KD count (2 -> 1).
POST-P&R (default-depth configs): all PASS at 80MHz with large
margin (287-367 MHz range, real place&route) -- these buffers are
not a timing concern in isolation.
errors: none.
decision: keep DEPTH parametric as specified, but document (this
entry + benchmark.log) that weight_buffer's real BRAM cost is driven
by P_IN (its width), not DEPTH -- relevant when M4/M9 size these
buffers against a real workload.
next_action: M4 -- memory_manager.v + prefetch_engine.v (wires these
three buffers + the array together, PSRAM backend reused unmodified
from V1 per §15).
hardware/v2/logs/simulation.log
+8
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@@ -28,3 +28,11 @@ concurrency: confirmed genuine -- in the staggered test, the
later-launched, shorter job (processor 1) completes BEFORE the
earlier-launched, longer job (processor 0), proving independent
progress rather than serialization.
[2026-09-05] EXP-0004 -- hardware/v2/sim/tb_buffers.v
test: 10 cases across activation_buffer/weight_buffer/result_buffer
vectors: extreme INT8 (-128, 127, -100, 100), regular values, full
64-bit tile round-trip (weight_buffer), re-reads confirming earlier
writes undisturbed
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 10/10 PASS
hardware/v2/logs/synthesis.log
+9
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@@ -27,3 +27,12 @@ CHECK: 0 problems in all 4 configurations. Perfectly linear scaling in
flawed harness attempt fed identical data to every processor/lane
and Yosys silently deduplicated down to 1x regardless of N -- caught
by checking for exactly this linearity before trusting the numbers).
[2026-09-05] EXP-0004 -- activation_buffer/weight_buffer/result_buffer,
2 depths each
activation_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1)
weight_buffer D=512: LUT=88 FF=139 DP16KD=2 (D=64: LUT=73 FF=136 DP16KD=2)
result_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1)
CHECK: 0 problems, all 6 configs correctly infer DP16KD (no LUT-RAM
fallback). weight_buffer's DP16KD count does NOT drop with depth
(width-bound, not depth-bound -- see decisions.log / benchmark.log).
hardware/v2/logs/timing.log
+7
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@@ -31,3 +31,10 @@ TRELLIS_IO stays at 18/245 (7%) throughout (harness has only
clk/rst/seed/checksum as real pins, by design -- see ERR-0005).
See decisions.log DEC-0005: DSP, not Fmax or LUT/FF, is the resource
that will first prevent scaling N_PROCESSORS further at P_IN=8.
[2026-09-05] EXP-0004 -- default-depth buffer configs, real nextpnr-ecp5
activation_buffer (D=4096): Fmax=325.20 MHz PASS
weight_buffer (D=512): Fmax=339.67 MHz PASS
result_buffer (D=4096): Fmax=325.20 MHz PASS
All far above the 80MHz target -- buffers are not a timing concern in
isolation at these depths.
hardware/v2/rtl/activation_buffer.v
+47
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@@ -0,0 +1,47 @@
`timescale 1ns/1ps
// ================================================================
// FPGA-Neural V2 -- Activation Buffer (M3, docs/v2-description.md §14)
//
// Holds the "Input Buffer" of the §12 data-plane diagram: one INT8
// activation slot per signal id, read by the Neural Processor Array
// (via the Memory Manager, M4) and written by producers (external
// input load, or a Neural Processor's own result forwarded here for
// a downstream consumer).
//
// Same proven BRAM-inference idiom as hardware/v1/rtl/act_buffer.v
// (frozen, unmodified reference): dual-port, byte-addressed, Port A
// synchronous write, Port B synchronous REGISTERED read (1-cycle
// latency, no `rst` on the read register -- a synchronous reset on an
// indexed array forces Yosys onto LUT-RAM instead of a Lattice
// DP16KD block RAM). DEPTH is fully parametric (§14: "la profondita'
// deve essere parametrica").
// ================================================================
module activation_buffer #(
parameter DEPTH = 4096,
parameter DATA_WIDTH = 8,
localparam ADDR_WIDTH = $clog2(DEPTH)
)(
input wire clk,
input wire wr_en,
input wire [ADDR_WIDTH-1:0] wr_addr,
input wire signed [DATA_WIDTH-1:0] wr_data,
input wire [ADDR_WIDTH-1:0] rd_addr,
output reg signed [DATA_WIDTH-1:0] rd_data
);
reg signed [DATA_WIDTH-1:0] mem [0:DEPTH-1];
always @(posedge clk) begin
if (wr_en)
mem[wr_addr] <= wr_data;
end
always @(posedge clk) begin
rd_data <= mem[rd_addr];
end
endmodule
hardware/v2/rtl/result_buffer.v
+47
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@@ -0,0 +1,47 @@
`timescale 1ns/1ps
// ================================================================
// FPGA-Neural V2 -- Result Buffer (M3, docs/v2-description.md §14)
//
// Holds the "Result Buffer" of the §12 data-plane diagram: one INT8
// slot per node id, written by a Neural Processor's result_data (at
// its result_node_id address) once its job's tile_last has drained
// through the pipeline (M1), and read by whichever consumer needs it
// next -- a downstream layer's Weight/Activation Buffer producer, the
// Dependency Manager (M6, dependency resolution), or the host
// (READ_RAM-equivalent path, M4/M8).
//
// Same BRAM-inference idiom as activation_buffer.v (dual-port, Port A
// sync write, Port B sync REGISTERED read, no reset on the read
// register). DEPTH is fully parametric. Deliberately NOT tracking
// "has this id been written yet" here -- that bookkeeping belongs to
// the Dependency Manager (M6), not this buffer.
// ================================================================
module result_buffer #(
parameter DEPTH = 4096,
parameter DATA_WIDTH = 8,
localparam ADDR_WIDTH = $clog2(DEPTH)
)(
input wire clk,
input wire wr_en,
input wire [ADDR_WIDTH-1:0] wr_addr,
input wire signed [DATA_WIDTH-1:0] wr_data,
input wire [ADDR_WIDTH-1:0] rd_addr,
output reg signed [DATA_WIDTH-1:0] rd_data
);
reg signed [DATA_WIDTH-1:0] mem [0:DEPTH-1];
always @(posedge clk) begin
if (wr_en)
mem[wr_addr] <= wr_data;
end
always @(posedge clk) begin
rd_data <= mem[rd_addr];
end
endmodule
hardware/v2/rtl/weight_buffer.v
+48
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@@ -0,0 +1,48 @@
`timescale 1ns/1ps
// ================================================================
// FPGA-Neural V2 -- Weight Buffer (M3, docs/v2-description.md §14)
//
// Holds the "Weight Buffer" of the §12 data-plane diagram. Unlike
// activation_buffer (one INT8 per signal id), each address here holds
// one WHOLE TILE of P_IN weights -- exactly the width a Neural
// Processor (M1) consumes per cycle on its weight_data port, so the
// Memory Manager (M4) can feed a processor one tile/cycle without any
// additional muxing/serialization at this buffer's boundary (§7:
// avoid big dynamic muxes).
//
// Same BRAM-inference idiom as activation_buffer.v /
// hardware/v1/rtl/act_buffer.v (dual-port, Port A sync write, Port B
// sync REGISTERED read, no reset on the read register). DEPTH (in
// TILES, not individual weights) is fully parametric.
// ================================================================
module weight_buffer #(
parameter DEPTH = 512, // depth in TILES (each DEPTH*P_IN*DATA_WIDTH/8 bytes)
parameter DATA_WIDTH = 8,
parameter P_IN = 8,
localparam ADDR_WIDTH = $clog2(DEPTH),
localparam TILE_WIDTH = DATA_WIDTH * P_IN
)(
input wire clk,
input wire wr_en,
input wire [ADDR_WIDTH-1:0] wr_addr,
input wire signed [TILE_WIDTH-1:0] wr_data,
input wire [ADDR_WIDTH-1:0] rd_addr,
output reg signed [TILE_WIDTH-1:0] rd_data
);
reg signed [TILE_WIDTH-1:0] mem [0:DEPTH-1];
always @(posedge clk) begin
if (wr_en)
mem[wr_addr] <= wr_data;
end
always @(posedge clk) begin
rd_data <= mem[rd_addr];
end
endmodule
hardware/v2/sim/tb_buffers.v
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@@ -0,0 +1,169 @@
`timescale 1ns/1ps
// ============================================================
// M3 testbench (docs/v2-description.md §14/§20): activation_buffer.v,
// weight_buffer.v, result_buffer.v. Verified with Verilator (see
// hardware/v2/logs/decisions.log DEC-0004).
//
// Coverage: write-then-read correctness (incl. the 1-cycle registered
// read latency all three share with hardware/v1/rtl/act_buffer.v),
// back-to-back writes to different addresses without corrupting
// earlier entries, and extreme INT8 values (-128, 127) round-tripping
// exactly.
// ============================================================
module tb;
localparam DATA_WIDTH = 8;
localparam P_IN = 8;
localparam AB_DEPTH = 64;
localparam WB_DEPTH = 16;
localparam RB_DEPTH = 64;
reg clk;
initial begin clk = 0; forever #5 clk = ~clk; end
integer errors, tests;
// ---- activation_buffer ----
reg ab_wr_en;
reg [$clog2(AB_DEPTH)-1:0] ab_wr_addr, ab_rd_addr;
reg signed [DATA_WIDTH-1:0] ab_wr_data;
wire signed [DATA_WIDTH-1:0] ab_rd_data;
activation_buffer #(.DEPTH(AB_DEPTH), .DATA_WIDTH(DATA_WIDTH)) u_ab (
.clk(clk), .wr_en(ab_wr_en), .wr_addr(ab_wr_addr), .wr_data(ab_wr_data),
.rd_addr(ab_rd_addr), .rd_data(ab_rd_data)
);
// ---- weight_buffer ----
reg wb_wr_en;
reg [$clog2(WB_DEPTH)-1:0] wb_wr_addr, wb_rd_addr;
reg signed [DATA_WIDTH*P_IN-1:0] wb_wr_data;
wire signed [DATA_WIDTH*P_IN-1:0] wb_rd_data;
weight_buffer #(.DEPTH(WB_DEPTH), .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN)) u_wb (
.clk(clk), .wr_en(wb_wr_en), .wr_addr(wb_wr_addr), .wr_data(wb_wr_data),
.rd_addr(wb_rd_addr), .rd_data(wb_rd_data)
);
// ---- result_buffer ----
reg rb_wr_en;
reg [$clog2(RB_DEPTH)-1:0] rb_wr_addr, rb_rd_addr;
reg signed [DATA_WIDTH-1:0] rb_wr_data;
wire signed [DATA_WIDTH-1:0] rb_rd_data;
result_buffer #(.DEPTH(RB_DEPTH), .DATA_WIDTH(DATA_WIDTH)) u_rb (
.clk(clk), .wr_en(rb_wr_en), .wr_addr(rb_wr_addr), .wr_data(rb_wr_data),
.rd_addr(rb_rd_addr), .rd_data(rb_rd_data)
);
task automatic check_ab(input [$clog2(AB_DEPTH)-1:0] addr, input signed [DATA_WIDTH-1:0] exp_val);
begin
tests = tests + 1;
ab_rd_addr = addr;
@(posedge clk);
@(posedge clk); // registered read: value settles one cycle after rd_addr
if (ab_rd_data !== exp_val) begin
$display("FAIL activation_buffer[%0d]: got %0d expected %0d", addr, ab_rd_data, exp_val);
errors = errors + 1;
end else
$display("PASS activation_buffer[%0d] = %0d", addr, ab_rd_data);
end
endtask
task automatic check_wb(input [$clog2(WB_DEPTH)-1:0] addr, input signed [DATA_WIDTH*P_IN-1:0] exp_val);
begin
tests = tests + 1;
wb_rd_addr = addr;
@(posedge clk);
@(posedge clk);
if (wb_rd_data !== exp_val) begin
$display("FAIL weight_buffer[%0d]: got %h expected %h", addr, wb_rd_data, exp_val);
errors = errors + 1;
end else
$display("PASS weight_buffer[%0d] = %h", addr, wb_rd_data);
end
endtask
task automatic check_rb(input [$clog2(RB_DEPTH)-1:0] addr, input signed [DATA_WIDTH-1:0] exp_val);
begin
tests = tests + 1;
rb_rd_addr = addr;
@(posedge clk);
@(posedge clk);
if (rb_rd_data !== exp_val) begin
$display("FAIL result_buffer[%0d]: got %0d expected %0d", addr, rb_rd_data, exp_val);
errors = errors + 1;
end else
$display("PASS result_buffer[%0d] = %0d", addr, rb_rd_data);
end
endtask
integer i;
initial begin
errors = 0; tests = 0;
ab_wr_en = 0; ab_wr_addr = 0; ab_wr_data = 0; ab_rd_addr = 0;
wb_wr_en = 0; wb_wr_addr = 0; wb_wr_data = 0; wb_rd_addr = 0;
rb_wr_en = 0; rb_wr_addr = 0; rb_wr_data = 0; rb_rd_addr = 0;
@(posedge clk);
// ---- activation_buffer: write extreme + regular values at
// several addresses, confirm each reads back correctly and
// earlier writes are not disturbed by later ones. ----
@(posedge clk);
ab_wr_en = 1; ab_wr_addr = 0; ab_wr_data = -8'sd128; @(posedge clk);
ab_wr_addr = 1; ab_wr_data = 8'sd127; @(posedge clk);
ab_wr_addr = 5; ab_wr_data = 8'sd42; @(posedge clk);
ab_wr_addr = 63; ab_wr_data = -8'sd1; @(posedge clk);
ab_wr_en = 0;
check_ab(0, -8'sd128);
check_ab(1, 8'sd127);
check_ab(5, 8'sd42);
check_ab(63, -8'sd1);
check_ab(1, 8'sd127); // re-read: confirm earlier writes undisturbed
// ---- weight_buffer: write two whole tiles, confirm full
// TILE_WIDTH round-trips exactly (not just one lane). ----
@(posedge clk);
wb_wr_en = 1; wb_wr_addr = 0;
wb_wr_data = 0;
for (i = 0; i < P_IN; i = i + 1)
wb_wr_data[i*DATA_WIDTH +: DATA_WIDTH] = i[DATA_WIDTH-1:0]; // 0,1,2,...,7
@(posedge clk);
wb_wr_addr = 3;
wb_wr_data = 0;
for (i = 0; i < P_IN; i = i + 1)
wb_wr_data[i*DATA_WIDTH +: DATA_WIDTH] = -8'sd1; // all-lanes -1
@(posedge clk);
wb_wr_en = 0;
begin
reg signed [DATA_WIDTH*P_IN-1:0] expect0, expect3;
expect0 = 0;
for (i = 0; i < P_IN; i = i + 1) expect0[i*DATA_WIDTH +: DATA_WIDTH] = i[DATA_WIDTH-1:0];
expect3 = {P_IN{8'hFF}};
check_wb(0, expect0);
check_wb(3, expect3);
check_wb(0, expect0); // re-read: confirm undisturbed
end
// ---- result_buffer: same pattern as activation_buffer ----
@(posedge clk);
rb_wr_en = 1; rb_wr_addr = 7; rb_wr_data = 8'sd100; @(posedge clk);
rb_wr_addr = 8; rb_wr_data = -8'sd100; @(posedge clk);
rb_wr_en = 0;
check_rb(7, 8'sd100);
check_rb(8, -8'sd100);
$display("========================================");
if (errors == 0)
$display("ALL %0d TESTS PASSED (activation/weight/result buffers)", tests);
else
$display("FAILED: %0d/%0d test(s) had errors -- see messages above", errors, tests);
$display("========================================");
$finish;
end
endmodule
hardware/v2/synthesis/activation_buffer_d256/top.json
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hardware/v2/synthesis/activation_buffer_d256/yosys.log
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hardware/v2/synthesis/activation_buffer_d4096/nextpnr.log
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@@ -0,0 +1,231 @@
Info: Logic utilisation before packing:
Info: Total LUT4s: 37/43848 0%
Info: logic LUTs: 37/43848 0%
Info: carry LUTs: 0/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 30/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 0 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x79ea6f22
Info: Device utilisation:
Info: TRELLIS_IO: 42/ 245 17%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 2/ 108 1%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 30/ 43848 0%
Info: TRELLIS_COMB: 39/ 43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 52 cells, random placement wirelen = 6761.
Info: at initial placer iter 0, wirelen = 2512
Info: at initial placer iter 1, wirelen = 2493
Info: at initial placer iter 2, wirelen = 2489
Info: at initial placer iter 3, wirelen = 2489
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info: at iteration #1, type ALL: wirelen solved = 2490, spread = 2980, legal = 3609; time = 0.00s
Info: at iteration #2, type ALL: wirelen solved = 2499, spread = 2882, legal = 3446; time = 0.00s
Info: at iteration #3, type ALL: wirelen solved = 2487, spread = 2864, legal = 3310; time = 0.00s
Info: at iteration #4, type ALL: wirelen solved = 2497, spread = 2893, legal = 3455; time = 0.00s
Info: at iteration #5, type ALL: wirelen solved = 2495, spread = 2888, legal = 3449; time = 0.00s
Info: at iteration #6, type ALL: wirelen solved = 2516, spread = 2855, legal = 3121; time = 0.00s
Info: HeAP Placer Time: 0.02s
Info: of which solving equations: 0.00s
Info: of which spreading cells: 0.00s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 17, wirelen = 3121
Info: at iteration #5: temp = 0.000000, timing cost = 13, wirelen = 2026
Info: at iteration #10: temp = 0.000000, timing cost = 11, wirelen = 1982
Info: at iteration #15: temp = 0.000000, timing cost = 9, wirelen = 1976
Info: at iteration #15: temp = 0.000000, timing cost = 9, wirelen = 1977
Info: SA placement time 0.01s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 287.77 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.73 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.33 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 9025, 9161) |*
Info: [ 9161, 9297) |
Info: [ 9297, 9433) |
Info: [ 9433, 9569) |
Info: [ 9569, 9705) |
Info: [ 9705, 9841) |
Info: [ 9841, 9977) |
Info: [ 9977, 10113) |
Info: [ 10113, 10249) |
Info: [ 10249, 10385) |*
Info: [ 10385, 10521) |*****
Info: [ 10521, 10657) |********
Info: [ 10657, 10793) |************
Info: [ 10793, 10929) |*
Info: [ 10929, 11065) |*
Info: [ 11065, 11201) |
Info: [ 11201, 11337) |*
Info: [ 11337, 11473) |*****
Info: [ 11473, 11609) |**
Info: [ 11609, 11745) |******
Info: Checksum: 0xf7cffeae
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 211 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 221 | 10 200 | 10 200 | 0| 0.10 0.10|
Info: Routing complete.
Info: Router1 time 0.10s
Info: Checksum: 0x4d69308e
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source mem.0.1_ADA5_TRELLIS_FF_Q_1.Q
Info: routing 0.52 0.92 Net mem.0.1_ADA5[2] (27,17) -> (29,17)
Info: Sink mem.0.1_ADA11_LUT4_D_Z_LUT4_Z_1.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.10 Source mem.0.1_ADA11_LUT4_D_Z_LUT4_Z_1.F
Info: routing 0.51 1.61 Net mem.0.1_ADA11_LUT4_D_Z[5] (29,17) -> (29,18)
Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 1.80 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.00 1.80 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1 (29,18) -> (29,18)
Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72
Info: logic 0.18 1.98 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.55 2.53 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z[5] (29,18) -> (27,17)
Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 2.72 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.35 3.08 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI (27,17) -> (27,17)
Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1.M
Info: setup 0.00 3.08 Source mem.0.0_DOB0_TRELLIS_FF_Q_1.M
Info: 1.14 ns logic, 1.93 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source rd_addr[2]$tr_io.O
Info: routing 3.38 3.38 Net rd_addr[2]$TRELLIS_IO_IN (90,14) -> (28,18)
Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.56 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: routing 0.00 3.56 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT (28,18) -> (28,18)
Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32
Info: logic 0.13 3.69 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.00 3.69 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1 (28,18) -> (28,18)
Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
Info: logic 0.18 3.87 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.53 4.40 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z[2] (28,18) -> (27,17)
Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.58 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: routing 0.00 4.58 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT (27,17) -> (27,17)
Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32
Info: logic 0.13 4.70 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.00 4.70 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1 (27,17) -> (27,17)
Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
Info: logic 0.18 4.88 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.35 5.23 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI (27,17) -> (27,17)
Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1.M
Info: setup 0.00 5.23 Source mem.0.0_DOB0_TRELLIS_FF_Q_1.M
Info: 0.97 ns logic, 4.26 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 4.26 4.26 Source mem.0.0.DOB2
Info: routing 0.94 5.20 Net mem.0.0_DOB2[1] (26,10) -> (26,11)
Info: Sink rd_data_LUT4_Z_4.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v:46.13-46.16
Info: logic 0.18 5.38 Source rd_data_LUT4_Z_4.F
Info: routing 3.77 9.15 Net rd_data[2]$TRELLIS_IO_OUT (26,11) -> (15,71)
Info: Sink rd_data[2]$tr_io.I
Info: Defined in:
Info: hardware/v2/rtl/activation_buffer.v:33.41-33.48
Info: 4.44 ns logic, 4.71 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 325.20 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.23 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 9.15 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 9425, 9544) |*
Info: [ 9544, 9663) |
Info: [ 9663, 9782) |
Info: [ 9782, 9901) |
Info: [ 9901, 10020) |
Info: [ 10020, 10139) |
Info: [ 10139, 10258) |
Info: [ 10258, 10377) |
Info: [ 10377, 10496) |
Info: [ 10496, 10615) |
Info: [ 10615, 10734) |***
Info: [ 10734, 10853) |****
Info: [ 10853, 10972) |**************
Info: [ 10972, 11091) |****
Info: [ 11091, 11210) |
Info: [ 11210, 11329) |*********
Info: [ 11329, 11448) |
Info: [ 11448, 11567) |*
Info: [ 11567, 11686) |**
Info: [ 11686, 11805) |*****
Info: Program finished normally.
hardware/v2/synthesis/activation_buffer_d4096/top.config
+3388
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hardware/v2/synthesis/activation_buffer_d4096/top.json
+24708
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hardware/v2/synthesis/activation_buffer_d4096/yosys.log
+1175
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hardware/v2/synthesis/result_buffer_d256/top.json
+23413
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hardware/v2/synthesis/result_buffer_d256/yosys.log
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hardware/v2/synthesis/result_buffer_d4096/nextpnr.log
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@@ -0,0 +1,231 @@
Info: Logic utilisation before packing:
Info: Total LUT4s: 37/43848 0%
Info: logic LUTs: 37/43848 0%
Info: carry LUTs: 0/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 30/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 0 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x72c9a928
Info: Device utilisation:
Info: TRELLIS_IO: 42/ 245 17%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 2/ 108 1%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 30/ 43848 0%
Info: TRELLIS_COMB: 39/ 43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 52 cells, random placement wirelen = 6761.
Info: at initial placer iter 0, wirelen = 2512
Info: at initial placer iter 1, wirelen = 2493
Info: at initial placer iter 2, wirelen = 2489
Info: at initial placer iter 3, wirelen = 2489
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info: at iteration #1, type ALL: wirelen solved = 2490, spread = 2980, legal = 3609; time = 0.00s
Info: at iteration #2, type ALL: wirelen solved = 2499, spread = 2882, legal = 3446; time = 0.00s
Info: at iteration #3, type ALL: wirelen solved = 2487, spread = 2864, legal = 3310; time = 0.00s
Info: at iteration #4, type ALL: wirelen solved = 2497, spread = 2893, legal = 3455; time = 0.00s
Info: at iteration #5, type ALL: wirelen solved = 2495, spread = 2888, legal = 3449; time = 0.00s
Info: at iteration #6, type ALL: wirelen solved = 2516, spread = 2855, legal = 3121; time = 0.00s
Info: HeAP Placer Time: 0.02s
Info: of which solving equations: 0.00s
Info: of which spreading cells: 0.00s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 17, wirelen = 3121
Info: at iteration #5: temp = 0.000000, timing cost = 13, wirelen = 2026
Info: at iteration #10: temp = 0.000000, timing cost = 11, wirelen = 1982
Info: at iteration #15: temp = 0.000000, timing cost = 9, wirelen = 1976
Info: at iteration #15: temp = 0.000000, timing cost = 9, wirelen = 1977
Info: SA placement time 0.01s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 287.77 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.73 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.33 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 9025, 9161) |*
Info: [ 9161, 9297) |
Info: [ 9297, 9433) |
Info: [ 9433, 9569) |
Info: [ 9569, 9705) |
Info: [ 9705, 9841) |
Info: [ 9841, 9977) |
Info: [ 9977, 10113) |
Info: [ 10113, 10249) |
Info: [ 10249, 10385) |*
Info: [ 10385, 10521) |*****
Info: [ 10521, 10657) |********
Info: [ 10657, 10793) |************
Info: [ 10793, 10929) |*
Info: [ 10929, 11065) |*
Info: [ 11065, 11201) |
Info: [ 11201, 11337) |*
Info: [ 11337, 11473) |*****
Info: [ 11473, 11609) |**
Info: [ 11609, 11745) |******
Info: Checksum: 0x8fd0df74
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 211 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 221 | 10 200 | 10 200 | 0| 0.05 0.05|
Info: Routing complete.
Info: Router1 time 0.05s
Info: Checksum: 0xb7c8fedd
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source mem.0.1_ADA5_TRELLIS_FF_Q_1.Q
Info: routing 0.52 0.92 Net mem.0.1_ADA5[2] (27,17) -> (29,17)
Info: Sink mem.0.1_ADA11_LUT4_D_Z_LUT4_Z_1.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.10 Source mem.0.1_ADA11_LUT4_D_Z_LUT4_Z_1.F
Info: routing 0.51 1.61 Net mem.0.1_ADA11_LUT4_D_Z[5] (29,17) -> (29,18)
Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 1.80 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.00 1.80 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1 (29,18) -> (29,18)
Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72
Info: logic 0.18 1.98 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.55 2.53 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z[5] (29,18) -> (27,17)
Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 2.72 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.35 3.08 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI (27,17) -> (27,17)
Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1.M
Info: setup 0.00 3.08 Source mem.0.0_DOB0_TRELLIS_FF_Q_1.M
Info: 1.14 ns logic, 1.93 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source rd_addr[2]$tr_io.O
Info: routing 3.38 3.38 Net rd_addr[2]$TRELLIS_IO_IN (90,14) -> (28,18)
Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.56 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: routing 0.00 3.56 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT (28,18) -> (28,18)
Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32
Info: logic 0.13 3.69 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.00 3.69 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1 (28,18) -> (28,18)
Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
Info: logic 0.18 3.87 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.53 4.40 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z[2] (28,18) -> (27,17)
Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.58 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: routing 0.00 4.58 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT (27,17) -> (27,17)
Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32
Info: logic 0.13 4.70 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.00 4.70 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1 (27,17) -> (27,17)
Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
Info: logic 0.18 4.88 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.35 5.23 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI (27,17) -> (27,17)
Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1.M
Info: setup 0.00 5.23 Source mem.0.0_DOB0_TRELLIS_FF_Q_1.M
Info: 0.97 ns logic, 4.26 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 4.26 4.26 Source mem.0.0.DOB2
Info: routing 0.94 5.20 Net mem.0.0_DOB2[1] (26,10) -> (26,11)
Info: Sink rd_data_LUT4_Z_4.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v:46.13-46.16
Info: logic 0.18 5.38 Source rd_data_LUT4_Z_4.F
Info: routing 3.77 9.15 Net rd_data[2]$TRELLIS_IO_OUT (26,11) -> (15,71)
Info: Sink rd_data[2]$tr_io.I
Info: Defined in:
Info: hardware/v2/rtl/result_buffer.v:33.41-33.48
Info: 4.44 ns logic, 4.71 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 325.20 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.23 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 9.15 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 9425, 9544) |*
Info: [ 9544, 9663) |
Info: [ 9663, 9782) |
Info: [ 9782, 9901) |
Info: [ 9901, 10020) |
Info: [ 10020, 10139) |
Info: [ 10139, 10258) |
Info: [ 10258, 10377) |
Info: [ 10377, 10496) |
Info: [ 10496, 10615) |
Info: [ 10615, 10734) |***
Info: [ 10734, 10853) |****
Info: [ 10853, 10972) |**************
Info: [ 10972, 11091) |****
Info: [ 11091, 11210) |
Info: [ 11210, 11329) |*********
Info: [ 11329, 11448) |
Info: [ 11448, 11567) |*
Info: [ 11567, 11686) |**
Info: [ 11686, 11805) |*****
Info: Program finished normally.
hardware/v2/synthesis/result_buffer_d4096/top.config
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hardware/v2/synthesis/result_buffer_d4096/top.json
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hardware/v2/synthesis/result_buffer_d4096/yosys.log
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hardware/v2/synthesis/weight_buffer_d512/nextpnr.log
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Info: Logic utilisation before packing:
Info: Total LUT4s: 88/43848 0%
Info: logic LUTs: 88/43848 0%
Info: carry LUTs: 0/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 139/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 1 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x8d179719
Info: Device utilisation:
Info: TRELLIS_IO: 148/ 245 60%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 2/ 108 1%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 139/ 43848 0%
Info: TRELLIS_COMB: 90/ 43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 214 cells, random placement wirelen = 21853.
Info: at initial placer iter 0, wirelen = 8761
Info: at initial placer iter 1, wirelen = 8682
Info: at initial placer iter 2, wirelen = 8664
Info: at initial placer iter 3, wirelen = 8654
Info: Running main analytical placer, max placement attempts per cell = 18050.
Info: at iteration #1, type ALL: wirelen solved = 8649, spread = 9182, legal = 10156; time = 0.00s
Info: HeAP Placer Time: 0.02s
Info: of which solving equations: 0.00s
Info: of which spreading cells: 0.00s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 85, wirelen = 10156
Info: at iteration #5: temp = 0.000000, timing cost = 31, wirelen = 8157
Info: at iteration #10: temp = 0.000000, timing cost = 12, wirelen = 8054
Info: at iteration #13: temp = 0.000000, timing cost = 10, wirelen = 7961
Info: SA placement time 0.03s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 366.57 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.42 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.27 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 9772, 9871) |*
Info: [ 9871, 9970) |
Info: [ 9970, 10069) |*
Info: [ 10069, 10168) |
Info: [ 10168, 10267) |***
Info: [ 10267, 10366) |**
Info: [ 10366, 10465) |**
Info: [ 10465, 10564) |*******
Info: [ 10564, 10663) |****
Info: [ 10663, 10762) |*************
Info: [ 10762, 10861) |*****
Info: [ 10861, 10960) |******
Info: [ 10960, 11059) |**********
Info: [ 11059, 11158) |*******
Info: [ 11158, 11257) |***************
Info: [ 11257, 11356) |******
Info: [ 11356, 11455) |*************************
Info: [ 11455, 11554) |**********
Info: [ 11554, 11653) |*************
Info: [ 11653, 11752) |*************************
Info: Checksum: 0x6f062bf9
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 568 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 586 | 18 560 | 18 560 | 0| 0.09 0.09|
Info: Routing complete.
Info: Router1 time 0.09s
Info: Checksum: 0x1cfed5f0
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source mem.0.0_ADA8_TRELLIS_FF_Q.Q
Info: routing 0.67 1.06 Net mem.0.0_ADA8[1] (41,26) -> (41,27)
Info: Sink wr_en_TRELLIS_FF_DI_Q_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.24 Source wr_en_TRELLIS_FF_DI_Q_LUT4_Z.F
Info: routing 0.56 1.80 Net wr_en_TRELLIS_FF_DI_Q[6] (41,27) -> (40,28)
Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 2.00 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.65 2.65 Net mem.0.0_ADA5_LUT4_D_Z[2] (40,28) -> (40,26)
Info: Sink mem.0.0_DOA0_TRELLIS_FF_Q_1_DI_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.83 Source mem.0.0_DOA0_TRELLIS_FF_Q_1_DI_LUT4_Z.F
Info: routing 0.12 2.94 Net mem.0.0_DOA0_TRELLIS_FF_Q_1_DI (40,26) -> (40,26)
Info: Sink mem.0.0_DOA0_TRELLIS_FF_Q_1.DI
Info: setup 0.00 2.94 Source mem.0.0_DOA0_TRELLIS_FF_Q_1.DI
Info: 0.95 ns logic, 2.00 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source rd_addr[6]$tr_io.O
Info: routing 4.15 4.15 Net rd_addr[6]$TRELLIS_IO_IN (13,71) -> (41,25)
Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.A
Info: Defined in:
Info: hardware/v2/rtl/weight_buffer.v:33.48-33.55
Info: logic 0.18 4.33 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.F
Info: routing 0.00 4.33 Net mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT (41,25) -> (41,25)
Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24
Info: logic 0.13 4.45 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.00 4.45 Net mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 (41,25) -> (41,25)
Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52
Info: logic 0.18 4.63 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.00 4.63 Net mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0 (41,25) -> (41,25)
Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68
Info: logic 0.18 4.81 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.52 5.34 Net mem.0.0_ADA5_LUT4_D_Z[3] (41,25) -> (40,26)
Info: Sink mem.0.0_DOA0_TRELLIS_FF_Q_1_DI_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.52 Source mem.0.0_DOA0_TRELLIS_FF_Q_1_DI_LUT4_Z.F
Info: routing 0.12 5.63 Net mem.0.0_DOA0_TRELLIS_FF_Q_1_DI (40,26) -> (40,26)
Info: Sink mem.0.0_DOA0_TRELLIS_FF_Q_1.DI
Info: setup 0.00 5.63 Source mem.0.0_DOA0_TRELLIS_FF_Q_1.DI
Info: 0.84 ns logic, 4.79 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 4.26 4.26 Source mem.0.0.DOB10
Info: routing 1.07 5.33 Net mem.0.0_DOB10[0] (37,34) -> (37,35)
Info: Sink rd_data_LUT4_Z_30.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.51 Source rd_data_LUT4_Z_30.F
Info: routing 3.27 8.78 Net rd_data[28]$TRELLIS_IO_OUT (37,35) -> (67,0)
Info: Sink rd_data[28]$tr_io.I
Info: Defined in:
Info: hardware/v2/rtl/weight_buffer.v:34.48-34.55
Info: 4.44 ns logic, 4.33 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 339.67 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.63 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.78 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 9556, 9668) |*
Info: [ 9668, 9780) |
Info: [ 9780, 9892) |
Info: [ 9892, 10004) |
Info: [ 10004, 10116) |
Info: [ 10116, 10228) |
Info: [ 10228, 10340) |
Info: [ 10340, 10452) |
Info: [ 10452, 10564) |
Info: [ 10564, 10676) |****
Info: [ 10676, 10788) |*****
Info: [ 10788, 10900) |*****
Info: [ 10900, 11012) |************************
Info: [ 11012, 11124) |********************
Info: [ 11124, 11236) |***************
Info: [ 11236, 11348) |*****************
Info: [ 11348, 11460) |***********
Info: [ 11460, 11572) |*************
Info: [ 11572, 11684) |***********
Info: [ 11684, 11796) |*****************************
Info: Program finished normally.
hardware/v2/synthesis/weight_buffer_d512/top.config
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hardware/v2/synthesis/weight_buffer_d64/top.json
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