diff --git a/hardware/v2/docs/ROADMAP.md b/hardware/v2/docs/ROADMAP.md index 7c6626a..d05af2b 100644 --- a/hardware/v2/docs/ROADMAP.md +++ b/hardware/v2/docs/ROADMAP.md @@ -18,8 +18,10 @@ reali, non solo scritto). Fmax sempre PASS a 80MHz (159.11→134.70 MHz). Scoperta: il DSP (MULT18X18D), non LUT/FF, satura per primo (88% a N=8) — vedi `logs/decisions.log` DEC-0005. -- [ ] **M3 — Buffers** (`activation_buffer.v`, `weight_buffer.v`, - `result_buffer.v`). +- [x] **M3 — Buffers** (`activation_buffer.v`, `weight_buffer.v`, + `result_buffer.v`). Tutti inferiscono DP16KD reale (10/10 test, + 6/6 config sintetizzate 0 problemi). Scoperta: il costo BRAM di + weight_buffer e' guidato da P_IN (larghezza), non da DEPTH. - [ ] **M4 — Memory Manager** (`memory_manager.v`, `prefetch_engine.v`), backend PSRAM V1 riusato senza modifiche. - [ ] **M5 — Neural Director** (`neural_director.v`), scheduling first-free. diff --git a/hardware/v2/logs/benchmark.log b/hardware/v2/logs/benchmark.log index 8adec52..a3213c6 100644 --- a/hardware/v2/logs/benchmark.log +++ b/hardware/v2/logs/benchmark.log @@ -40,3 +40,22 @@ until M9): N_PROCESSORS * P_IN MACs/cycle when all processors are simultaneously streaming tiles (8, 16, 32, 64 for N=1/2/4/8 -- verified achievable in principle by EXP-0003's concurrent/staggered simulation, not yet measured as a sustained throughput number). + +[2026-09-05] M3 buffers -- BRAM cost vs DEPTH (real Yosys synth_ecp5) + +| Module | DEPTH | DP16KD | LUT4 | FF | +|--------------------|-------|--------|------|-----| +| activation_buffer | 4096 | 2 | 37 | 30 | +| activation_buffer | 256 | 1 | 21 | 26 | +| weight_buffer | 512 | 2 | 88 | 139 | +| weight_buffer | 64 | 2 | 73 | 136 | +| result_buffer | 4096 | 2 | 37 | 30 | +| result_buffer | 256 | 1 | 21 | 26 | + +weight_buffer's DP16KD count is flat across an 8x depth reduction -- +its 64-bit TILE_WIDTH (P_IN=8 * DATA_WIDTH=8), not DEPTH, determines +BRAM count for this module. activation_buffer/result_buffer (byte- +wide) scale as expected with depth. Confirms §14's warning literally: +"non assumere che buffer piu' grandi siano automaticamente migliori" +-- here, smaller was not cheaper either, because depth was the wrong +lever for this specific buffer's cost. diff --git a/hardware/v2/logs/development.log b/hardware/v2/logs/development.log index 4fe5296..90d5021 100644 --- a/hardware/v2/logs/development.log +++ b/hardware/v2/logs/development.log @@ -88,3 +88,25 @@ errors: ERR-0005 (artefatto di sintesi da pin-count, non un bug RTL -- decision: vedi decisions.log DEC-0005. next_action: M3 -- activation_buffer.v / weight_buffer.v / result_buffer.v (profondita' parametrica, valutare BRAM mapping). + +[2026-09-05T15:15:00Z] commit=3026dcd session=v2-M3-buffers +module: hardware/v2/rtl/activation_buffer.v, weight_buffer.v, + result_buffer.v +action: implementato M3 -- tre buffer paramentrici (profondita' + parametrica) che inferiscono DP16KD reale, riusando l'idioma gia' + validato in hardware/v1/rtl/act_buffer.v (porta A scrittura sync, + porta B lettura sync REGISTRATA, nessun reset sulla porta di lettura + per restare fuori dal percorso LUT-RAM). +reason: roadmap M3. +result: 10/10 test PASS (Verilator). Sintesi reale a 2 profondita' + ciascuno: 0 problemi CHECK, DP16KD reale confermato in tutte le 6 + configurazioni (mai LUT-RAM). Scoperta reale non assunta: il costo + BRAM di weight_buffer e' determinato dalla LARGHEZZA (P_IN*DATA_ + WIDTH=64 bit), non dalla profondita' -- 512->64 di profondita' non + ha ridotto il conteggio DP16KD (resta 2). Place&route reale sui + default: tutti PASS a 80MHz con ampio margine (287-367 MHz). +errors: nessuno. +decision: vedi benchmark.log -- il dimensionamento di weight_buffer + andra' guidato da P_IN, non solo da DEPTH, quando si arrivera' a + M4/M9. +next_action: M4 -- memory_manager.v + prefetch_engine.v. diff --git a/hardware/v2/logs/experiments.log b/hardware/v2/logs/experiments.log index bad4b18..1e05658 100644 --- a/hardware/v2/logs/experiments.log +++ b/hardware/v2/logs/experiments.log @@ -159,3 +159,62 @@ decision: see decisions.log DEC-0005 (DSP is the binding constraint, be explored going forward). next_action: M3 -- activation_buffer.v / weight_buffer.v / result_buffer.v. + +EXP-0004 +timestamp: 2026-09-05T15:15:00Z +git_commit: 3026dcd (+ uncommitted M3 work) +session: v2-M3-buffers +module: hardware/v2/rtl/activation_buffer.v, weight_buffer.v, + result_buffer.v +configuration: activation_buffer/result_buffer DEPTH in {4096, 256}; + weight_buffer DEPTH (in tiles) in {512, 64}, P_IN=8, DATA_WIDTH=8 + (TILE_WIDTH=64 bits) +action: M3 -- three parametric dual-port BRAM-inferring buffers + (Input/Weight/Result of the §12 data-plane diagram), reusing the + proven inference idiom from hardware/v1/rtl/act_buffer.v (sync + write, sync REGISTERED read, no reset on the read register). +command (sim, Verilator): verilator --binary --timing -j 0 -Wno-fatal + --top-module tb -o /tmp/vtb_buffers hardware/v2/rtl/ + activation_buffer.v hardware/v2/rtl/weight_buffer.v + hardware/v2/rtl/result_buffer.v hardware/v2/sim/tb_buffers.v && + /tmp/vtb_buffers +command (synth): yosys -p "read_verilog ; chparam -set DEPTH + ; synth_ecp5 -json .../top.json -top " for each + of the 6 (module, depth) combinations. +command (timing): nextpnr-ecp5 --45k --package CABGA381 --speed 8 + --freq 80 --lpf-allow-unconstrained, default-depth configs only. +result: + SIMULATED: 10/10 tests PASS -- write-then-read correctness incl. + extreme INT8 (-128/127) round-tripping exactly, back-to-back + writes to different addresses not disturbing earlier entries, and + weight_buffer's full 64-bit TILE_WIDTH round-tripping (not just + one lane). + SYNTHESIZED (real BRAM mapping, not assumed): + activation_buffer DEPTH=4096: 2 DP16KD, 37 LUT4, 30 FF + activation_buffer DEPTH=256: 1 DP16KD, 21 LUT4, 26 FF + weight_buffer DEPTH=512: 2 DP16KD, 88 LUT4, 139 FF + weight_buffer DEPTH=64: 2 DP16KD, 73 LUT4, 136 FF + result_buffer DEPTH=4096: 2 DP16KD, 37 LUT4, 30 FF + result_buffer DEPTH=256: 1 DP16KD, 21 LUT4, 26 FF + 0 CHECK problems in all 6 configurations -- every one correctly + inferred DP16KD block RAM, none fell back to LUT-RAM. + REAL, NON-OBVIOUS FINDING (§14: "non assumere che buffer piu' grandi + siano automaticamente migliori"): shrinking weight_buffer's DEPTH + 8x (512->64) did NOT reduce DP16KD usage at all (2->2) -- its + 64-bit TILE_WIDTH (P_IN*DATA_WIDTH), not its depth, is what forces + 2 physical block RAMs (a single DP16KD's usable port width in the + density this needs is narrower than 64 bits). Depth-only buffer + sizing decisions are the wrong lever for THIS buffer; width + (P_IN) is. activation_buffer/result_buffer, being byte-wide, DO + show the expected depth-proportional DP16KD count (2 -> 1). + POST-P&R (default-depth configs): all PASS at 80MHz with large + margin (287-367 MHz range, real place&route) -- these buffers are + not a timing concern in isolation. +errors: none. +decision: keep DEPTH parametric as specified, but document (this + entry + benchmark.log) that weight_buffer's real BRAM cost is driven + by P_IN (its width), not DEPTH -- relevant when M4/M9 size these + buffers against a real workload. +next_action: M4 -- memory_manager.v + prefetch_engine.v (wires these + three buffers + the array together, PSRAM backend reused unmodified + from V1 per §15). diff --git a/hardware/v2/logs/simulation.log b/hardware/v2/logs/simulation.log index e3b90ee..adc53ee 100644 --- a/hardware/v2/logs/simulation.log +++ b/hardware/v2/logs/simulation.log @@ -28,3 +28,11 @@ concurrency: confirmed genuine -- in the staggered test, the later-launched, shorter job (processor 1) completes BEFORE the earlier-launched, longer job (processor 0), proving independent progress rather than serialization. + +[2026-09-05] EXP-0004 -- hardware/v2/sim/tb_buffers.v +test: 10 cases across activation_buffer/weight_buffer/result_buffer +vectors: extreme INT8 (-128, 127, -100, 100), regular values, full + 64-bit tile round-trip (weight_buffer), re-reads confirming earlier + writes undisturbed +simulator: Verilator 5.050 (--binary --timing) +PASS/FAIL: 10/10 PASS diff --git a/hardware/v2/logs/synthesis.log b/hardware/v2/logs/synthesis.log index 81e24c5..bed6e8d 100644 --- a/hardware/v2/logs/synthesis.log +++ b/hardware/v2/logs/synthesis.log @@ -27,3 +27,12 @@ CHECK: 0 problems in all 4 configurations. Perfectly linear scaling in flawed harness attempt fed identical data to every processor/lane and Yosys silently deduplicated down to 1x regardless of N -- caught by checking for exactly this linearity before trusting the numbers). + +[2026-09-05] EXP-0004 -- activation_buffer/weight_buffer/result_buffer, +2 depths each +activation_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1) +weight_buffer D=512: LUT=88 FF=139 DP16KD=2 (D=64: LUT=73 FF=136 DP16KD=2) +result_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1) +CHECK: 0 problems, all 6 configs correctly infer DP16KD (no LUT-RAM + fallback). weight_buffer's DP16KD count does NOT drop with depth + (width-bound, not depth-bound -- see decisions.log / benchmark.log). diff --git a/hardware/v2/logs/timing.log b/hardware/v2/logs/timing.log index b63b7a3..699ab0b 100644 --- a/hardware/v2/logs/timing.log +++ b/hardware/v2/logs/timing.log @@ -31,3 +31,10 @@ TRELLIS_IO stays at 18/245 (7%) throughout (harness has only clk/rst/seed/checksum as real pins, by design -- see ERR-0005). See decisions.log DEC-0005: DSP, not Fmax or LUT/FF, is the resource that will first prevent scaling N_PROCESSORS further at P_IN=8. + +[2026-09-05] EXP-0004 -- default-depth buffer configs, real nextpnr-ecp5 +activation_buffer (D=4096): Fmax=325.20 MHz PASS +weight_buffer (D=512): Fmax=339.67 MHz PASS +result_buffer (D=4096): Fmax=325.20 MHz PASS +All far above the 80MHz target -- buffers are not a timing concern in +isolation at these depths. diff --git a/hardware/v2/rtl/activation_buffer.v b/hardware/v2/rtl/activation_buffer.v new file mode 100644 index 0000000..1fc64d0 --- /dev/null +++ b/hardware/v2/rtl/activation_buffer.v @@ -0,0 +1,47 @@ +`timescale 1ns/1ps + +// ================================================================ +// FPGA-Neural V2 -- Activation Buffer (M3, docs/v2-description.md §14) +// +// Holds the "Input Buffer" of the §12 data-plane diagram: one INT8 +// activation slot per signal id, read by the Neural Processor Array +// (via the Memory Manager, M4) and written by producers (external +// input load, or a Neural Processor's own result forwarded here for +// a downstream consumer). +// +// Same proven BRAM-inference idiom as hardware/v1/rtl/act_buffer.v +// (frozen, unmodified reference): dual-port, byte-addressed, Port A +// synchronous write, Port B synchronous REGISTERED read (1-cycle +// latency, no `rst` on the read register -- a synchronous reset on an +// indexed array forces Yosys onto LUT-RAM instead of a Lattice +// DP16KD block RAM). DEPTH is fully parametric (§14: "la profondita' +// deve essere parametrica"). +// ================================================================ + +module activation_buffer #( + parameter DEPTH = 4096, + parameter DATA_WIDTH = 8, + localparam ADDR_WIDTH = $clog2(DEPTH) +)( + input wire clk, + + input wire wr_en, + input wire [ADDR_WIDTH-1:0] wr_addr, + input wire signed [DATA_WIDTH-1:0] wr_data, + + input wire [ADDR_WIDTH-1:0] rd_addr, + output reg signed [DATA_WIDTH-1:0] rd_data +); + + reg signed [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + + always @(posedge clk) begin + if (wr_en) + mem[wr_addr] <= wr_data; + end + + always @(posedge clk) begin + rd_data <= mem[rd_addr]; + end + +endmodule diff --git a/hardware/v2/rtl/result_buffer.v b/hardware/v2/rtl/result_buffer.v new file mode 100644 index 0000000..0234e26 --- /dev/null +++ b/hardware/v2/rtl/result_buffer.v @@ -0,0 +1,47 @@ +`timescale 1ns/1ps + +// ================================================================ +// FPGA-Neural V2 -- Result Buffer (M3, docs/v2-description.md §14) +// +// Holds the "Result Buffer" of the §12 data-plane diagram: one INT8 +// slot per node id, written by a Neural Processor's result_data (at +// its result_node_id address) once its job's tile_last has drained +// through the pipeline (M1), and read by whichever consumer needs it +// next -- a downstream layer's Weight/Activation Buffer producer, the +// Dependency Manager (M6, dependency resolution), or the host +// (READ_RAM-equivalent path, M4/M8). +// +// Same BRAM-inference idiom as activation_buffer.v (dual-port, Port A +// sync write, Port B sync REGISTERED read, no reset on the read +// register). DEPTH is fully parametric. Deliberately NOT tracking +// "has this id been written yet" here -- that bookkeeping belongs to +// the Dependency Manager (M6), not this buffer. +// ================================================================ + +module result_buffer #( + parameter DEPTH = 4096, + parameter DATA_WIDTH = 8, + localparam ADDR_WIDTH = $clog2(DEPTH) +)( + input wire clk, + + input wire wr_en, + input wire [ADDR_WIDTH-1:0] wr_addr, + input wire signed [DATA_WIDTH-1:0] wr_data, + + input wire [ADDR_WIDTH-1:0] rd_addr, + output reg signed [DATA_WIDTH-1:0] rd_data +); + + reg signed [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + + always @(posedge clk) begin + if (wr_en) + mem[wr_addr] <= wr_data; + end + + always @(posedge clk) begin + rd_data <= mem[rd_addr]; + end + +endmodule diff --git a/hardware/v2/rtl/weight_buffer.v b/hardware/v2/rtl/weight_buffer.v new file mode 100644 index 0000000..3101597 --- /dev/null +++ b/hardware/v2/rtl/weight_buffer.v @@ -0,0 +1,48 @@ +`timescale 1ns/1ps + +// ================================================================ +// FPGA-Neural V2 -- Weight Buffer (M3, docs/v2-description.md §14) +// +// Holds the "Weight Buffer" of the §12 data-plane diagram. Unlike +// activation_buffer (one INT8 per signal id), each address here holds +// one WHOLE TILE of P_IN weights -- exactly the width a Neural +// Processor (M1) consumes per cycle on its weight_data port, so the +// Memory Manager (M4) can feed a processor one tile/cycle without any +// additional muxing/serialization at this buffer's boundary (§7: +// avoid big dynamic muxes). +// +// Same BRAM-inference idiom as activation_buffer.v / +// hardware/v1/rtl/act_buffer.v (dual-port, Port A sync write, Port B +// sync REGISTERED read, no reset on the read register). DEPTH (in +// TILES, not individual weights) is fully parametric. +// ================================================================ + +module weight_buffer #( + parameter DEPTH = 512, // depth in TILES (each DEPTH*P_IN*DATA_WIDTH/8 bytes) + parameter DATA_WIDTH = 8, + parameter P_IN = 8, + localparam ADDR_WIDTH = $clog2(DEPTH), + localparam TILE_WIDTH = DATA_WIDTH * P_IN +)( + input wire clk, + + input wire wr_en, + input wire [ADDR_WIDTH-1:0] wr_addr, + input wire signed [TILE_WIDTH-1:0] wr_data, + + input wire [ADDR_WIDTH-1:0] rd_addr, + output reg signed [TILE_WIDTH-1:0] rd_data +); + + reg signed [TILE_WIDTH-1:0] mem [0:DEPTH-1]; + + always @(posedge clk) begin + if (wr_en) + mem[wr_addr] <= wr_data; + end + + always @(posedge clk) begin + rd_data <= mem[rd_addr]; + end + +endmodule diff --git a/hardware/v2/sim/tb_buffers.v b/hardware/v2/sim/tb_buffers.v new file mode 100644 index 0000000..197e458 --- /dev/null +++ b/hardware/v2/sim/tb_buffers.v @@ -0,0 +1,169 @@ +`timescale 1ns/1ps + +// ============================================================ +// M3 testbench (docs/v2-description.md §14/§20): activation_buffer.v, +// weight_buffer.v, result_buffer.v. Verified with Verilator (see +// hardware/v2/logs/decisions.log DEC-0004). +// +// Coverage: write-then-read correctness (incl. the 1-cycle registered +// read latency all three share with hardware/v1/rtl/act_buffer.v), +// back-to-back writes to different addresses without corrupting +// earlier entries, and extreme INT8 values (-128, 127) round-tripping +// exactly. +// ============================================================ + +module tb; + + localparam DATA_WIDTH = 8; + localparam P_IN = 8; + localparam AB_DEPTH = 64; + localparam WB_DEPTH = 16; + localparam RB_DEPTH = 64; + + reg clk; + initial begin clk = 0; forever #5 clk = ~clk; end + + integer errors, tests; + + // ---- activation_buffer ---- + reg ab_wr_en; + reg [$clog2(AB_DEPTH)-1:0] ab_wr_addr, ab_rd_addr; + reg signed [DATA_WIDTH-1:0] ab_wr_data; + wire signed [DATA_WIDTH-1:0] ab_rd_data; + + activation_buffer #(.DEPTH(AB_DEPTH), .DATA_WIDTH(DATA_WIDTH)) u_ab ( + .clk(clk), .wr_en(ab_wr_en), .wr_addr(ab_wr_addr), .wr_data(ab_wr_data), + .rd_addr(ab_rd_addr), .rd_data(ab_rd_data) + ); + + // ---- weight_buffer ---- + reg wb_wr_en; + reg [$clog2(WB_DEPTH)-1:0] wb_wr_addr, wb_rd_addr; + reg signed [DATA_WIDTH*P_IN-1:0] wb_wr_data; + wire signed [DATA_WIDTH*P_IN-1:0] wb_rd_data; + + weight_buffer #(.DEPTH(WB_DEPTH), .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN)) u_wb ( + .clk(clk), .wr_en(wb_wr_en), .wr_addr(wb_wr_addr), .wr_data(wb_wr_data), + .rd_addr(wb_rd_addr), .rd_data(wb_rd_data) + ); + + // ---- result_buffer ---- + reg rb_wr_en; + reg [$clog2(RB_DEPTH)-1:0] rb_wr_addr, rb_rd_addr; + reg signed [DATA_WIDTH-1:0] rb_wr_data; + wire signed [DATA_WIDTH-1:0] rb_rd_data; + + result_buffer #(.DEPTH(RB_DEPTH), .DATA_WIDTH(DATA_WIDTH)) u_rb ( + .clk(clk), .wr_en(rb_wr_en), .wr_addr(rb_wr_addr), .wr_data(rb_wr_data), + .rd_addr(rb_rd_addr), .rd_data(rb_rd_data) + ); + + task automatic check_ab(input [$clog2(AB_DEPTH)-1:0] addr, input signed [DATA_WIDTH-1:0] exp_val); + begin + tests = tests + 1; + ab_rd_addr = addr; + @(posedge clk); + @(posedge clk); // registered read: value settles one cycle after rd_addr + if (ab_rd_data !== exp_val) begin + $display("FAIL activation_buffer[%0d]: got %0d expected %0d", addr, ab_rd_data, exp_val); + errors = errors + 1; + end else + $display("PASS activation_buffer[%0d] = %0d", addr, ab_rd_data); + end + endtask + + task automatic check_wb(input [$clog2(WB_DEPTH)-1:0] addr, input signed [DATA_WIDTH*P_IN-1:0] exp_val); + begin + tests = tests + 1; + wb_rd_addr = addr; + @(posedge clk); + @(posedge clk); + if (wb_rd_data !== exp_val) begin + $display("FAIL weight_buffer[%0d]: got %h expected %h", addr, wb_rd_data, exp_val); + errors = errors + 1; + end else + $display("PASS weight_buffer[%0d] = %h", addr, wb_rd_data); + end + endtask + + task automatic check_rb(input [$clog2(RB_DEPTH)-1:0] addr, input signed [DATA_WIDTH-1:0] exp_val); + begin + tests = tests + 1; + rb_rd_addr = addr; + @(posedge clk); + @(posedge clk); + if (rb_rd_data !== exp_val) begin + $display("FAIL result_buffer[%0d]: got %0d expected %0d", addr, rb_rd_data, exp_val); + errors = errors + 1; + end else + $display("PASS result_buffer[%0d] = %0d", addr, rb_rd_data); + end + endtask + + integer i; + + initial begin + errors = 0; tests = 0; + ab_wr_en = 0; ab_wr_addr = 0; ab_wr_data = 0; ab_rd_addr = 0; + wb_wr_en = 0; wb_wr_addr = 0; wb_wr_data = 0; wb_rd_addr = 0; + rb_wr_en = 0; rb_wr_addr = 0; rb_wr_data = 0; rb_rd_addr = 0; + @(posedge clk); + + // ---- activation_buffer: write extreme + regular values at + // several addresses, confirm each reads back correctly and + // earlier writes are not disturbed by later ones. ---- + @(posedge clk); + ab_wr_en = 1; ab_wr_addr = 0; ab_wr_data = -8'sd128; @(posedge clk); + ab_wr_addr = 1; ab_wr_data = 8'sd127; @(posedge clk); + ab_wr_addr = 5; ab_wr_data = 8'sd42; @(posedge clk); + ab_wr_addr = 63; ab_wr_data = -8'sd1; @(posedge clk); + ab_wr_en = 0; + check_ab(0, -8'sd128); + check_ab(1, 8'sd127); + check_ab(5, 8'sd42); + check_ab(63, -8'sd1); + check_ab(1, 8'sd127); // re-read: confirm earlier writes undisturbed + + // ---- weight_buffer: write two whole tiles, confirm full + // TILE_WIDTH round-trips exactly (not just one lane). ---- + @(posedge clk); + wb_wr_en = 1; wb_wr_addr = 0; + wb_wr_data = 0; + for (i = 0; i < P_IN; i = i + 1) + wb_wr_data[i*DATA_WIDTH +: DATA_WIDTH] = i[DATA_WIDTH-1:0]; // 0,1,2,...,7 + @(posedge clk); + wb_wr_addr = 3; + wb_wr_data = 0; + for (i = 0; i < P_IN; i = i + 1) + wb_wr_data[i*DATA_WIDTH +: DATA_WIDTH] = -8'sd1; // all-lanes -1 + @(posedge clk); + wb_wr_en = 0; + + begin + reg signed [DATA_WIDTH*P_IN-1:0] expect0, expect3; + expect0 = 0; + for (i = 0; i < P_IN; i = i + 1) expect0[i*DATA_WIDTH +: DATA_WIDTH] = i[DATA_WIDTH-1:0]; + expect3 = {P_IN{8'hFF}}; + check_wb(0, expect0); + check_wb(3, expect3); + check_wb(0, expect0); // re-read: confirm undisturbed + end + + // ---- result_buffer: same pattern as activation_buffer ---- + @(posedge clk); + rb_wr_en = 1; rb_wr_addr = 7; rb_wr_data = 8'sd100; @(posedge clk); + rb_wr_addr = 8; rb_wr_data = -8'sd100; @(posedge clk); + rb_wr_en = 0; + check_rb(7, 8'sd100); + check_rb(8, -8'sd100); + + $display("========================================"); + if (errors == 0) + $display("ALL %0d TESTS PASSED (activation/weight/result buffers)", tests); + else + $display("FAILED: %0d/%0d test(s) had errors -- see messages above", errors, tests); + $display("========================================"); + $finish; + end + +endmodule diff --git a/hardware/v2/synthesis/activation_buffer_d256/top.json b/hardware/v2/synthesis/activation_buffer_d256/top.json new file mode 100644 index 0000000..77dca79 --- /dev/null +++ b/hardware/v2/synthesis/activation_buffer_d256/top.json @@ -0,0 +1,23413 @@ +{ + "creator": "Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)", + "modules": { + "$__ABC9_DELAY": { + "attributes": { + "abc9_box_id": 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"CH0_TDRV_SLICE5_CUR": "DONTCARE", + "CH0_TDRV_SLICE5_SEL": "DONTCARE", + "CH0_TPWDNB": "DONTCARE", + "CH0_TXAMPLITUDE": "DONTCARE", + "CH0_TXDEPOST": "DONTCARE", + "CH0_TXDEPRE": "DONTCARE", + "CH0_TX_CM_SEL": "DONTCARE", + "CH0_TX_DIV11_SEL": "DONTCARE", + "CH0_TX_GEAR_BYPASS": "DONTCARE", + "CH0_TX_GEAR_MODE": "DONTCARE", + "CH0_TX_POST_SIGN": "DONTCARE", + "CH0_TX_PRE_SIGN": "DONTCARE", + "CH0_UC_MODE": "DONTCARE", + "CH0_UDF_COMMA_A": "DONTCARE", + "CH0_UDF_COMMA_B": "DONTCARE", + "CH0_UDF_COMMA_MASK": "DONTCARE", + "CH0_WA_BYPASS": "DONTCARE", + "CH0_WA_MODE": "DONTCARE", + "CH1_AUTO_CALIB_EN": "DONTCARE", + "CH1_AUTO_FACQ_EN": "DONTCARE", + "CH1_BAND_THRESHOLD": "DONTCARE", + "CH1_CALIB_CK_MODE": "DONTCARE", + "CH1_CC_MATCH_1": "DONTCARE", + "CH1_CC_MATCH_2": "DONTCARE", + "CH1_CC_MATCH_3": "DONTCARE", + "CH1_CC_MATCH_4": "DONTCARE", + "CH1_CDR_CNT4SEL": "DONTCARE", + "CH1_CDR_CNT8SEL": "DONTCARE", + "CH1_CDR_MAX_RATE": "DONTCARE", + "CH1_CTC_BYPASS": "DONTCARE", + "CH1_DCOATDCFG": "DONTCARE", + "CH1_DCOATDDLY": "DONTCARE", + "CH1_DCOBYPSATD": "DONTCARE", + "CH1_DCOCALDIV": "DONTCARE", + "CH1_DCOCTLGI": "DONTCARE", + "CH1_DCODISBDAVOID": "DONTCARE", + "CH1_DCOFLTDAC": "DONTCARE", + "CH1_DCOFTNRG": "DONTCARE", + "CH1_DCOIOSTUNE": "DONTCARE", + "CH1_DCOITUNE": "DONTCARE", + "CH1_DCOITUNE4LSB": "DONTCARE", + "CH1_DCOIUPDNX2": "DONTCARE", + "CH1_DCONUOFLSB": "DONTCARE", + "CH1_DCOSCALEI": "DONTCARE", + "CH1_DCOSTARTVAL": "DONTCARE", + "CH1_DCOSTEP": "DONTCARE", + "CH1_DEC_BYPASS": "DONTCARE", + "CH1_ENABLE_CG_ALIGN": "DONTCARE", + "CH1_ENC_BYPASS": "DONTCARE", + "CH1_FF_RX_F_CLK_DIS": "DONTCARE", + "CH1_FF_RX_H_CLK_EN": "DONTCARE", + "CH1_FF_TX_F_CLK_DIS": "DONTCARE", + "CH1_FF_TX_H_CLK_EN": "DONTCARE", + "CH1_GE_AN_ENABLE": "DONTCARE", + "CH1_INVERT_RX": "DONTCARE", + "CH1_INVERT_TX": "DONTCARE", + "CH1_LDR_CORE2TX_SEL": "DONTCARE", + "CH1_LDR_RX2CORE_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_TRIM": "DONTCARE", + "CH1_LSM_DISABLE": "DONTCARE", + "CH1_MATCH_2_ENABLE": "DONTCARE", + "CH1_MATCH_4_ENABLE": "DONTCARE", + "CH1_MIN_IPG_CNT": "DONTCARE", + "CH1_PCIE_EI_EN": "DONTCARE", + "CH1_PCIE_MODE": "DONTCARE", + "CH1_PCS_DET_TIME_SEL": "DONTCARE", + "CH1_PDEN_SEL": "DONTCARE", + "CH1_PRBS_ENABLE": "DONTCARE", + "CH1_PRBS_LOCK": "DONTCARE", + "CH1_PRBS_SELECTION": "DONTCARE", + "CH1_PROTOCOL": "DONTCARE", + "CH1_RATE_MODE_RX": "DONTCARE", + "CH1_RATE_MODE_TX": "DONTCARE", + "CH1_RCV_DCC_EN": "DONTCARE", + "CH1_REG_BAND_OFFSET": "DONTCARE", + "CH1_REG_BAND_SEL": "DONTCARE", + "CH1_REG_IDAC_EN": "DONTCARE", + "CH1_REG_IDAC_SEL": "DONTCARE", + "CH1_REQ_EN": "DONTCARE", + "CH1_REQ_LVL_SET": "DONTCARE", + "CH1_RIO_MODE": "DONTCARE", + "CH1_RLOS_SEL": "DONTCARE", + "CH1_RPWDNB": "DONTCARE", + "CH1_RTERM_RX": "DONTCARE", + "CH1_RTERM_TX": "DONTCARE", + "CH1_RXIN_CM": "DONTCARE", + "CH1_RXTERM_CM": "DONTCARE", + "CH1_RX_DCO_CK_DIV": "DONTCARE", + "CH1_RX_DIV11_SEL": "DONTCARE", + "CH1_RX_GEAR_BYPASS": "DONTCARE", + "CH1_RX_GEAR_MODE": "DONTCARE", + "CH1_RX_LOS_CEQ": "DONTCARE", + "CH1_RX_LOS_EN": "DONTCARE", + "CH1_RX_LOS_HYST_EN": "DONTCARE", + "CH1_RX_LOS_LVL": "DONTCARE", + "CH1_RX_RATE_SEL": "DONTCARE", + "CH1_RX_SB_BYPASS": "DONTCARE", + "CH1_SB_BYPASS": "DONTCARE", + "CH1_SEL_SD_RX_CLK": "DONTCARE", + "CH1_TDRV_DAT_SEL": "DONTCARE", + "CH1_TDRV_POST_EN": "DONTCARE", + "CH1_TDRV_PRE_EN": "DONTCARE", + "CH1_TDRV_SLICE0_CUR": "DONTCARE", + "CH1_TDRV_SLICE0_SEL": "DONTCARE", + "CH1_TDRV_SLICE1_CUR": "DONTCARE", + "CH1_TDRV_SLICE1_SEL": "DONTCARE", + "CH1_TDRV_SLICE2_CUR": "DONTCARE", + "CH1_TDRV_SLICE2_SEL": "DONTCARE", + "CH1_TDRV_SLICE3_CUR": "DONTCARE", + "CH1_TDRV_SLICE3_SEL": "DONTCARE", + "CH1_TDRV_SLICE4_CUR": "DONTCARE", + "CH1_TDRV_SLICE4_SEL": "DONTCARE", + "CH1_TDRV_SLICE5_CUR": "DONTCARE", + "CH1_TDRV_SLICE5_SEL": "DONTCARE", + "CH1_TPWDNB": "DONTCARE", + "CH1_TXAMPLITUDE": "DONTCARE", + "CH1_TXDEPOST": "DONTCARE", + "CH1_TXDEPRE": "DONTCARE", + "CH1_TX_CM_SEL": "DONTCARE", + "CH1_TX_DIV11_SEL": "DONTCARE", + "CH1_TX_GEAR_BYPASS": "DONTCARE", + "CH1_TX_GEAR_MODE": "DONTCARE", + "CH1_TX_POST_SIGN": "DONTCARE", + "CH1_TX_PRE_SIGN": "DONTCARE", + "CH1_UC_MODE": "DONTCARE", + "CH1_UDF_COMMA_A": "DONTCARE", + "CH1_UDF_COMMA_B": "DONTCARE", + "CH1_UDF_COMMA_MASK": "DONTCARE", + "CH1_WA_BYPASS": "DONTCARE", + "CH1_WA_MODE": "DONTCARE", + "D_BITCLK_FROM_ND_EN": "DONTCARE", + "D_BITCLK_LOCAL_EN": "DONTCARE", + "D_BITCLK_ND_EN": "DONTCARE", + "D_BUS8BIT_SEL": "DONTCARE", + "D_CDR_LOL_SET": "DONTCARE", + "D_CMUSETBIASI": "DONTCARE", + "D_CMUSETI4CPP": "DONTCARE", + "D_CMUSETI4CPZ": "DONTCARE", + "D_CMUSETI4VCO": "DONTCARE", + "D_CMUSETICP4P": "DONTCARE", + "D_CMUSETICP4Z": "DONTCARE", + "D_CMUSETINITVCT": "DONTCARE", + "D_CMUSETISCL4VCO": "DONTCARE", + "D_CMUSETP1GM": "DONTCARE", + "D_CMUSETP2AGM": "DONTCARE", + "D_CMUSETZGM": "DONTCARE", + "D_DCO_CALIB_TIME_SEL": "DONTCARE", + "D_HIGH_MARK": "DONTCARE", + "D_IB_PWDNB": "DONTCARE", + "D_ISETLOS": "DONTCARE", + "D_LOW_MARK": "DONTCARE", + "D_MACROPDB": "DONTCARE", + "D_PD_ISET": "DONTCARE", + "D_PLL_LOL_SET": "DONTCARE", + "D_REFCK_MODE": "DONTCARE", + "D_REQ_ISET": "DONTCARE", + "D_RG_EN": "DONTCARE", + "D_RG_SET": "DONTCARE", + "D_SETICONST_AUX": "DONTCARE", + "D_SETICONST_CH": "DONTCARE", + "D_SETIRPOLY_AUX": "DONTCARE", + "D_SETIRPOLY_CH": "DONTCARE", + "D_SETPLLRC": "DONTCARE", + "D_SYNC_LOCAL_EN": "DONTCARE", + "D_SYNC_ND_EN": "DONTCARE", + "D_TXPLL_PWDNB": "DONTCARE", + "D_TX_MAX_RATE": "DONTCARE", + "D_TX_VCO_CK_DIV": "DONTCARE", + "D_XGE_MODE": "DONTCARE" + }, + "ports": { + "CH0_HDINP": { + "direction": "input", + "bits": [ 2 ] + }, + "CH1_HDINP": { + "direction": "input", + "bits": [ 3 ] + }, + "CH0_HDINN": { + "direction": "input", + "bits": [ 4 ] + }, + "CH1_HDINN": { + "direction": "input", + "bits": [ 5 ] + }, + "D_TXBIT_CLKP_FROM_ND": { + "direction": "input", + "bits": [ 6 ] + }, + "D_TXBIT_CLKN_FROM_ND": { + "direction": "input", + "bits": [ 7 ] + }, + "D_SYNC_ND": { + "direction": "input", + "bits": [ 8 ] + }, + "D_TXPLL_LOL_FROM_ND": { + "direction": "input", + "bits": [ 9 ] + }, + "CH0_RX_REFCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "CH1_RX_REFCLK": { + "direction": "input", + "bits": [ 11 ] + }, + "CH0_FF_RXI_CLK": { + "direction": "input", + "bits": [ 12 ] + }, + "CH1_FF_RXI_CLK": { + "direction": "input", + "bits": [ 13 ] + }, + "CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 86 ] + }, + "CH1_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 87 ] + }, + "CH0_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 88 ] + }, + "CH1_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 89 ] + }, + "CH0_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 90 ] + }, + "CH1_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 91 ] + }, + "CH0_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 92 ] + }, + "CH1_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 93 ] + }, + "CH0_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 94 ] + }, + "CH1_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 95 ] + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 96 ] + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 97 ] + }, + "CH0_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 98 ] + }, + "CH1_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 99 ] + }, + "CH0_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 100 ] + }, + "CH1_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 101 ] + }, + "CH0_FFC_RRST": { + "direction": "input", + "bits": [ 102 ] + }, + "CH1_FFC_RRST": { + "direction": "input", + "bits": [ 103 ] + }, + "CH0_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 104 ] + }, + "CH1_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 105 ] + }, + "CH0_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 106 ] + }, + "CH1_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 107 ] + }, + "CH0_LDR_CORE2TX": { + "direction": "input", + "bits": [ 108 ] + }, + "CH1_LDR_CORE2TX": { + "direction": "input", + "bits": [ 109 ] + }, + "D_SCIWDATA0": { + "direction": "input", + "bits": [ 110 ] + }, + "D_SCIWDATA1": { + "direction": "input", + "bits": [ 111 ] + }, + "D_SCIWDATA2": { + "direction": "input", + "bits": [ 112 ] + }, + "D_SCIWDATA3": { + "direction": "input", + "bits": [ 113 ] + }, + "D_SCIWDATA4": { + "direction": "input", + "bits": [ 114 ] + }, + "D_SCIWDATA5": { + "direction": "input", + "bits": [ 115 ] + }, + "D_SCIWDATA6": { + "direction": "input", + "bits": [ 116 ] + }, + "D_SCIWDATA7": { + "direction": "input", + "bits": [ 117 ] + }, + "D_SCIADDR0": { + "direction": "input", + "bits": [ 118 ] + }, + "D_SCIADDR1": { + "direction": "input", + "bits": [ 119 ] + }, + "D_SCIADDR2": { + "direction": "input", + "bits": [ 120 ] + }, + "D_SCIADDR3": { + "direction": "input", + "bits": [ 121 ] + }, + "D_SCIADDR4": { + "direction": "input", + "bits": [ 122 ] + }, + "D_SCIADDR5": { + "direction": "input", + "bits": [ 123 ] + }, + "D_SCIENAUX": { + "direction": "input", + "bits": [ 124 ] + }, + "D_SCISELAUX": { + "direction": "input", + "bits": [ 125 ] + }, + "CH0_SCIEN": { + "direction": "input", + "bits": [ 126 ] + }, + "CH1_SCIEN": { + "direction": "input", + "bits": [ 127 ] + }, + "CH0_SCISEL": { + "direction": "input", + "bits": [ 128 ] + }, + "CH1_SCISEL": { + "direction": "input", + "bits": [ 129 ] + }, + "D_SCIRD": { + "direction": "input", + "bits": [ 130 ] + }, + "D_SCIWSTN": { + "direction": "input", + "bits": [ 131 ] + }, + "D_CYAWSTN": { + "direction": "input", + "bits": [ 132 ] + }, + "D_FFC_SYNC_TOGGLE": { + "direction": "input", + "bits": [ 133 ] + }, + "D_FFC_DUAL_RST": { + "direction": "input", + "bits": [ 134 ] + }, + "D_FFC_MACRO_RST": { + "direction": "input", + "bits": [ 135 ] + }, + "D_FFC_MACROPDB": { + "direction": "input", + "bits": [ 136 ] + }, + "D_FFC_TRST": { + "direction": "input", + "bits": [ 137 ] + }, + "CH0_FFC_CDR_EN_BITSLIP": { + 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"mem.0.0_DOB2_TRELLIS_FF_Q_DI_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24" + } + }, + "mem.0.0_DOB2_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.18-133.20" + } + }, + "mem.0.0_DOB3": { + "hide_name": 0, + "bits": [ 81, 111, 107 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.0_DOB4": { + "hide_name": 0, + "bits": [ 112, 82, 107 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.0_DOB5": { + "hide_name": 0, + "bits": [ 113, 83, 107 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.0_DOB6": { + "hide_name": 0, + "bits": [ 114, 84, 107 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.0_DOB7": { + "hide_name": 0, + "bits": [ 115, 85, 107 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.0_DOB8": { + "hide_name": 0, + "bits": [ 70, 71, 80, 81, 82, 83, 84, 85, 86 ], + "attributes": { + "unused_bits": "8" + } + }, + "mem.0.0_DOB9": { + "hide_name": 0, + "bits": [ 70, 71, 80, 81, 82, 83, 84, 85, 86, 87, 72, 73, 74, 75, 76, 77, 78, 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v:46.13-46.16", + "unused_bits": "8 9 10 11 12 13 14 15 16 17" + } + }, + "rd_addr": { + "hide_name": 0, + "bits": [ 20, 21, 22, 23, 24, 25, 26, 27 ], + "attributes": { + "src": "hardware/v2/rtl/activation_buffer.v:32.41-32.48" + } + }, + "rd_data": { + "hide_name": 0, + "bits": [ 28, 29, 30, 31, 32, 33, 34, 35 ], + "signed": 1, + "attributes": { + "src": "hardware/v2/rtl/activation_buffer.v:33.41-33.48" + } + }, + "wr_addr": { + "hide_name": 0, + "bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ], + "attributes": { + "src": "hardware/v2/rtl/activation_buffer.v:29.41-29.48" + } + }, + "wr_data": { + "hide_name": 0, + "bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ], + "signed": 1, + "attributes": { + "src": "hardware/v2/rtl/activation_buffer.v:30.41-30.48" + } + }, + "wr_en": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "hardware/v2/rtl/activation_buffer.v:28.41-28.46" + } + }, + "wr_en_TRELLIS_FF_DI_Q": { + "hide_name": 0, + "bits": [ 26, 24, 43, 41, 88, 93 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + } + } + } + } +} diff --git a/hardware/v2/synthesis/activation_buffer_d256/yosys.log b/hardware/v2/synthesis/activation_buffer_d256/yosys.log new file mode 100644 index 0000000..7add178 --- /dev/null +++ b/hardware/v2/synthesis/activation_buffer_d256/yosys.log @@ -0,0 +1,1162 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) + +-- Running command ` + read_verilog hardware/v2/rtl/activation_buffer.v + chparam -set DEPTH 256 activation_buffer + synth_ecp5 -json hardware/v2/synthesis/activation_buffer_d256/top.json -top activation_buffer +' -- + +1. Executing Verilog-2005 frontend: hardware/v2/rtl/activation_buffer.v +Parsing Verilog input from `hardware/v2/rtl/activation_buffer.v' to AST representation. +Generating RTLIL representation for module `\activation_buffer'. +Successfully finished Verilog frontend. +Parameter \DEPTH = 256 + +2. Executing AST frontend in derive mode using pre-parsed AST for module `\activation_buffer'. +Parameter \DEPTH = 256 +Generating RTLIL representation for module `$paramod\activation_buffer\DEPTH=s32'00000000000000000000000100000000'. + +3. Executing SYNTH_LATTICE pass. + +3.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +3.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +3.3. Executing HIERARCHY pass (managing design hierarchy). + +3.3.1. Analyzing design hierarchy.. +Top module: \activation_buffer + +3.3.2. Analyzing design hierarchy.. +Top module: \activation_buffer +Removed 0 unused modules. + +3.4. Executing PROC pass (convert processes to netlists). + +3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/activation_buffer.v:38$12 in module activation_buffer. +Removed a total of 0 dead cases. + +3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 4 assignments to connections. + +3.4.4. Executing PROC_INIT pass (extract init attributes). + +3.4.5. Executing PROC_ARST pass (detect async resets in processes). + +3.4.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$12'. + 1/3: $1$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$18 + 2/3: $1$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_DATA[7:0]$17 + 3/3: $1$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_ADDR[7:0]$16 +Creating decoders for process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:43$19'. + +3.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +3.4.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\activation_buffer.$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_ADDR' using process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$12'. + created $dff cell `$procdff$255' with positive edge clock. +Creating register for signal `\activation_buffer.$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_DATA' using process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$12'. + created $dff cell `$procdff$256' with positive edge clock. +Creating register for signal `\activation_buffer.$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN' using process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$12'. + created $dff cell `$procdff$257' with positive edge clock. +Creating register for signal `\activation_buffer.\rd_data' using process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:43$19'. + created $dff cell `$procdff$258' with positive edge clock. + +3.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$12'. +Removing empty process `activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$12'. +Removing empty process `activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:43$19'. +Cleaned up 1 empty switch. + +3.4.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.5. Executing CHECK pass (checking for obvious problems). +Checking module activation_buffer... +Found and reported 0 problems. + +3.6. Executing FLATTEN pass (flatten design). + +3.7. Executing TRIBUF pass. + +3.8. Executing DEMINOUT pass (demote inout ports to input or output). + +3.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. +Removed 3 unused cells and 13 unused wires. + + +3.11. Executing CHECK pass (checking for obvious problems). +Checking module activation_buffer... +Found and reported 0 problems. + +3.12. Executing OPT pass (performing simple optimizations). + +3.12.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.12.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \activation_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \activation_buffer. + Consolidated identical input bits for $mux cell $procmux$247: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] + New connections: $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [7:1] = { $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] } + Optimizing cells in module \activation_buffer. +Performed a total of 1 changes. + +3.12.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.12.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +3.12.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.12.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \activation_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \activation_buffer. +Performed a total of 0 changes. + +3.12.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.12.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +3.12.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.12.16. Finished fast OPT passes. (There is nothing left to do.) + +3.13. Executing FSM pass (extract and optimize FSM). + +3.13.1. Executing FSM_DETECT pass (finding FSMs in design). + +3.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +3.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +3.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +3.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +3.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +3.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +3.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +3.14. Executing OPT pass (performing simple optimizations). + +3.14.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.14.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \activation_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \activation_buffer. +Performed a total of 0 changes. + +3.14.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.14.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +3.14.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.14.9. Finished fast OPT passes. (There is nothing left to do.) + +3.15. Executing WREDUCE pass (reducing word size of cells). + +3.16. Executing PEEPOPT pass (run peephole optimizers). + +3.17. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +3.18. Executing SHARE pass (SAT-based resource sharing). + +3.19. Executing TECHMAP pass (map to technology primitives). + +3.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +3.19.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.20. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +3.22. Executing TECHMAP pass (map to technology primitives). + +3.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +3.22.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.23. Executing TECHMAP pass (map to technology primitives). + +3.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +3.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.24. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module activation_buffer: + created 0 $alu and 0 $macc cells. + +3.25. Executing OPT pass (performing simple optimizations). + +3.25.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.25.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \activation_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \activation_buffer. +Performed a total of 0 changes. + +3.25.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.25.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +3.25.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.25.9. Finished fast OPT passes. (There is nothing left to do.) + +3.26. Executing MEMORY pass. + +3.26.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +3.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +3.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing activation_buffer.mem write port 0. + +3.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +3.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\mem'[0] in module `\activation_buffer': merging output FF to cell. + Write port 0: non-transparent. + +3.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. +Removed 1 unused cells and 9 unused wires. + + +3.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +3.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +3.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +3.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +3.27. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +3.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). +mapping memory activation_buffer.mem via $__DP16KD_ + + +3.29. Executing TECHMAP pass (map to technology primitives). + +3.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +3.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +3.29.3. Continuing TECHMAP pass. +Using template $paramod$eed5c07ccc20b30fea5f07adc53d361b0ef0f8bc$__DP16KD_ for cells of type $__DP16KD_. +No more expansions possible. + + +3.30. Executing OPT pass (performing simple optimizations). + +3.30.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + + +3.30.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 9 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.30.3. Executing OPT_DFF pass (perform DFF optimizations). +Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$277 ($dffe) from module activation_buffer. + +3.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. +Removed 0 unused cells and 26 unused wires. + + +3.30.5. Rerunning OPT passes. (Removed registers in this run.) + +3.30.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.30.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 9 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.30.8. Executing OPT_DFF pass (perform DFF optimizations). + +3.30.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +3.30.10. Finished fast OPT passes. + +3.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +3.32. Executing OPT pass (performing simple optimizations). + +3.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 9 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \activation_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \activation_buffer. +Performed a total of 0 changes. + +3.32.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 9 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.32.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +3.32.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.32.9. Finished fast OPT passes. (There is nothing left to do.) + +3.33. Executing TECHMAP pass (map to technology primitives). + +3.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +3.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +3.33.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $eq. +No more expansions possible. + + +3.34. Executing OPT pass (performing simple optimizations). + +3.34.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.34.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 52 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.34.3. Executing OPT_DFF pass (perform DFF optimizations). + +3.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. +Removed 0 unused cells and 1 unused wires. + + +3.34.5. Finished fast OPT passes. + +3.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +3.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +3.37. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 52 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +3.38. Executing TECHMAP pass (map to technology primitives). + +3.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +3.38.2. Continuing TECHMAP pass. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +No more expansions possible. + + +3.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +3.40. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +3.41. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in activation_buffer. + +3.42. Executing ATTRMVCP pass (move or copy attributes). + +3.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. +Removed 0 unused cells and 104 unused wires. + + +3.44. Executing CHECK pass (checking for obvious problems). +Checking module activation_buffer... +Found and reported 0 problems. + +3.45. Executing TECHMAP pass (map to technology primitives). + +3.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +3.45.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.46. Executing ABC9 pass. + +3.46.1. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.2. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module activation_buffer. +Found 0 SCCs. + +3.46.4. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.5. Executing TECHMAP pass (map to technology primitives). + +3.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +3.46.5.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.46.6. Executing OPT pass (performing simple optimizations). + +3.46.6.1. Executing OPT_EXPR pass (perform const folding). + +3.46.6.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +3.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +3.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +3.46.6.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +3.46.6.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +3.46.6.8. Executing OPT_EXPR pass (perform const folding). + +3.46.6.9. Finished fast OPT passes. (There is nothing left to do.) + +3.46.7. Executing TECHMAP pass (map to technology primitives). + +3.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +3.46.7.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3.46.9. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.10. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +3.46.12. Executing AIGMAP pass (map logic to AIG). +Module activation_buffer: replaced 23 cells with 140 new cells, skipped 29 cells. + replaced 3 cell types: + 8 $_MUX_ + 7 $_OR_ + 8 $_XOR_ + not replaced 4 cell types: + 1 $_AND_ + 1 $_NOT_ + 26 TRELLIS_FF + 1 DP16KD + +3.46.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.12.2. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.12.3. Executing XAIGER backend. + +Extracted 56 AND gates and 204 wires from module `activation_buffer' to a netlist network with 60 inputs and 26 outputs. + +3.46.12.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +3.46.12.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 60/ 26 and = 56 lev = 6 (0.85) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 60/ 26 and = 119 lev = 6 (0.85) mem = 0.00 MB ch = 13 box = 0 bb = 0 +ABC: cst = 0 cls = 12 lit = 13 unused = 154 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 119. Ch = 12. Total mem = 0.03 MB. Peak cut mem = 0.02 MB. +ABC: P: Del = 1612.00. Ar = 33.0. Edge = 58. Cut = 648. T = 0.00 sec +ABC: P: Del = 1612.00. Ar = 33.0. Edge = 58. Cut = 634. T = 0.00 sec +ABC: P: Del = 1612.00. Ar = 27.0. Edge = 59. Cut = 849. T = 0.00 sec +ABC: F: Del = 1581.00. Ar = 21.0. Edge = 58. Cut = 756. T = 0.00 sec +ABC: A: Del = 1581.00. Ar = 21.0. Edge = 58. Cut = 729. T = 0.00 sec +ABC: A: Del = 1581.00. Ar = 21.0. Edge = 58. Cut = 725. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: Timing manager is given but there is no GIA of boxes. +ABC: Error: Abc_FrameUpdateGia(): Transformation has failed. +ABC: + &ps -l +ABC: /input : i/o = 60/ 26 and = 56 lev = 6 (0.85) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=6) : lut = 16 edge = 58 lev = 3 (0.42) mem = 0.00 MB +ABC: LUT = 16 : 2=1 6.2 % 3=8 50.0 % 4=4 25.0 % 5=2 12.5 % 6=1 6.2 % Ave = 3.62 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.01 sec +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +3.46.12.6. Executing AIGER frontend. + +Removed 89 unused cells and 158 unused wires. + +3.46.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 16 +ABC RESULTS: input signals: 8 +ABC RESULTS: output signals: 5 + +Removing temp directory. + +3.46.13. Executing TECHMAP pass (map to technology primitives). + +3.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +3.46.13.2. Continuing TECHMAP pass. +No more expansions possible. + +Removed 8 unused cells and 233 unused wires. + +3.47. Executing TECHMAP pass (map to technology primitives). + +3.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +3.47.2. Continuing TECHMAP pass. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. +Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut. +Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$977bf81c91b9e0cdfe901822d1642d278c1b0ecd$lut for cells of type $lut. +Using template $paramod$8614da24b3846fe751594d00fba789cfcb7b874c$lut for cells of type $lut. +Using template $paramod$adb3580ae7f1e000bff662054d4f52a48cec1e58$lut for cells of type $lut. +Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. +No more expansions possible. + + +3.48. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in activation_buffer. + Optimizing lut $abc$1022$lut$aiger1021$70.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$1022$lut$aiger1021$70.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$1022$lut$aiger1021$88.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$1022$lut$aiger1021$70.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$1022$lut$aiger$o2.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) +Removed 0 unused cells and 37 unused wires. + +3.49. Executing AUTONAME pass. +Renamed 89 objects in module activation_buffer. + + +3.50. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `activation_buffer'. Setting top module to activation_buffer. + +3.50.1. Analyzing design hierarchy.. +Top module: \activation_buffer + +3.50.2. Analyzing design hierarchy.. +Top module: \activation_buffer +Removed 0 unused modules. + +3.51. Printing statistics. + +=== activation_buffer === + + +----------Local Count, excluding submodules. + | + 43 wires + 159 wire bits + 43 public wires + 159 public wire bits + 6 ports + 34 port bits + 1 cells + 1 DP16KD + 52 submodules + 1 L6MUX21 + 21 LUT4 + 4 PFUMX + 26 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + 1 activation_buffer + + +----------Count including submodules. + | + 43 wires + 159 wire bits + 43 public wires + 159 public wire bits + 6 ports + 34 port bits + - memories + - memory bits + - processes + 1 cells + 1 DP16KD + 52 submodules + 1 L6MUX21 + 21 LUT4 + 4 PFUMX + 26 TRELLIS_FF + +3.52. Executing CHECK pass (checking for obvious problems). +Checking module activation_buffer... +Found and reported 0 problems. + +3.53. Executing JSON backend. + +End of script. Logfile hash: 6a34f02f72, time: 0.30s, user: 0.27s, system: 0.01s, MEM: 28.34 MB peak +Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) +Time spent: 56% 20x read_verilog (0 sec), 24% 11x techmap (0 sec), ... diff --git a/hardware/v2/synthesis/activation_buffer_d4096/nextpnr.log b/hardware/v2/synthesis/activation_buffer_d4096/nextpnr.log new file mode 100644 index 0000000..0ec1712 --- /dev/null +++ b/hardware/v2/synthesis/activation_buffer_d4096/nextpnr.log @@ -0,0 +1,231 @@ + + +Info: Logic utilisation before packing: +Info: Total LUT4s: 37/43848 0% +Info: logic LUTs: 37/43848 0% +Info: carry LUTs: 0/43848 0% +Info: RAM LUTs: 0/ 5481 0% +Info: RAMW LUTs: 0/10962 0% + +Info: Total DFFs: 30/43848 0% + +Info: Packing IOs.. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 0 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0x79ea6f22 + +Info: Device utilisation: +Info: TRELLIS_IO: 42/ 245 17% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 2/ 108 1% +Info: MULT18X18D: 0/ 72 0% +Info: ALU54B: 0/ 36 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 160 0% +Info: SIOLOGIC: 0/ 85 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 10 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 30/ 43848 0% +Info: TRELLIS_COMB: 39/ 43848 0% +Info: TRELLIS_RAMW: 0/ 5481 0% + +Info: Placed 0 cells based on constraints. +Info: Creating initial analytic placement for 52 cells, random placement wirelen = 6761. +Info: at initial placer iter 0, wirelen = 2512 +Info: at initial placer iter 1, wirelen = 2493 +Info: at initial placer iter 2, wirelen = 2489 +Info: at initial placer iter 3, wirelen = 2489 +Info: Running main analytical placer, max placement attempts per cell = 10000. +Info: at iteration #1, type ALL: wirelen solved = 2490, spread = 2980, legal = 3609; time = 0.00s +Info: at iteration #2, type ALL: wirelen solved = 2499, spread = 2882, legal = 3446; time = 0.00s +Info: at iteration #3, type ALL: wirelen solved = 2487, spread = 2864, legal = 3310; time = 0.00s +Info: at iteration #4, type ALL: wirelen solved = 2497, spread = 2893, legal = 3455; time = 0.00s +Info: at iteration #5, type ALL: wirelen solved = 2495, spread = 2888, legal = 3449; time = 0.00s +Info: at iteration #6, type ALL: wirelen solved = 2516, spread = 2855, legal = 3121; time = 0.00s +Info: HeAP Placer Time: 0.02s +Info: of which solving equations: 0.00s +Info: of which spreading cells: 0.00s +Info: of which strict legalisation: 0.00s + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 17, wirelen = 3121 +Info: at iteration #5: temp = 0.000000, timing cost = 13, wirelen = 2026 +Info: at iteration #10: temp = 0.000000, timing cost = 11, wirelen = 1982 +Info: at iteration #15: temp = 0.000000, timing cost = 9, wirelen = 1976 +Info: at iteration #15: temp = 0.000000, timing cost = 9, wirelen = 1977 +Info: SA placement time 0.01s + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 287.77 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.73 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 10.33 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 9025, 9161) |* +Info: [ 9161, 9297) | +Info: [ 9297, 9433) | +Info: [ 9433, 9569) | +Info: [ 9569, 9705) | +Info: [ 9705, 9841) | +Info: [ 9841, 9977) | +Info: [ 9977, 10113) | +Info: [ 10113, 10249) | +Info: [ 10249, 10385) |* +Info: [ 10385, 10521) |***** +Info: [ 10521, 10657) |******** +Info: [ 10657, 10793) |************ +Info: [ 10793, 10929) |* +Info: [ 10929, 11065) |* +Info: [ 11065, 11201) | +Info: [ 11201, 11337) |* +Info: [ 11337, 11473) |***** +Info: [ 11473, 11609) |** +Info: [ 11609, 11745) |****** +Info: Checksum: 0xf7cffeae +Info: Routing globals... +Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 211 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 221 | 10 200 | 10 200 | 0| 0.10 0.10| +Info: Routing complete. +Info: Router1 time 0.10s +Info: Checksum: 0x4d69308e + +Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source mem.0.1_ADA5_TRELLIS_FF_Q_1.Q +Info: routing 0.52 0.92 Net mem.0.1_ADA5[2] (27,17) -> (29,17) +Info: Sink mem.0.1_ADA11_LUT4_D_Z_LUT4_Z_1.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 1.10 Source mem.0.1_ADA11_LUT4_D_Z_LUT4_Z_1.F +Info: routing 0.51 1.61 Net mem.0.1_ADA11_LUT4_D_Z[5] (29,17) -> (29,18) +Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.19 1.80 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.00 1.80 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1 (29,18) -> (29,18) +Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72 +Info: logic 0.18 1.98 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.55 2.53 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z[5] (29,18) -> (27,17) +Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.19 2.72 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.35 3.08 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI (27,17) -> (27,17) +Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1.M +Info: setup 0.00 3.08 Source mem.0.0_DOB0_TRELLIS_FF_Q_1.M +Info: 1.14 ns logic, 1.93 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': +Info: type curr total name +Info: source 0.00 0.00 Source rd_addr[2]$tr_io.O +Info: routing 3.38 3.38 Net rd_addr[2]$TRELLIS_IO_IN (90,14) -> (28,18) +Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 3.56 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F +Info: routing 0.00 3.56 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT (28,18) -> (28,18) +Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1 +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32 +Info: logic 0.13 3.69 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 0.00 3.69 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1 (28,18) -> (28,18) +Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40 +Info: logic 0.18 3.87 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.53 4.40 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z[2] (28,18) -> (27,17) +Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 4.58 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F +Info: routing 0.00 4.58 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT (27,17) -> (27,17) +Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1 +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32 +Info: logic 0.13 4.70 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 0.00 4.70 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1 (27,17) -> (27,17) +Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40 +Info: logic 0.18 4.88 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.35 5.23 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI (27,17) -> (27,17) +Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1.M +Info: setup 0.00 5.23 Source mem.0.0_DOB0_TRELLIS_FF_Q_1.M +Info: 0.97 ns logic, 4.26 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': +Info: type curr total name +Info: clk-to-q 4.26 4.26 Source mem.0.0.DOB2 +Info: routing 0.94 5.20 Net mem.0.0_DOB2[1] (26,10) -> (26,11) +Info: Sink rd_data_LUT4_Z_4.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v:46.13-46.16 +Info: logic 0.18 5.38 Source rd_data_LUT4_Z_4.F +Info: routing 3.77 9.15 Net rd_data[2]$TRELLIS_IO_OUT (26,11) -> (15,71) +Info: Sink rd_data[2]$tr_io.I +Info: Defined in: +Info: hardware/v2/rtl/activation_buffer.v:33.41-33.48 +Info: 4.44 ns logic, 4.71 ns routing + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 325.20 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.23 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 9.15 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 9425, 9544) |* +Info: [ 9544, 9663) | +Info: [ 9663, 9782) | +Info: [ 9782, 9901) | +Info: [ 9901, 10020) | +Info: [ 10020, 10139) | +Info: [ 10139, 10258) | +Info: [ 10258, 10377) | +Info: [ 10377, 10496) | +Info: [ 10496, 10615) | +Info: [ 10615, 10734) |*** +Info: [ 10734, 10853) |**** +Info: [ 10853, 10972) |************** +Info: [ 10972, 11091) |**** +Info: [ 11091, 11210) | +Info: [ 11210, 11329) |********* +Info: [ 11329, 11448) | +Info: [ 11448, 11567) |* +Info: [ 11567, 11686) |** +Info: [ 11686, 11805) |***** + +Info: Program finished normally. diff --git a/hardware/v2/synthesis/activation_buffer_d4096/top.config b/hardware/v2/synthesis/activation_buffer_d4096/top.config new file mode 100644 index 0000000..6a94c2e --- /dev/null +++ b/hardware/v2/synthesis/activation_buffer_d4096/top.config @@ -0,0 +1,3388 @@ +.device LFE5U-45F + +.comment Part: LFE5U-45F-8CABGA381 + +.tile CIB_R10C13:CIB_EBR +arc: E3_H06E0003 W3_H06E0303 + +.tile CIB_R10C19:CIB_EBR +arc: E3_H06E0003 W3_H06E0003 + +.tile CIB_R10C1:CIB_LR_S +arc: E3_H06E0303 S3_V06N0303 + +.tile CIB_R10C25:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06N0203 + +.tile CIB_R10C26:CIB_EBR +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: H00L0100 V02S0301 +arc: H00R0000 V02N0601 +arc: H00R0100 V02S0701 +arc: JB5 H00R0000 +arc: JB7 V00B0000 +arc: JD4 H00R0100 +arc: JD6 H00L0100 +arc: N1_V02N0601 JQ4 +arc: S1_V02S0401 JQ6 +arc: S1_V02S0501 JQ5 +arc: V00B0000 V02N0001 +arc: V01S0000 JQ7 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JLSR1MUX 0 +enum: CIB.JCLK1MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 + +.tile CIB_R10C27:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0501 +arc: JA0 W1_H02E0701 +arc: JA1 H00R0000 +arc: JA2 S1_V02N0701 +arc: JA3 H02W0501 +arc: JA6 S1_V02N0301 +arc: JA7 H02W0701 +arc: JC0 H02W0401 +arc: JC1 H00R0100 +arc: JC2 V02N0601 +arc: JC3 V02N0401 +arc: JC6 V02N0001 +arc: JC7 V00B0100 +arc: JCLK0 G_HPBX0000 +arc: JLSR1 V00T0000 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0601 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JCE1MUX 1 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 + +.tile CIB_R10C28:CIB_EBR +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02N0501 +arc: JA0 V02N0701 +arc: JA1 H00R0000 +arc: JA2 V00T0000 +arc: JA3 V02S0701 +arc: JA4 W1_H02E0701 +arc: JA5 W1_H02E0501 +arc: JC0 V02N0401 +arc: JC1 S1_V02N0601 +arc: JC2 N1_V01S0100 +arc: JC3 S1_V02N0401 +arc: JC4 H02W0601 +arc: JC5 H02E0401 +arc: JCLK0 G_HPBX0000 +arc: JD6 V00B0000 +arc: JD7 H00R0100 +arc: N1_V02N0501 JQ7 +arc: N1_V02N0601 E1_H01W0000 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 JQ6 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V01N0101 +enum: CIB.JB7MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JLSR1MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB5MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JCE1MUX 1 + +.tile CIB_R10C29:CIB_EBR +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 H02E0201 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 JQ0 +arc: H01W0100 JQ1 +arc: JA0 H00L0000 +arc: JA1 H00L0100 +arc: JA2 W1_H02E0701 +arc: JA3 H02E0501 +arc: JA6 V00T0100 +arc: JA7 H00R0000 +arc: JB1 W1_H02E0101 +arc: JC0 H02E0401 +arc: JC1 H00R0100 +arc: JC2 W1_H02E0601 +arc: JC3 S1_V02N0401 +arc: JC6 V02N0001 +arc: JC7 E1_H01E0101 +arc: JCLK0 G_HPBX0000 +arc: JD0 W1_H02E0201 +arc: JLSR1 W1_H02E0501 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JCE1MUX 1 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 + +.tile CIB_R10C30:CIB_EBR +arc: H00R0000 W1_H02E0601 +arc: JA0 H02W0701 +arc: JA1 S1_V02N0701 +arc: JA4 E1_H01W0000 +arc: JA5 V02N0101 +arc: JA6 H00R0000 +arc: JA7 W1_H02E0701 +arc: JC0 H02E0601 +arc: JC1 H02E0401 +arc: JC4 S1_V02N0001 +arc: JC5 H02W0401 +arc: JC6 V01N0101 +arc: JC7 S1_V02N0201 +arc: JCLK0 G_HPBX0000 +arc: W1_H02W0201 S1_V02N0201 +enum: CIB.JLSR1MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JCE1MUX 1 + +.tile CIB_R10C31:CIB_EBR +arc: H01W0000 W3_H06E0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 W3_H06E0203 + +.tile CIB_R10C35:CIB_EBR +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R10C41:CIB_EBR +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R10C47:CIB_EBR +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R10C53:CIB_EBR +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R10C59:CIB_EBR +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R10C65:CIB_EBR +arc: W3_H06W0103 E3_H06W0103 + +.tile CIB_R10C71:CIB_EBR +arc: W3_H06W0103 E3_H06W0103 + +.tile CIB_R10C77:CIB_EBR +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R10C7:CIB_EBR +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R10C83:CIB_EBR +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R10C89:CIB_LR_S +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R11C1:CIB_LR +arc: E1_H01E0101 JQ5 +arc: E3_H06E0303 V06N0303 +arc: N3_V06N0303 JF5 +arc: S1_V02S0701 E3_H06W0203 + +.tile CIB_R11C89:CIB_LR +arc: JA3 W1_H02E0701 +arc: W3_H06W0303 JF5 +enum: CIB.JB3MUX 0 + +.tile CIB_R13C1:CIB_LR +arc: E3_H06E0303 JQ5 +arc: JA0 N1_V02S0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R13C89:CIB_LR +arc: W3_H06W0303 JF5 + +.tile CIB_R14C1:CIB_LR +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 JQ5 +arc: N3_V06N0303 JF5 +arc: S3_V06S0303 JF5 + +.tile CIB_R14C89:CIB_LR +arc: H01W0100 JQ5 +arc: S1_V02S0701 W3_H06E0203 +arc: W3_H06W0303 JF5 + +.tile CIB_R16C1:CIB_LR +arc: E3_H06E0303 JF5 +arc: N1_V02N0701 JQ5 +arc: N3_V06N0303 JF5 + +.tile CIB_R16C89:CIB_LR +arc: JA0 N1_V02S0701 +arc: N3_V06N0303 JQ5 +arc: S1_V02S0501 W3_H06E0303 +arc: W3_H06W0303 JQ5 +enum: CIB.JB0MUX 0 + +.tile CIB_R17C1:CIB_LR +arc: E1_H01E0101 JQ5 +arc: E3_H06E0303 V06S0303 +arc: S1_V02S0701 JF5 + +.tile CIB_R17C89:CIB_LR +arc: JA0 V02S0501 +arc: W3_H06W0303 JQ5 +enum: CIB.JB0MUX 0 + +.tile CIB_R18C1:CIB_LR +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 V01N0001 + +.tile CIB_R18C89:CIB_LR +arc: W3_H06W0103 V01N0101 + +.tile CIB_R19C1:CIB_LR +arc: E3_H06E0303 JF5 +arc: N1_V01N0001 JQ5 + +.tile CIB_R19C89:CIB_LR +arc: N1_V01N0101 JF5 +arc: W3_H06W0303 JQ5 + +.tile CIB_R1C24:CIB +arc: S3_V06S0003 JQ0 + +.tile CIB_R1C25:CIB +arc: S3_V06S0003 JQ0 +arc: S3_V06S0103 H06W0103 + +.tile CIB_R1C26:CIB +arc: S3_V06S0203 H06W0203 + +.tile CIB_R1C27:CIB +arc: S3_V06S0003 JQ0 +arc: S3_V06S0103 E1_H01W0100 + +.tile CIB_R1C28:CIB +arc: H01W0100 JQ0 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H06W0203 +arc: W3_H06W0103 E1_H01W0100 + +.tile CIB_R1C29:CIB +arc: H01W0100 JQ0 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R1C30:CIB +arc: H01W0100 JQ0 +arc: S3_V06S0103 E3_H06W0103 + +.tile CIB_R1C31:CIB +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R1C32:CIB +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R1C35:CIB +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R1C36:CIB +arc: W3_H06W0103 E3_H06W0103 + +.tile CIB_R1C37:CIB +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R1C38:CIB +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R1C40:CIB +arc: E1_H02E0501 S1_V02N0501 + +.tile CIB_R1C41:CIB +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R1C42:CIB +arc: JA0 W1_H02E0501 +arc: W3_H06W0103 E3_H06W0003 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C43:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C44:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C45:CIB +arc: JA0 S1_V02N0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C46:CIB +arc: E1_H02E0001 S1_V02N0001 + +.tile CIB_R1C47:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C48:CIB +arc: JD7 W1_H02E0001 +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C50:CIB +arc: JA0 S1_V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R20C89:CIB_LR +arc: W3_H06W0303 JQ5 + +.tile CIB_R22C13:CIB_DSP +arc: E3_H06E0103 W3_H06E0003 + +.tile CIB_R22C19:CIB_DSP +arc: E3_H06E0103 W3_H06E0103 + +.tile CIB_R22C1:CIB_LR_S +arc: E3_H06E0303 JF5 + +.tile CIB_R22C25:CIB_DSP +arc: E3_H06E0203 W3_H06E0103 + +.tile CIB_R22C27:CIB_DSP +arc: N1_V02N0001 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 + +.tile CIB_R22C29:CIB_DSP +arc: N3_V06N0303 E3_H06W0303 + +.tile CIB_R22C31:CIB_DSP +arc: N1_V02N0401 W3_H06E0203 + +.tile CIB_R22C35:CIB_DSP +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C41:CIB_DSP +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R22C47:CIB_DSP +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R22C53:CIB_DSP +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R22C59:CIB_DSP +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R22C65:CIB_DSP +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R22C71:CIB_DSP +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R22C77:CIB_DSP +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R22C7:CIB_DSP +arc: E3_H06E0003 W3_H06E0303 + +.tile CIB_R22C83:CIB_DSP +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R22C89:CIB_LR_S +arc: W3_H06W0303 JQ5 + +.tile CIB_R34C27:CIB_EBR +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile CIB_R46C27:CIB_DSP +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile CIB_R58C27:CIB_EBR +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile CIB_R5C1:CIB_PLL1 +arc: E3_H06E0303 S3_V06N0303 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C89:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C15:CIB +arc: E3_H06E0003 JQ0 + +.tile CIB_R70C16:CIB +arc: JA0 N1_V02S0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R70C18:CIB +arc: E3_H06E0003 JQ0 + +.tile CIB_R70C21:CIB +arc: E3_H06E0103 W3_H06E0003 + +.tile CIB_R70C24:CIB +arc: E3_H06E0003 W3_H06E0003 + +.tile CIB_R70C27:CIB +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 + +.tile CIB_R70C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C42:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C43:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C44:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C45:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C46:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C47:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C48:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C49:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C50:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C51:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C52:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C53:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C69:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C70:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C71:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C72:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C73:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C74:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C75:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C76:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C77:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C78:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C79:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile CIB_R70C80:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C87:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile MIB_R0C24:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C25:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C27:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C28:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C29:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C30:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C40:TMID_0 +arc: G_TDCC0CLKI G_JTRQPCLKCIB1 + +.tile MIB_R0C42:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C43:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C44:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C45:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C47:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C48:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C50:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C87:BANKREF1 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C0:BANKREF7 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C30:EBR_SPINE_UL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C40:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_VPFS0000 + +.tile MIB_R10C41:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_VPFS0000 + +.tile MIB_R10C90:BANKREF2 +enum: BANK.VCCIO 3V3 + +.tile MIB_R11C0:PICL0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R11C90:PICR0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R12C0:PICL1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R12C90:PICR1 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R13C0:PICL2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R13C90:PICR2 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R14C0:PICL0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R14C90:PICR0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R15C0:PICL1_DQS0 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON + +.tile MIB_R15C90:PICR1_DQS0 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R16C0:PICL2_DQS1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R16C90:PICR2_DQS1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R17C0:PICL0_DQS2 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R17C90:PICR0_DQS2 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R18C0:PICL1_DQS3 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON + +.tile MIB_R18C90:PICR1_DQS3 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R19C0:PICL2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R19C90:PICR2 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C24:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C25:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C27:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C28:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C29:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C30:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C42:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C43:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C44:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C45:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C47:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C48:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C50:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R20C90:PICR0 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R21C0:PICL1 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON + +.tile MIB_R21C90:PICR1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R22C0:MIB_CIB_LR +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R22C90:MIB_CIB_LR_A +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R58C40:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_VPFS0000 + +.tile MIB_R58C41:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_VPFS0000 + +.tile MIB_R71C15:PICB0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R71C16:PICB1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R71C18:SPICB0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R71C3:BANKREF8 +enum: BANK.VCCIO 3V3 + +.tile MIB_R71C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile R11C13:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R11C14:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: S3_V06S0303 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 + +.tile R11C19:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R11C20:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R11C25:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0103 + +.tile R11C26:PLC2 +arc: E1_H02E0501 V02S0501 +arc: H00L0100 N1_V02S0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: V00T0000 V02S0401 +arc: B3 H01W0100 +arc: B7 V00T0000 +arc: C3 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D3 N1_V01S0000 +arc: D7 H00R0100 +arc: E1_H02E0401 Q6 +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0100 Q1 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M6 H02E0401 +arc: M7 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0601 Q6 +arc: V01S0100 Q2 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F7 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1111110000001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R11C27:PLC2 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: A3 H02E0501 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D3 V01S0100 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: H00R0100 Q5 +arc: M5 H00R0000 +arc: MUXCLK2 CLK0 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R11C28:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 H06E0203 +arc: S3_V06S0203 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0601 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: M7 H00R0100 +arc: MUXCLK3 CLK0 +arc: N1_V02N0501 Q7 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C29:PLC2 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 + +.tile R11C2:PLC2 +arc: E3_H06E0303 H01E0101 + +.tile R11C30:PLC2 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 + +.tile R11C31:PLC2 +arc: N1_V02N0401 W3_H06E0203 + +.tile R11C33:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R11C35:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R11C39:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R11C41:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C45:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R11C47:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C51:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R11C53:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C57:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R11C59:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C63:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R11C65:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C69:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R11C71:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C75:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R11C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: W3_H06W0203 E1_H01W0000 + +.tile R11C81:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R11C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R11C87:PLC2 +arc: E1_H02E0701 W3_H06E0203 + +.tile R11C8:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 + +.tile R12C25:PLC2 +arc: E1_H02E0701 S1_V02N0701 + +.tile R12C27:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 + +.tile R12C28:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: W1_H02W0301 S1_V02N0301 + +.tile R12C29:PLC2 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 + +.tile R12C30:PLC2 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0701 H06E0203 + +.tile R13C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R13C19:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R13C25:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 + +.tile R13C26:PLC2 +arc: N3_V06N0303 H01E0101 + +.tile R13C27:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 + +.tile R13C28:PLC2 +arc: N1_V02N0701 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 + +.tile R13C29:PLC2 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V01S0000 N3_V06S0103 + +.tile R13C30:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R13C35:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R13C41:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R13C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R13C53:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R13C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R13C65:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R13C71:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R13C77:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R13C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R13C83:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R14C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R14C15:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R14C19:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R14C21:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R14C25:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 + +.tile R14C27:PLC2 +arc: E1_H02E0601 W3_H06E0303 + +.tile R14C28:PLC2 +arc: N1_V02N0301 E3_H06W0003 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: A6 V00T0100 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D6 S1_V02N0601 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R14C29:PLC2 +arc: N1_V02N0401 E3_H06W0203 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0003 N1_V01S0000 + +.tile R14C34:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R14C35:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R14C3:PLC2 +arc: E3_H06E0203 W1_H02E0701 + +.tile R14C40:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R14C41:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R14C46:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R14C47:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R14C52:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R14C53:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R14C58:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile R14C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R14C64:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 + +.tile R14C65:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R14C70:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0003 + +.tile R14C71:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R14C76:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 + +.tile R14C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R14C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R14C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: W3_H06W0303 E3_H06W0303 + +.tile R14C83:PLC2 +arc: E3_H06E0203 H01E0001 +arc: W3_H06W0003 E3_H06W0303 + +.tile R14C88:PLC2 +arc: W3_H06W0303 E1_H01W0100 + +.tile R14C9:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R15C27:PLC2 +arc: N3_V06N0103 S1_V02N0101 + +.tile R15C28:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N3_V06N0303 S1_V02N0501 + +.tile R16C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R16C19:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R16C25:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R16C27:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: N3_V06N0103 E1_H01W0100 + +.tile R16C28:PLC2 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: V01S0000 N3_V06S0103 +arc: A0 H00L0100 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: H00L0100 Q3 +arc: H00R0100 Q7 +arc: H01W0100 Q7 +arc: M3 H00R0100 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C29:PLC2 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0701 E3_H06W0203 + +.tile R16C34:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R16C35:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R16C40:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R16C41:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R16C46:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R16C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R16C52:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R16C53:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R16C58:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R16C59:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R16C64:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R16C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R16C70:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R16C71:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R16C76:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R16C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R16C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R16C82:PLC2 +arc: E1_H01E0101 W3_H06E0203 + +.tile R16C83:PLC2 +arc: E3_H06E0303 H01E0101 +arc: W3_H06W0003 E3_H06W0303 + +.tile R17C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R17C14:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0303 + +.tile R17C19:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R17C20:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R17C25:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R17C26:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: N3_V06N0103 E1_H01W0100 + +.tile R17C27:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: A1 H02W0701 +arc: A4 H02W0501 +arc: B1 V01N0001 +arc: B4 H02W0301 +arc: C1 F4 +arc: C4 E1_H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D4 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q4 +arc: E1_H02E0401 Q4 +arc: E3_H06E0203 Q4 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q5 +arc: M0 E1_H02W0601 +arc: M1 E1_H02W0001 +arc: M2 E1_H02W0601 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N3_V06N0303 Q5 +arc: S1_V02S0501 F7 +arc: V00B0000 Q4 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0100000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C28:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: W1_H02W0501 V06S0303 +arc: A1 H02W0501 +arc: A6 N1_V01N0101 +arc: B1 Q1 +arc: B5 S1_V02N0701 +arc: B6 V02S0701 +arc: C1 V02S0601 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0201 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q4 +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: S1_V02S0401 Q4 +arc: V00B0000 F6 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 0011001100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1010001011110011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C29:PLC2 +arc: H00R0100 H02E0701 +arc: S1_V02S0401 E3_H06W0203 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V01S0100 +arc: A3 V00T0000 +arc: B3 H00R0100 +arc: C3 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D3 V01S0100 +arc: F3 F3_SLICE +arc: H01W0100 Q0 +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +arc: N3_V06N0003 Q0 +arc: S1_V02S0301 F3 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 1111010100110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C2:PLC2 +arc: E3_H06E0103 H01E0101 + +.tile R17C30:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R17C35:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R17C41:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R17C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R17C53:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R17C59:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R17C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R17C71:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R17C77:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R17C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R17C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R17C8:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R18C13:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R18C15:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R18C19:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R18C21:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R18C25:PLC2 +arc: E1_H02E0401 W3_H06E0203 + +.tile R18C27:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 E1_H01W0000 +arc: A3 V02N0701 +arc: B3 Q3 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D3 H00R0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M5 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F1 +arc: N3_V06N0003 Q3 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V00B0100 Q5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R18C28:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0000 S1_V02N0601 +arc: V00B0100 V02N0301 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A7 S1_V02N0301 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B7 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C4 Q4 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q6 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0000 F1 +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 H02E0401 +arc: M6 V00B0100 +arc: M7 H02W0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 Q4 +arc: N1_V02N0701 Q7 +arc: N3_V06N0003 Q3 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: V00B0000 Q6 +arc: V00T0100 Q3 +arc: V01S0000 Q7 +arc: V01S0100 Q3 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 0000110000001100 +word: SLICEA.K0.INIT 0000100000000010 +word: SLICEA.K1.INIT 1000100000100010 +word: SLICEB.K0.INIT 0000110000000011 +word: SLICEB.K1.INIT 1100110000110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C29:PLC2 +arc: H00L0100 V02S0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E3_H06W0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H02E0501 +arc: B0 S1_V02N0301 +arc: C0 V02N0401 +arc: D0 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H01E0001 +arc: M1 H00L0100 +arc: M2 H02E0601 +arc: M3 H00R0100 +arc: M4 H02E0401 +arc: M5 H00L0100 +arc: M6 H02E0401 +arc: N1_V01N0001 F3 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R18C35:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R18C3:PLC2 +arc: E3_H06E0203 W1_H02E0701 + +.tile R18C41:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R18C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R18C53:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R18C59:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R18C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R18C71:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R18C77:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R18C7:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R18C83:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R18C9:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R19C13:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R19C19:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R19C25:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0701 N3_V06S0203 + +.tile R19C27:PLC2 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 W1_H02E0701 + +.tile R19C28:PLC2 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 + +.tile R19C29:PLC2 +arc: N1_V01N0001 N3_V06S0003 +arc: W1_H02W0301 E3_H06W0003 +arc: CLK0 G_HPBX0000 +arc: M6 E1_H02W0401 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 Q6 +arc: N3_V06N0303 Q6 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C30:PLC2 +arc: W1_H02W0601 N3_V06S0303 + +.tile R19C31:PLC2 +arc: W1_H02W0401 V02N0401 + +.tile R19C35:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R19C41:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R19C47:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R19C53:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R19C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R19C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R19C71:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R19C77:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R19C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R19C83:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R20C27:PLC2 +arc: N1_V02N0001 S1_V02N0001 + +.tile R20C28:PLC2 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N3_V06S0203 + +.tile R20C29:PLC2 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0301 N3_V06S0003 + +.tile R20C31:PLC2 +arc: N1_V02N0401 S1_V02N0401 + +.tile R20C35:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R20C41:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C47:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C53:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C59:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C65:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C71:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R23C14:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R26C39:PLC2 +word: SLICEC.K1.INIT 1111111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R28C27:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 + +.tile R28C28:PLC2 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R29C14:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R35C14:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R3C26:PLC2 +arc: E3_H06E0103 S3_V06N0103 + +.tile R3C28:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 S3_V06N0303 + +.tile R3C32:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R3C34:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 + +.tile R3C38:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R3C40:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0501 W3_H06E0303 + +.tile R3C44:PLC2 +arc: E1_H01E0101 W3_H06E0203 + +.tile R3C45:PLC2 +arc: N1_V02N0501 H01E0101 + +.tile R3C46:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0501 + +.tile R3C47:PLC2 +arc: E3_H06E0203 H01E0001 + +.tile R3C50:PLC2 +arc: N1_V02N0701 H06E0203 + +.tile R40C27:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R41C14:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R47C14:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R52C27:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R53C14:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R59C14:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R5C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R5C19:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R5C25:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R5C31:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R5C37:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R5C43:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R5C46:PLC2 +arc: N1_V02N0501 H06E0303 + +.tile R5C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R64C27:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R65C14:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R68C14:PLC2 +arc: E1_H02E0501 V06S0303 + +.tile R68C16:PLC2 +arc: S1_V02S0501 W1_H02E0501 + +.tile R7C24:PLC2 +arc: S1_V02S0001 N3_V06S0003 + +.tile R7C25:PLC2 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 + +.tile R7C26:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R7C27:PLC2 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 + +.tile R7C28:PLC2 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 + +.tile R7C29:PLC2 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 + +.tile R7C30:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R9C24:PLC2 +arc: E1_H02E0001 N1_V02S0001 + +.tile R9C25:PLC2 +arc: E1_H02E0001 N1_V02S0001 + +.tile R9C26:PLC2 +arc: H00L0000 H02E0001 +arc: B2 H01W0100 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D2 S1_V02N0201 +arc: F2 F2_SLICE +arc: H00R0100 Q7 +arc: H01W0100 Q5 +arc: M1 W1_H02E0001 +arc: M5 H00R0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 F2 +arc: S1_V02S0301 Q1 +arc: S1_V02S0701 Q7 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R9C27:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q0 +arc: M0 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V00B0100 Q5 +arc: V01S0000 Q5 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C28:PLC2 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0100 H02E0501 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: A3 V02N0501 +arc: A6 H02E0501 +arc: C3 H00L0000 +arc: C6 H01E0001 +arc: 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"CH0_TDRV_SLICE5_CUR": "DONTCARE", + "CH0_TDRV_SLICE5_SEL": "DONTCARE", + "CH0_TPWDNB": "DONTCARE", + "CH0_TXAMPLITUDE": "DONTCARE", + "CH0_TXDEPOST": "DONTCARE", + "CH0_TXDEPRE": "DONTCARE", + "CH0_TX_CM_SEL": "DONTCARE", + "CH0_TX_DIV11_SEL": "DONTCARE", + "CH0_TX_GEAR_BYPASS": "DONTCARE", + "CH0_TX_GEAR_MODE": "DONTCARE", + "CH0_TX_POST_SIGN": "DONTCARE", + "CH0_TX_PRE_SIGN": "DONTCARE", + "CH0_UC_MODE": "DONTCARE", + "CH0_UDF_COMMA_A": "DONTCARE", + "CH0_UDF_COMMA_B": "DONTCARE", + "CH0_UDF_COMMA_MASK": "DONTCARE", + "CH0_WA_BYPASS": "DONTCARE", + "CH0_WA_MODE": "DONTCARE", + "CH1_AUTO_CALIB_EN": "DONTCARE", + "CH1_AUTO_FACQ_EN": "DONTCARE", + "CH1_BAND_THRESHOLD": "DONTCARE", + "CH1_CALIB_CK_MODE": "DONTCARE", + "CH1_CC_MATCH_1": "DONTCARE", + "CH1_CC_MATCH_2": "DONTCARE", + "CH1_CC_MATCH_3": "DONTCARE", + "CH1_CC_MATCH_4": "DONTCARE", + "CH1_CDR_CNT4SEL": "DONTCARE", + "CH1_CDR_CNT8SEL": "DONTCARE", + "CH1_CDR_MAX_RATE": "DONTCARE", + "CH1_CTC_BYPASS": "DONTCARE", + "CH1_DCOATDCFG": "DONTCARE", + "CH1_DCOATDDLY": "DONTCARE", + "CH1_DCOBYPSATD": "DONTCARE", + "CH1_DCOCALDIV": "DONTCARE", + "CH1_DCOCTLGI": "DONTCARE", + "CH1_DCODISBDAVOID": "DONTCARE", + "CH1_DCOFLTDAC": "DONTCARE", + "CH1_DCOFTNRG": "DONTCARE", + "CH1_DCOIOSTUNE": "DONTCARE", + "CH1_DCOITUNE": "DONTCARE", + "CH1_DCOITUNE4LSB": "DONTCARE", + "CH1_DCOIUPDNX2": "DONTCARE", + "CH1_DCONUOFLSB": "DONTCARE", + "CH1_DCOSCALEI": "DONTCARE", + "CH1_DCOSTARTVAL": "DONTCARE", + "CH1_DCOSTEP": "DONTCARE", + "CH1_DEC_BYPASS": "DONTCARE", + "CH1_ENABLE_CG_ALIGN": "DONTCARE", + "CH1_ENC_BYPASS": "DONTCARE", + "CH1_FF_RX_F_CLK_DIS": "DONTCARE", + "CH1_FF_RX_H_CLK_EN": "DONTCARE", + "CH1_FF_TX_F_CLK_DIS": "DONTCARE", + "CH1_FF_TX_H_CLK_EN": "DONTCARE", + "CH1_GE_AN_ENABLE": "DONTCARE", + "CH1_INVERT_RX": "DONTCARE", + "CH1_INVERT_TX": "DONTCARE", + "CH1_LDR_CORE2TX_SEL": "DONTCARE", + "CH1_LDR_RX2CORE_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_TRIM": "DONTCARE", + "CH1_LSM_DISABLE": "DONTCARE", + "CH1_MATCH_2_ENABLE": "DONTCARE", + "CH1_MATCH_4_ENABLE": "DONTCARE", + "CH1_MIN_IPG_CNT": "DONTCARE", + "CH1_PCIE_EI_EN": "DONTCARE", + "CH1_PCIE_MODE": "DONTCARE", + "CH1_PCS_DET_TIME_SEL": "DONTCARE", + "CH1_PDEN_SEL": "DONTCARE", + "CH1_PRBS_ENABLE": "DONTCARE", + "CH1_PRBS_LOCK": "DONTCARE", + "CH1_PRBS_SELECTION": "DONTCARE", + "CH1_PROTOCOL": "DONTCARE", + "CH1_RATE_MODE_RX": "DONTCARE", + "CH1_RATE_MODE_TX": "DONTCARE", + "CH1_RCV_DCC_EN": "DONTCARE", + "CH1_REG_BAND_OFFSET": "DONTCARE", + "CH1_REG_BAND_SEL": "DONTCARE", + "CH1_REG_IDAC_EN": "DONTCARE", + "CH1_REG_IDAC_SEL": "DONTCARE", + "CH1_REQ_EN": "DONTCARE", + "CH1_REQ_LVL_SET": "DONTCARE", + "CH1_RIO_MODE": "DONTCARE", + "CH1_RLOS_SEL": "DONTCARE", + "CH1_RPWDNB": "DONTCARE", + "CH1_RTERM_RX": "DONTCARE", + "CH1_RTERM_TX": "DONTCARE", + "CH1_RXIN_CM": "DONTCARE", + "CH1_RXTERM_CM": "DONTCARE", + "CH1_RX_DCO_CK_DIV": "DONTCARE", + "CH1_RX_DIV11_SEL": "DONTCARE", + "CH1_RX_GEAR_BYPASS": "DONTCARE", + "CH1_RX_GEAR_MODE": "DONTCARE", + "CH1_RX_LOS_CEQ": "DONTCARE", + "CH1_RX_LOS_EN": "DONTCARE", + "CH1_RX_LOS_HYST_EN": "DONTCARE", + "CH1_RX_LOS_LVL": "DONTCARE", + "CH1_RX_RATE_SEL": "DONTCARE", + "CH1_RX_SB_BYPASS": "DONTCARE", + "CH1_SB_BYPASS": "DONTCARE", + "CH1_SEL_SD_RX_CLK": "DONTCARE", + "CH1_TDRV_DAT_SEL": "DONTCARE", + "CH1_TDRV_POST_EN": "DONTCARE", + "CH1_TDRV_PRE_EN": "DONTCARE", + "CH1_TDRV_SLICE0_CUR": "DONTCARE", + "CH1_TDRV_SLICE0_SEL": "DONTCARE", + "CH1_TDRV_SLICE1_CUR": "DONTCARE", + "CH1_TDRV_SLICE1_SEL": "DONTCARE", + "CH1_TDRV_SLICE2_CUR": "DONTCARE", + "CH1_TDRV_SLICE2_SEL": "DONTCARE", + "CH1_TDRV_SLICE3_CUR": "DONTCARE", + "CH1_TDRV_SLICE3_SEL": "DONTCARE", + "CH1_TDRV_SLICE4_CUR": "DONTCARE", + "CH1_TDRV_SLICE4_SEL": "DONTCARE", + "CH1_TDRV_SLICE5_CUR": "DONTCARE", + "CH1_TDRV_SLICE5_SEL": "DONTCARE", + "CH1_TPWDNB": "DONTCARE", + "CH1_TXAMPLITUDE": "DONTCARE", + "CH1_TXDEPOST": "DONTCARE", + "CH1_TXDEPRE": "DONTCARE", + "CH1_TX_CM_SEL": "DONTCARE", + "CH1_TX_DIV11_SEL": "DONTCARE", + "CH1_TX_GEAR_BYPASS": "DONTCARE", + "CH1_TX_GEAR_MODE": "DONTCARE", + "CH1_TX_POST_SIGN": "DONTCARE", + "CH1_TX_PRE_SIGN": "DONTCARE", + "CH1_UC_MODE": "DONTCARE", + "CH1_UDF_COMMA_A": "DONTCARE", + "CH1_UDF_COMMA_B": "DONTCARE", + "CH1_UDF_COMMA_MASK": "DONTCARE", + "CH1_WA_BYPASS": "DONTCARE", + "CH1_WA_MODE": "DONTCARE", + "D_BITCLK_FROM_ND_EN": "DONTCARE", + "D_BITCLK_LOCAL_EN": "DONTCARE", + "D_BITCLK_ND_EN": "DONTCARE", + "D_BUS8BIT_SEL": "DONTCARE", + "D_CDR_LOL_SET": "DONTCARE", + "D_CMUSETBIASI": "DONTCARE", + "D_CMUSETI4CPP": "DONTCARE", + "D_CMUSETI4CPZ": "DONTCARE", + "D_CMUSETI4VCO": "DONTCARE", + "D_CMUSETICP4P": "DONTCARE", + "D_CMUSETICP4Z": "DONTCARE", + "D_CMUSETINITVCT": "DONTCARE", + "D_CMUSETISCL4VCO": "DONTCARE", + "D_CMUSETP1GM": "DONTCARE", + "D_CMUSETP2AGM": "DONTCARE", + "D_CMUSETZGM": "DONTCARE", + "D_DCO_CALIB_TIME_SEL": "DONTCARE", + "D_HIGH_MARK": "DONTCARE", + "D_IB_PWDNB": "DONTCARE", + "D_ISETLOS": "DONTCARE", + "D_LOW_MARK": "DONTCARE", + "D_MACROPDB": "DONTCARE", + "D_PD_ISET": "DONTCARE", + "D_PLL_LOL_SET": "DONTCARE", + "D_REFCK_MODE": "DONTCARE", + "D_REQ_ISET": "DONTCARE", + "D_RG_EN": "DONTCARE", + "D_RG_SET": "DONTCARE", + "D_SETICONST_AUX": "DONTCARE", + "D_SETICONST_CH": "DONTCARE", + "D_SETIRPOLY_AUX": "DONTCARE", + "D_SETIRPOLY_CH": "DONTCARE", + "D_SETPLLRC": "DONTCARE", + "D_SYNC_LOCAL_EN": "DONTCARE", + "D_SYNC_ND_EN": "DONTCARE", + "D_TXPLL_PWDNB": "DONTCARE", + "D_TX_MAX_RATE": "DONTCARE", + "D_TX_VCO_CK_DIV": "DONTCARE", + "D_XGE_MODE": "DONTCARE" + }, + "ports": { + "CH0_HDINP": { + "direction": "input", + "bits": [ 2 ] + }, + "CH1_HDINP": { + "direction": "input", + "bits": [ 3 ] + }, + "CH0_HDINN": { + "direction": "input", + "bits": [ 4 ] + }, + "CH1_HDINN": { + "direction": "input", + "bits": [ 5 ] + }, + "D_TXBIT_CLKP_FROM_ND": { + "direction": "input", + "bits": [ 6 ] + }, + "D_TXBIT_CLKN_FROM_ND": { + "direction": "input", + "bits": [ 7 ] + }, + "D_SYNC_ND": { + "direction": "input", + "bits": [ 8 ] + }, + "D_TXPLL_LOL_FROM_ND": { + "direction": "input", + "bits": [ 9 ] + }, + "CH0_RX_REFCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "CH1_RX_REFCLK": { + "direction": "input", + "bits": [ 11 ] + }, + "CH0_FF_RXI_CLK": { + "direction": "input", + "bits": [ 12 ] + }, + "CH1_FF_RXI_CLK": { + "direction": "input", + "bits": [ 13 ] + }, + "CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 86 ] + }, + "CH1_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 87 ] + }, + "CH0_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 88 ] + }, + "CH1_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 89 ] + }, + "CH0_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 90 ] + }, + "CH1_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 91 ] + }, + "CH0_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 92 ] + }, + "CH1_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 93 ] + }, + "CH0_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 94 ] + }, + "CH1_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 95 ] + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 96 ] + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 97 ] + }, + "CH0_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 98 ] + }, + "CH1_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 99 ] + }, + "CH0_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 100 ] + }, + "CH1_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 101 ] + }, + "CH0_FFC_RRST": { + "direction": "input", + "bits": [ 102 ] + }, + "CH1_FFC_RRST": { + "direction": "input", + "bits": [ 103 ] + }, + "CH0_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 104 ] + }, + "CH1_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 105 ] + }, + "CH0_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 106 ] + }, + "CH1_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 107 ] + }, + "CH0_LDR_CORE2TX": { + "direction": "input", + "bits": [ 108 ] + }, + "CH1_LDR_CORE2TX": { + "direction": "input", + "bits": [ 109 ] + }, + "D_SCIWDATA0": { + "direction": "input", + "bits": [ 110 ] + }, + "D_SCIWDATA1": { + "direction": "input", + "bits": [ 111 ] + }, + "D_SCIWDATA2": { + "direction": "input", + "bits": [ 112 ] + }, + "D_SCIWDATA3": { + "direction": "input", + "bits": [ 113 ] + }, + "D_SCIWDATA4": { + "direction": "input", + "bits": [ 114 ] + }, + "D_SCIWDATA5": { + "direction": "input", + "bits": [ 115 ] + }, + "D_SCIWDATA6": { + "direction": "input", + "bits": [ 116 ] + }, + "D_SCIWDATA7": { + "direction": "input", + "bits": [ 117 ] + }, + "D_SCIADDR0": { + "direction": "input", + "bits": [ 118 ] + }, + "D_SCIADDR1": { + "direction": "input", + "bits": [ 119 ] + }, + "D_SCIADDR2": { + "direction": "input", + "bits": [ 120 ] + }, + "D_SCIADDR3": { + "direction": "input", + "bits": [ 121 ] + }, + "D_SCIADDR4": { + "direction": "input", + "bits": [ 122 ] + }, + "D_SCIADDR5": { + "direction": "input", + "bits": [ 123 ] + }, + "D_SCIENAUX": { + "direction": "input", + "bits": [ 124 ] + }, + "D_SCISELAUX": { + "direction": "input", + "bits": [ 125 ] + }, + "CH0_SCIEN": { + "direction": "input", + "bits": [ 126 ] + }, + "CH1_SCIEN": { + "direction": "input", + "bits": [ 127 ] + }, + "CH0_SCISEL": { + "direction": "input", + "bits": [ 128 ] + }, + "CH1_SCISEL": { + "direction": "input", + "bits": [ 129 ] + }, + "D_SCIRD": { + "direction": "input", + "bits": [ 130 ] + }, + "D_SCIWSTN": { + "direction": "input", + "bits": [ 131 ] + }, + "D_CYAWSTN": { + "direction": "input", + "bits": [ 132 ] + }, + "D_FFC_SYNC_TOGGLE": { + "direction": "input", + "bits": [ 133 ] + }, + "D_FFC_DUAL_RST": { + "direction": "input", + "bits": [ 134 ] + }, + "D_FFC_MACRO_RST": { + "direction": "input", + "bits": [ 135 ] + }, + "D_FFC_MACROPDB": { + "direction": "input", + "bits": [ 136 ] + }, + "D_FFC_TRST": { + "direction": "input", + "bits": [ 137 ] + }, + "CH0_FFC_CDR_EN_BITSLIP": { + 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"bits": [ 185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "mem.0.1_ADA11_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 34, 31, 46, 55, 168, 165, 162 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_ADA3": { + "hide_name": 0, + "bits": [ 25, 24, 49, 48 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_ADA5": { + "hide_name": 0, + "bits": [ 32, 27, 44, 51 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DIA0": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + } + }, + "mem.0.1_DIA1": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + } + }, + "mem.0.1_DIA2": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + } + }, + "mem.0.1_DIA3": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + } + }, + "mem.0.1_DOA3": { + "hide_name": 0, + "bits": [ 119, 120, 129, 130 ], + "attributes": { + "unused_bits": "0 1 2 3" + } + }, + "mem.0.1_DOA9": { + "hide_name": 0, + "bits": [ 119, 120, 129, 130, 131, 132, 133, 134, 135, 136, 121, 122, 123, 124, 125, 126, 127, 128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v:45.13-45.16", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" + } + }, + "mem.0.1_DOB0": { + "hide_name": 0, + "bits": [ 188, 137, 99 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB1": { + "hide_name": 0, + "bits": [ 138, 189, 99 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB2": { + "hide_name": 0, + "bits": [ 190, 147, 99 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB3": { + "hide_name": 0, + "bits": [ 148, 191, 99 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB9": { + "hide_name": 0, + "bits": [ 137, 138, 147, 148, 149, 150, 151, 152, 153, 154, 139, 140, 141, 142, 143, 144, 145, 146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v:46.13-46.16", + "unused_bits": "4 5 6 7 8 9 10 11 12 13 14 15 16 17" + } + }, + "rd_addr": { + "hide_name": 0, + "bits": [ 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35 ], + "attributes": { + "src": "hardware/v2/rtl/activation_buffer.v:32.41-32.48" + } + }, + "rd_data": { + "hide_name": 0, + "bits": [ 36, 37, 38, 39, 40, 41, 42, 43 ], + "signed": 1, + "attributes": { + "src": "hardware/v2/rtl/activation_buffer.v:33.41-33.48" + } + }, + "wr_addr": { + "hide_name": 0, + "bits": [ 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 ], + "attributes": { + "src": "hardware/v2/rtl/activation_buffer.v:29.41-29.48" + } + }, + "wr_addr_TRELLIS_FF_DI_Q": { + "hide_name": 0, + "bits": [ 30, 29, 26, 54, 53, 50 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "wr_data": { + "hide_name": 0, + "bits": [ 16, 17, 18, 19, 20, 21, 22, 23 ], + "signed": 1, + "attributes": { + "src": "hardware/v2/rtl/activation_buffer.v:30.41-30.48" + } + }, + "wr_en": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "hardware/v2/rtl/activation_buffer.v:28.41-28.46" + } + }, + "wr_en_TRELLIS_FF_DI_Q": { + "hide_name": 0, + "bits": [ 35, 28, 47, 52, 96, 179 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + } + } + } + } +} diff --git a/hardware/v2/synthesis/activation_buffer_d4096/yosys.log b/hardware/v2/synthesis/activation_buffer_d4096/yosys.log new file mode 100644 index 0000000..7d85439 --- /dev/null +++ b/hardware/v2/synthesis/activation_buffer_d4096/yosys.log @@ -0,0 +1,1175 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) + +-- Parsing `hardware/v2/rtl/activation_buffer.v' using frontend ` -vlog2k' -- + +1. Executing Verilog-2005 frontend: hardware/v2/rtl/activation_buffer.v +Parsing Verilog input from `hardware/v2/rtl/activation_buffer.v' to AST representation. +Storing AST representation for module `$abstract\activation_buffer'. +Successfully finished Verilog frontend. + +-- Running command `synth_ecp5 -json hardware/v2/synthesis/activation_buffer_d4096/top.json -top activation_buffer' -- + +2. Executing SYNTH_LATTICE pass. + +2.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +2.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +2.3. Executing HIERARCHY pass (managing design hierarchy). + +2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\activation_buffer'. +Generating RTLIL representation for module `\activation_buffer'. + +2.4.1. Analyzing design hierarchy.. +Top module: \activation_buffer + +2.4.2. Analyzing design hierarchy.. +Top module: \activation_buffer +Removing unused module `$abstract\activation_buffer'. +Removed 1 unused modules. + +2.5. Executing PROC pass (convert processes to netlists). + +2.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +2.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/activation_buffer.v:38$227 in module activation_buffer. +Removed a total of 0 dead cases. + +2.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 4 assignments to connections. + +2.5.4. Executing PROC_INIT pass (extract init attributes). + +2.5.5. Executing PROC_ARST pass (detect async resets in processes). + +2.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +2.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:43$234'. +Creating decoders for process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$227'. + 1/3: $1$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_EN[7:0]$233 + 2/3: $1$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_DATA[7:0]$232 + 3/3: $1$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_ADDR[11:0]$231 + +2.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +2.5.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\activation_buffer.\rd_data' using process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:43$234'. + created $dff cell `$procdff$245' with positive edge clock. +Creating register for signal `\activation_buffer.$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_ADDR' using process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$227'. + created $dff cell `$procdff$246' with positive edge clock. +Creating register for signal `\activation_buffer.$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_DATA' using process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$227'. + created $dff cell `$procdff$247' with positive edge clock. +Creating register for signal `\activation_buffer.$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_EN' using process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$227'. + created $dff cell `$procdff$248' with positive edge clock. + +2.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +2.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:43$234'. +Found and cleaned up 1 empty switch in `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$227'. +Removing empty process `activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$227'. +Cleaned up 1 empty switch. + +2.5.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.6. Executing CHECK pass (checking for obvious problems). +Checking module activation_buffer... +Found and reported 0 problems. + +2.7. Executing FLATTEN pass (flatten design). + +2.8. Executing TRIBUF pass. + +2.9. Executing DEMINOUT pass (demote inout ports to input or output). + +2.10. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.11. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. +Removed 3 unused cells and 13 unused wires. + + +2.12. Executing CHECK pass (checking for obvious problems). +Checking module activation_buffer... +Found and reported 0 problems. + +2.13. Executing OPT pass (performing simple optimizations). + +2.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \activation_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \activation_buffer. + Consolidated identical input bits for $mux cell $procmux$237: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_EN[7:0]$230 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_EN[7:0]$230 [0] + New connections: $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_EN[7:0]$230 [7:1] = { $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_EN[7:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_EN[7:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_EN[7:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_EN[7:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_EN[7:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_EN[7:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$226_EN[7:0]$230 [0] } + Optimizing cells in module \activation_buffer. +Performed a total of 1 changes. + +2.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +2.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \activation_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \activation_buffer. +Performed a total of 0 changes. + +2.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +2.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.13.16. Finished fast OPT passes. (There is nothing left to do.) + +2.14. Executing FSM pass (extract and optimize FSM). + +2.14.1. Executing FSM_DETECT pass (finding FSMs in design). + +2.14.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +2.14.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +2.14.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +2.14.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +2.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +2.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +2.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +2.15. Executing OPT pass (performing simple optimizations). + +2.15.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.15.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \activation_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \activation_buffer. +Performed a total of 0 changes. + +2.15.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.15.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +2.15.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.15.9. Finished fast OPT passes. (There is nothing left to do.) + +2.16. Executing WREDUCE pass (reducing word size of cells). + +2.17. Executing PEEPOPT pass (run peephole optimizers). + +2.18. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +2.19. Executing SHARE pass (SAT-based resource sharing). + +2.20. Executing TECHMAP pass (map to technology primitives). + +2.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +2.20.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.21. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.22. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +2.23. Executing TECHMAP pass (map to technology primitives). + +2.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +2.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.24. Executing TECHMAP pass (map to technology primitives). + +2.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +2.24.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.25. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module activation_buffer: + created 0 $alu and 0 $macc cells. + +2.26. Executing OPT pass (performing simple optimizations). + +2.26.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.26.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \activation_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \activation_buffer. +Performed a total of 0 changes. + +2.26.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 6 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.26.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.26.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +2.26.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.26.9. Finished fast OPT passes. (There is nothing left to do.) + +2.27. Executing MEMORY pass. + +2.27.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +2.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +2.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing activation_buffer.mem write port 0. + +2.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +2.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\mem'[0] in module `\activation_buffer': merging output FF to cell. + Write port 0: non-transparent. + +2.27.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. +Removed 1 unused cells and 9 unused wires. + + +2.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +2.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +2.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +2.27.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +2.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +2.29. Executing MEMORY_LIBMAP pass (mapping memories to cells). +mapping memory activation_buffer.mem via $__DP16KD_ + + +2.30. Executing TECHMAP pass (map to technology primitives). + +2.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +2.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +2.30.3. Continuing TECHMAP pass. +Using template $paramod$c4aea9a221b3d95ca47d9df3d018cdac65e6baac$__DP16KD_ for cells of type $__DP16KD_. +No more expansions possible. + + +2.31. Executing OPT pass (performing simple optimizations). + +2.31.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + + +2.31.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 10 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.31.3. Executing OPT_DFF pass (perform DFF optimizations). +Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$267 ($dffe) from module activation_buffer. + +2.31.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. +Removed 0 unused cells and 51 unused wires. + + +2.31.5. Rerunning OPT passes. (Removed registers in this run.) + +2.31.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.31.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 10 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.31.8. Executing OPT_DFF pass (perform DFF optimizations). + +2.31.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +2.31.10. Finished fast OPT passes. + +2.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +2.33. Executing OPT pass (performing simple optimizations). + +2.33.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.33.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 10 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \activation_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \activation_buffer. +Performed a total of 0 changes. + +2.33.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 10 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.33.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +2.33.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.33.9. Finished fast OPT passes. (There is nothing left to do.) + +2.34. Executing TECHMAP pass (map to technology primitives). + +2.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +2.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +2.34.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $eq. +No more expansions possible. + + +2.35. Executing OPT pass (performing simple optimizations). + +2.35.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.35.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 65 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.35.3. Executing OPT_DFF pass (perform DFF optimizations). + +2.35.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. +Removed 0 unused cells and 1 unused wires. + + +2.35.5. Finished fast OPT passes. + +2.36. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. + +2.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +2.38. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\activation_buffer'. +Computing hashes of 65 cells of `\activation_buffer'. +Finding duplicate cells in `\activation_buffer'. +Removed a total of 0 cells. + +2.39. Executing TECHMAP pass (map to technology primitives). + +2.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +2.39.2. Continuing TECHMAP pass. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +No more expansions possible. + + +2.40. Executing OPT_EXPR pass (perform const folding). +Optimizing module activation_buffer. + +2.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +2.42. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in activation_buffer. + +2.43. Executing ATTRMVCP pass (move or copy attributes). + +2.44. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \activation_buffer.. +Removed 0 unused cells and 120 unused wires. + + +2.45. Executing CHECK pass (checking for obvious problems). +Checking module activation_buffer... +Found and reported 0 problems. + +2.46. Executing TECHMAP pass (map to technology primitives). + +2.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +2.46.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.47. Executing ABC9 pass. + +2.47.1. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.2. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module activation_buffer. +Found 0 SCCs. + +2.47.4. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.5. Executing TECHMAP pass (map to technology primitives). + +2.47.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +2.47.5.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.47.6. Executing OPT pass (performing simple optimizations). + +2.47.6.1. Executing OPT_EXPR pass (perform const folding). + +2.47.6.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +2.47.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +2.47.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +2.47.6.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +2.47.6.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.47.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +2.47.6.8. Executing OPT_EXPR pass (perform const folding). + +2.47.6.9. Finished fast OPT passes. (There is nothing left to do.) + +2.47.7. Executing TECHMAP pass (map to technology primitives). + +2.47.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +2.47.7.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.47.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +2.47.9. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.10. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +2.47.12. Executing AIGMAP pass (map logic to AIG). +Module activation_buffer: replaced 31 cells with 184 new cells, skipped 34 cells. + replaced 3 cell types: + 8 $_MUX_ + 11 $_OR_ + 12 $_XOR_ + not replaced 4 cell types: + 1 $_AND_ + 1 $_NOT_ + 30 TRELLIS_FF + 2 DP16KD + +2.47.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.12.2. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.12.3. Executing XAIGER backend. + +Extracted 72 AND gates and 260 wires from module `activation_buffer' to a netlist network with 72 inputs and 30 outputs. + +2.47.12.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +2.47.12.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 72/ 30 and = 72 lev = 7 (0.77) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 72/ 30 and = 99 lev = 6 (0.73) mem = 0.00 MB ch = 9 box = 0 bb = 0 +ABC: cst = 0 cls = 9 lit = 9 unused = 153 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 99. Ch = 9. Total mem = 0.03 MB. Peak cut mem = 0.01 MB. +ABC: P: Del = 1756.00. Ar = 43.0. Edge = 76. Cut = 391. T = 0.00 sec +ABC: P: Del = 1756.00. Ar = 43.0. Edge = 76. Cut = 390. T = 0.00 sec +ABC: P: Del = 1756.00. Ar = 37.0. Edge = 76. Cut = 505. T = 0.00 sec +ABC: F: Del = 1756.00. Ar = 37.0. Edge = 76. Cut = 348. T = 0.00 sec +ABC: A: Del = 1756.00. Ar = 37.0. Edge = 76. Cut = 347. T = 0.00 sec +ABC: A: Del = 1756.00. Ar = 37.0. Edge = 76. Cut = 342. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: Timing manager is given but there is no GIA of boxes. +ABC: Error: Abc_FrameUpdateGia(): Transformation has failed. +ABC: + &ps -l +ABC: /input : i/o = 72/ 30 and = 72 lev = 6 (0.73) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=7) : lut = 20 edge = 76 lev = 3 (0.37) mem = 0.00 MB +ABC: LUT = 20 : 2=3 15.0 % 3=8 40.0 % 4=4 20.0 % 5=1 5.0 % 6=3 15.0 % 7=1 5.0 % Ave = 3.80 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.01 sec +ABC: + time +ABC: elapse: 0.02 seconds, total: 0.02 seconds + +2.47.12.6. Executing AIGER frontend. + +Removed 119 unused cells and 200 unused wires. + +2.47.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 20 +ABC RESULTS: input signals: 8 +ABC RESULTS: output signals: 5 + +Removing temp directory. + +2.47.13. Executing TECHMAP pass (map to technology primitives). + +2.47.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +2.47.13.2. Continuing TECHMAP pass. +No more expansions possible. + +Removed 8 unused cells and 290 unused wires. + +2.48. Executing TECHMAP pass (map to technology primitives). + +2.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +2.48.2. Continuing TECHMAP pass. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de$lut for cells of type $lut. +Using template $paramod$fe6a5d9c4f188f47ec07e4f5827baa5f3bf54c47$lut for cells of type $lut. +Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673$lut for cells of type $lut. +Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. +Using template $paramod$96f88ffdf52d3059c17d970c5fe3f19815bfce25$lut for cells of type $lut. +Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86$lut for cells of type $lut. +Using template $paramod$233b70872b0d11ad6386b65bc4d8864ac02395bb$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$977bf81c91b9e0cdfe901822d1642d278c1b0ecd$lut for cells of type $lut. +Using template $paramod$a7dad16c080c08c1647c7e1b9706a59a123d8bcd$lut for cells of type $lut. +No more expansions possible. + + +2.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in activation_buffer. + Optimizing lut $abc$1122$lut$aiger$o2.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger$o2.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$90.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$1122$lut$aiger1121$100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$83.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$90.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$1122$lut$aiger1121$90.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$1122$lut$aiger$o2.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) +Removed 0 unused cells and 51 unused wires. + +2.50. Executing AUTONAME pass. +Renamed 149 objects in module activation_buffer. + + +2.51. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `activation_buffer'. Setting top module to activation_buffer. + +2.51.1. Analyzing design hierarchy.. +Top module: \activation_buffer + +2.51.2. Analyzing design hierarchy.. +Top module: \activation_buffer +Removed 0 unused modules. + +2.52. Printing statistics. + +=== activation_buffer === + + +----------Local Count, excluding submodules. + | + 71 wires + 229 wire bits + 71 public wires + 229 public wire bits + 6 ports + 42 port bits + 2 cells + 2 DP16KD + 84 submodules + 6 L6MUX21 + 37 LUT4 + 11 PFUMX + 30 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + 2 activation_buffer + + +----------Count including submodules. + | + 71 wires + 229 wire bits + 71 public wires + 229 public wire bits + 6 ports + 42 port bits + - memories + - memory bits + - processes + 2 cells + 2 DP16KD + 84 submodules + 6 L6MUX21 + 37 LUT4 + 11 PFUMX + 30 TRELLIS_FF + +2.53. Executing CHECK pass (checking for obvious problems). +Checking module activation_buffer... +Found and reported 0 problems. + +2.54. Executing JSON backend. + +End of script. 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"CH0_RX_LOS_LVL": "DONTCARE", + "CH0_RX_RATE_SEL": "DONTCARE", + "CH0_RX_SB_BYPASS": "DONTCARE", + "CH0_SB_BYPASS": "DONTCARE", + "CH0_SEL_SD_RX_CLK": "DONTCARE", + "CH0_TDRV_DAT_SEL": "DONTCARE", + "CH0_TDRV_POST_EN": "DONTCARE", + "CH0_TDRV_PRE_EN": "DONTCARE", + "CH0_TDRV_SLICE0_CUR": "DONTCARE", + "CH0_TDRV_SLICE0_SEL": "DONTCARE", + "CH0_TDRV_SLICE1_CUR": "DONTCARE", + "CH0_TDRV_SLICE1_SEL": "DONTCARE", + "CH0_TDRV_SLICE2_CUR": "DONTCARE", + "CH0_TDRV_SLICE2_SEL": "DONTCARE", + "CH0_TDRV_SLICE3_CUR": "DONTCARE", + "CH0_TDRV_SLICE3_SEL": "DONTCARE", + "CH0_TDRV_SLICE4_CUR": "DONTCARE", + "CH0_TDRV_SLICE4_SEL": "DONTCARE", + "CH0_TDRV_SLICE5_CUR": "DONTCARE", + "CH0_TDRV_SLICE5_SEL": "DONTCARE", + "CH0_TPWDNB": "DONTCARE", + "CH0_TXAMPLITUDE": "DONTCARE", + "CH0_TXDEPOST": "DONTCARE", + "CH0_TXDEPRE": "DONTCARE", + "CH0_TX_CM_SEL": "DONTCARE", + "CH0_TX_DIV11_SEL": "DONTCARE", + "CH0_TX_GEAR_BYPASS": "DONTCARE", + "CH0_TX_GEAR_MODE": "DONTCARE", + "CH0_TX_POST_SIGN": "DONTCARE", + "CH0_TX_PRE_SIGN": "DONTCARE", + "CH0_UC_MODE": "DONTCARE", + "CH0_UDF_COMMA_A": "DONTCARE", + "CH0_UDF_COMMA_B": "DONTCARE", + "CH0_UDF_COMMA_MASK": "DONTCARE", + "CH0_WA_BYPASS": "DONTCARE", + "CH0_WA_MODE": "DONTCARE", + "CH1_AUTO_CALIB_EN": "DONTCARE", + "CH1_AUTO_FACQ_EN": "DONTCARE", + "CH1_BAND_THRESHOLD": "DONTCARE", + "CH1_CALIB_CK_MODE": "DONTCARE", + "CH1_CC_MATCH_1": "DONTCARE", + "CH1_CC_MATCH_2": "DONTCARE", + "CH1_CC_MATCH_3": "DONTCARE", + "CH1_CC_MATCH_4": "DONTCARE", + "CH1_CDR_CNT4SEL": "DONTCARE", + "CH1_CDR_CNT8SEL": "DONTCARE", + "CH1_CDR_MAX_RATE": "DONTCARE", + "CH1_CTC_BYPASS": "DONTCARE", + "CH1_DCOATDCFG": "DONTCARE", + "CH1_DCOATDDLY": "DONTCARE", + "CH1_DCOBYPSATD": "DONTCARE", + "CH1_DCOCALDIV": "DONTCARE", + "CH1_DCOCTLGI": "DONTCARE", + "CH1_DCODISBDAVOID": "DONTCARE", + "CH1_DCOFLTDAC": "DONTCARE", + "CH1_DCOFTNRG": "DONTCARE", + "CH1_DCOIOSTUNE": "DONTCARE", + "CH1_DCOITUNE": "DONTCARE", + "CH1_DCOITUNE4LSB": "DONTCARE", + "CH1_DCOIUPDNX2": "DONTCARE", + "CH1_DCONUOFLSB": "DONTCARE", + "CH1_DCOSCALEI": "DONTCARE", + "CH1_DCOSTARTVAL": "DONTCARE", + "CH1_DCOSTEP": "DONTCARE", + "CH1_DEC_BYPASS": "DONTCARE", + "CH1_ENABLE_CG_ALIGN": "DONTCARE", + "CH1_ENC_BYPASS": "DONTCARE", + "CH1_FF_RX_F_CLK_DIS": "DONTCARE", + "CH1_FF_RX_H_CLK_EN": "DONTCARE", + "CH1_FF_TX_F_CLK_DIS": "DONTCARE", + "CH1_FF_TX_H_CLK_EN": "DONTCARE", + "CH1_GE_AN_ENABLE": "DONTCARE", + "CH1_INVERT_RX": "DONTCARE", + "CH1_INVERT_TX": "DONTCARE", + "CH1_LDR_CORE2TX_SEL": "DONTCARE", + "CH1_LDR_RX2CORE_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_TRIM": "DONTCARE", + "CH1_LSM_DISABLE": "DONTCARE", + "CH1_MATCH_2_ENABLE": "DONTCARE", + "CH1_MATCH_4_ENABLE": "DONTCARE", + "CH1_MIN_IPG_CNT": "DONTCARE", + "CH1_PCIE_EI_EN": "DONTCARE", + "CH1_PCIE_MODE": "DONTCARE", + "CH1_PCS_DET_TIME_SEL": "DONTCARE", + "CH1_PDEN_SEL": "DONTCARE", + "CH1_PRBS_ENABLE": "DONTCARE", + "CH1_PRBS_LOCK": "DONTCARE", + "CH1_PRBS_SELECTION": "DONTCARE", + "CH1_PROTOCOL": "DONTCARE", + "CH1_RATE_MODE_RX": "DONTCARE", + "CH1_RATE_MODE_TX": "DONTCARE", + "CH1_RCV_DCC_EN": "DONTCARE", + "CH1_REG_BAND_OFFSET": "DONTCARE", + "CH1_REG_BAND_SEL": "DONTCARE", + "CH1_REG_IDAC_EN": "DONTCARE", + "CH1_REG_IDAC_SEL": "DONTCARE", + "CH1_REQ_EN": "DONTCARE", + "CH1_REQ_LVL_SET": "DONTCARE", + "CH1_RIO_MODE": "DONTCARE", + "CH1_RLOS_SEL": "DONTCARE", + "CH1_RPWDNB": "DONTCARE", + "CH1_RTERM_RX": "DONTCARE", + "CH1_RTERM_TX": "DONTCARE", + "CH1_RXIN_CM": "DONTCARE", + "CH1_RXTERM_CM": "DONTCARE", + "CH1_RX_DCO_CK_DIV": "DONTCARE", + "CH1_RX_DIV11_SEL": "DONTCARE", + "CH1_RX_GEAR_BYPASS": "DONTCARE", + "CH1_RX_GEAR_MODE": "DONTCARE", + "CH1_RX_LOS_CEQ": "DONTCARE", + "CH1_RX_LOS_EN": "DONTCARE", + "CH1_RX_LOS_HYST_EN": "DONTCARE", + "CH1_RX_LOS_LVL": "DONTCARE", + "CH1_RX_RATE_SEL": "DONTCARE", + "CH1_RX_SB_BYPASS": "DONTCARE", + "CH1_SB_BYPASS": "DONTCARE", + "CH1_SEL_SD_RX_CLK": "DONTCARE", + "CH1_TDRV_DAT_SEL": "DONTCARE", + "CH1_TDRV_POST_EN": "DONTCARE", + "CH1_TDRV_PRE_EN": "DONTCARE", + "CH1_TDRV_SLICE0_CUR": "DONTCARE", + "CH1_TDRV_SLICE0_SEL": "DONTCARE", + "CH1_TDRV_SLICE1_CUR": "DONTCARE", + "CH1_TDRV_SLICE1_SEL": "DONTCARE", + "CH1_TDRV_SLICE2_CUR": "DONTCARE", + "CH1_TDRV_SLICE2_SEL": "DONTCARE", + "CH1_TDRV_SLICE3_CUR": "DONTCARE", + "CH1_TDRV_SLICE3_SEL": "DONTCARE", + "CH1_TDRV_SLICE4_CUR": "DONTCARE", + "CH1_TDRV_SLICE4_SEL": "DONTCARE", + "CH1_TDRV_SLICE5_CUR": "DONTCARE", + "CH1_TDRV_SLICE5_SEL": "DONTCARE", + "CH1_TPWDNB": "DONTCARE", + "CH1_TXAMPLITUDE": "DONTCARE", + "CH1_TXDEPOST": "DONTCARE", + "CH1_TXDEPRE": "DONTCARE", + "CH1_TX_CM_SEL": "DONTCARE", + "CH1_TX_DIV11_SEL": "DONTCARE", + "CH1_TX_GEAR_BYPASS": "DONTCARE", + "CH1_TX_GEAR_MODE": "DONTCARE", + "CH1_TX_POST_SIGN": "DONTCARE", + "CH1_TX_PRE_SIGN": "DONTCARE", + "CH1_UC_MODE": "DONTCARE", + "CH1_UDF_COMMA_A": "DONTCARE", + "CH1_UDF_COMMA_B": "DONTCARE", + "CH1_UDF_COMMA_MASK": "DONTCARE", + "CH1_WA_BYPASS": "DONTCARE", + "CH1_WA_MODE": "DONTCARE", + "D_BITCLK_FROM_ND_EN": "DONTCARE", + "D_BITCLK_LOCAL_EN": "DONTCARE", + "D_BITCLK_ND_EN": "DONTCARE", + "D_BUS8BIT_SEL": "DONTCARE", + "D_CDR_LOL_SET": "DONTCARE", + "D_CMUSETBIASI": "DONTCARE", + "D_CMUSETI4CPP": "DONTCARE", + "D_CMUSETI4CPZ": "DONTCARE", + "D_CMUSETI4VCO": "DONTCARE", + "D_CMUSETICP4P": "DONTCARE", + "D_CMUSETICP4Z": "DONTCARE", + "D_CMUSETINITVCT": "DONTCARE", + "D_CMUSETISCL4VCO": "DONTCARE", + "D_CMUSETP1GM": "DONTCARE", + "D_CMUSETP2AGM": "DONTCARE", + "D_CMUSETZGM": "DONTCARE", + "D_DCO_CALIB_TIME_SEL": "DONTCARE", + "D_HIGH_MARK": "DONTCARE", + "D_IB_PWDNB": "DONTCARE", + "D_ISETLOS": "DONTCARE", + "D_LOW_MARK": "DONTCARE", + "D_MACROPDB": "DONTCARE", + "D_PD_ISET": "DONTCARE", + "D_PLL_LOL_SET": "DONTCARE", + "D_REFCK_MODE": "DONTCARE", + "D_REQ_ISET": "DONTCARE", + "D_RG_EN": "DONTCARE", + "D_RG_SET": "DONTCARE", + "D_SETICONST_AUX": "DONTCARE", + "D_SETICONST_CH": "DONTCARE", + "D_SETIRPOLY_AUX": "DONTCARE", + "D_SETIRPOLY_CH": "DONTCARE", + "D_SETPLLRC": "DONTCARE", + "D_SYNC_LOCAL_EN": "DONTCARE", + "D_SYNC_ND_EN": "DONTCARE", + "D_TXPLL_PWDNB": "DONTCARE", + "D_TX_MAX_RATE": "DONTCARE", + "D_TX_VCO_CK_DIV": "DONTCARE", + "D_XGE_MODE": "DONTCARE" + }, + "ports": { + "CH0_HDINP": { + "direction": "input", + "bits": [ 2 ] + }, + "CH1_HDINP": { + "direction": "input", + "bits": [ 3 ] + }, + "CH0_HDINN": { + "direction": "input", + "bits": [ 4 ] + }, + "CH1_HDINN": { + "direction": "input", + "bits": [ 5 ] + }, + "D_TXBIT_CLKP_FROM_ND": { + "direction": "input", + "bits": [ 6 ] + }, + "D_TXBIT_CLKN_FROM_ND": { + "direction": "input", + "bits": [ 7 ] + }, + "D_SYNC_ND": { + "direction": "input", + "bits": [ 8 ] + }, + "D_TXPLL_LOL_FROM_ND": { + "direction": "input", + "bits": [ 9 ] + }, + "CH0_RX_REFCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "CH1_RX_REFCLK": { + "direction": "input", + "bits": [ 11 ] + }, + "CH0_FF_RXI_CLK": { + "direction": "input", + "bits": [ 12 ] + }, + "CH1_FF_RXI_CLK": { + "direction": "input", + "bits": [ 13 ] + }, + "CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 86 ] + }, + "CH1_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 87 ] + }, + "CH0_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 88 ] + }, + "CH1_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 89 ] + }, + "CH0_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 90 ] + }, + "CH1_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 91 ] + }, + "CH0_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 92 ] + }, + "CH1_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 93 ] + }, + "CH0_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 94 ] + }, + "CH1_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 95 ] + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 96 ] + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 97 ] + }, + "CH0_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 98 ] + }, + "CH1_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 99 ] + }, + "CH0_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 100 ] + }, + "CH1_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 101 ] + }, + "CH0_FFC_RRST": { + "direction": "input", + "bits": [ 102 ] + }, + "CH1_FFC_RRST": { + "direction": "input", + "bits": [ 103 ] + }, + "CH0_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 104 ] + }, + "CH1_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 105 ] + }, + "CH0_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 106 ] + }, + "CH1_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 107 ] + }, + "CH0_LDR_CORE2TX": { + "direction": "input", + "bits": [ 108 ] + }, + "CH1_LDR_CORE2TX": { + "direction": "input", + "bits": [ 109 ] + }, + "D_SCIWDATA0": { + "direction": "input", + "bits": [ 110 ] + }, + "D_SCIWDATA1": { + "direction": "input", + "bits": [ 111 ] + }, + "D_SCIWDATA2": { + "direction": "input", + "bits": [ 112 ] + }, + "D_SCIWDATA3": { + "direction": "input", + "bits": [ 113 ] + }, + "D_SCIWDATA4": { + "direction": "input", + "bits": [ 114 ] + }, + "D_SCIWDATA5": { + "direction": "input", + "bits": [ 115 ] + }, + "D_SCIWDATA6": { + "direction": "input", + "bits": [ 116 ] + }, + "D_SCIWDATA7": { + "direction": "input", + "bits": [ 117 ] + }, + "D_SCIADDR0": { + "direction": "input", + "bits": [ 118 ] + }, + "D_SCIADDR1": { + "direction": "input", + "bits": [ 119 ] + }, + "D_SCIADDR2": { + "direction": "input", + "bits": [ 120 ] + }, + "D_SCIADDR3": { + "direction": "input", + "bits": [ 121 ] + }, + "D_SCIADDR4": { + "direction": "input", + "bits": [ 122 ] + }, + "D_SCIADDR5": { + "direction": "input", + "bits": [ 123 ] + }, + "D_SCIENAUX": { + "direction": "input", + "bits": [ 124 ] + }, + "D_SCISELAUX": { + "direction": "input", + "bits": [ 125 ] + }, + "CH0_SCIEN": { + "direction": "input", + "bits": [ 126 ] + }, + "CH1_SCIEN": { + "direction": "input", + "bits": [ 127 ] + }, + "CH0_SCISEL": { + "direction": "input", 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"mem.0.0_DOB2_TRELLIS_FF_Q_DI_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24" + } + }, + "mem.0.0_DOB2_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.18-133.20" + } + }, + "mem.0.0_DOB3": { + "hide_name": 0, + "bits": [ 81, 111, 107 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.0_DOB4": { + "hide_name": 0, + "bits": [ 112, 82, 107 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.0_DOB5": { + "hide_name": 0, + "bits": [ 113, 83, 107 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.0_DOB6": { + "hide_name": 0, + "bits": [ 114, 84, 107 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.0_DOB7": { + "hide_name": 0, + "bits": [ 115, 85, 107 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.0_DOB8": { + "hide_name": 0, + "bits": [ 70, 71, 80, 81, 82, 83, 84, 85, 86 ], + "attributes": { + "unused_bits": "8" + } + }, + "mem.0.0_DOB9": { + "hide_name": 0, + "bits": [ 70, 71, 80, 81, 82, 83, 84, 85, 86, 87, 72, 73, 74, 75, 76, 77, 78, 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v:46.13-46.16", + "unused_bits": "8 9 10 11 12 13 14 15 16 17" + } + }, + "rd_addr": { + "hide_name": 0, + "bits": [ 20, 21, 22, 23, 24, 25, 26, 27 ], + "attributes": { + "src": "hardware/v2/rtl/result_buffer.v:32.41-32.48" + } + }, + "rd_data": { + "hide_name": 0, + "bits": [ 28, 29, 30, 31, 32, 33, 34, 35 ], + "signed": 1, + "attributes": { + "src": "hardware/v2/rtl/result_buffer.v:33.41-33.48" + } + }, + "wr_addr": { + "hide_name": 0, + "bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ], + "attributes": { + "src": "hardware/v2/rtl/result_buffer.v:29.41-29.48" + } + }, + "wr_data": { + "hide_name": 0, + "bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ], + "signed": 1, + "attributes": { + "src": "hardware/v2/rtl/result_buffer.v:30.41-30.48" + } + }, + "wr_en": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "hardware/v2/rtl/result_buffer.v:28.41-28.46" + } + }, + "wr_en_TRELLIS_FF_DI_Q": { + "hide_name": 0, + "bits": [ 26, 24, 43, 41, 88, 93 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + } + } + } + } +} diff --git a/hardware/v2/synthesis/result_buffer_d256/yosys.log b/hardware/v2/synthesis/result_buffer_d256/yosys.log new file mode 100644 index 0000000..f6b9d00 --- /dev/null +++ b/hardware/v2/synthesis/result_buffer_d256/yosys.log @@ -0,0 +1,1162 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) + +-- Running command ` + read_verilog hardware/v2/rtl/result_buffer.v + chparam -set DEPTH 256 result_buffer + synth_ecp5 -json hardware/v2/synthesis/result_buffer_d256/top.json -top result_buffer +' -- + +1. Executing Verilog-2005 frontend: hardware/v2/rtl/result_buffer.v +Parsing Verilog input from `hardware/v2/rtl/result_buffer.v' to AST representation. +Generating RTLIL representation for module `\result_buffer'. +Successfully finished Verilog frontend. +Parameter \DEPTH = 256 + +2. Executing AST frontend in derive mode using pre-parsed AST for module `\result_buffer'. +Parameter \DEPTH = 256 +Generating RTLIL representation for module `$paramod\result_buffer\DEPTH=s32'00000000000000000000000100000000'. + +3. Executing SYNTH_LATTICE pass. + +3.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +3.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +3.3. Executing HIERARCHY pass (managing design hierarchy). + +3.3.1. Analyzing design hierarchy.. +Top module: \result_buffer + +3.3.2. Analyzing design hierarchy.. +Top module: \result_buffer +Removed 0 unused modules. + +3.4. Executing PROC pass (convert processes to netlists). + +3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/result_buffer.v:38$12 in module result_buffer. +Removed a total of 0 dead cases. + +3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 4 assignments to connections. + +3.4.4. Executing PROC_INIT pass (extract init attributes). + +3.4.5. Executing PROC_ARST pass (detect async resets in processes). + +3.4.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:38$12'. + 1/3: $1$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_EN[7:0]$18 + 2/3: $1$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_DATA[7:0]$17 + 3/3: $1$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_ADDR[7:0]$16 +Creating decoders for process `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:43$19'. + +3.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +3.4.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\result_buffer.$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_ADDR' using process `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:38$12'. + created $dff cell `$procdff$255' with positive edge clock. +Creating register for signal `\result_buffer.$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_DATA' using process `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:38$12'. + created $dff cell `$procdff$256' with positive edge clock. +Creating register for signal `\result_buffer.$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_EN' using process `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:38$12'. + created $dff cell `$procdff$257' with positive edge clock. +Creating register for signal `\result_buffer.\rd_data' using process `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:43$19'. + created $dff cell `$procdff$258' with positive edge clock. + +3.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:38$12'. +Removing empty process `result_buffer.$proc$hardware/v2/rtl/result_buffer.v:38$12'. +Removing empty process `result_buffer.$proc$hardware/v2/rtl/result_buffer.v:43$19'. +Cleaned up 1 empty switch. + +3.4.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.5. Executing CHECK pass (checking for obvious problems). +Checking module result_buffer... +Found and reported 0 problems. + +3.6. Executing FLATTEN pass (flatten design). + +3.7. Executing TRIBUF pass. + +3.8. Executing DEMINOUT pass (demote inout ports to input or output). + +3.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. +Removed 3 unused cells and 13 unused wires. + + +3.11. Executing CHECK pass (checking for obvious problems). +Checking module result_buffer... +Found and reported 0 problems. + +3.12. Executing OPT pass (performing simple optimizations). + +3.12.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.12.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \result_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \result_buffer. + Consolidated identical input bits for $mux cell $procmux$247: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_EN[7:0]$15 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_EN[7:0]$15 [0] + New connections: $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_EN[7:0]$15 [7:1] = { $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$11_EN[7:0]$15 [0] } + Optimizing cells in module \result_buffer. +Performed a total of 1 changes. + +3.12.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.12.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +3.12.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.12.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \result_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \result_buffer. +Performed a total of 0 changes. + +3.12.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.12.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +3.12.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.12.16. Finished fast OPT passes. (There is nothing left to do.) + +3.13. Executing FSM pass (extract and optimize FSM). + +3.13.1. Executing FSM_DETECT pass (finding FSMs in design). + +3.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +3.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +3.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +3.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +3.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +3.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +3.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +3.14. Executing OPT pass (performing simple optimizations). + +3.14.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.14.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \result_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \result_buffer. +Performed a total of 0 changes. + +3.14.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.14.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +3.14.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.14.9. Finished fast OPT passes. (There is nothing left to do.) + +3.15. Executing WREDUCE pass (reducing word size of cells). + +3.16. Executing PEEPOPT pass (run peephole optimizers). + +3.17. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +3.18. Executing SHARE pass (SAT-based resource sharing). + +3.19. Executing TECHMAP pass (map to technology primitives). + +3.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +3.19.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.20. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +3.22. Executing TECHMAP pass (map to technology primitives). + +3.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +3.22.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.23. Executing TECHMAP pass (map to technology primitives). + +3.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +3.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.24. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module result_buffer: + created 0 $alu and 0 $macc cells. + +3.25. Executing OPT pass (performing simple optimizations). + +3.25.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.25.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \result_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \result_buffer. +Performed a total of 0 changes. + +3.25.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.25.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +3.25.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.25.9. Finished fast OPT passes. (There is nothing left to do.) + +3.26. Executing MEMORY pass. + +3.26.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +3.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +3.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing result_buffer.mem write port 0. + +3.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +3.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\mem'[0] in module `\result_buffer': merging output FF to cell. + Write port 0: non-transparent. + +3.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. +Removed 1 unused cells and 9 unused wires. + + +3.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +3.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +3.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +3.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +3.27. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +3.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). +mapping memory result_buffer.mem via $__DP16KD_ + + +3.29. Executing TECHMAP pass (map to technology primitives). + +3.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +3.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +3.29.3. Continuing TECHMAP pass. +Using template $paramod$eed5c07ccc20b30fea5f07adc53d361b0ef0f8bc$__DP16KD_ for cells of type $__DP16KD_. +No more expansions possible. + + +3.30. Executing OPT pass (performing simple optimizations). + +3.30.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + + +3.30.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 9 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.30.3. Executing OPT_DFF pass (perform DFF optimizations). +Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$277 ($dffe) from module result_buffer. + +3.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. +Removed 0 unused cells and 26 unused wires. + + +3.30.5. Rerunning OPT passes. (Removed registers in this run.) + +3.30.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.30.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 9 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.30.8. Executing OPT_DFF pass (perform DFF optimizations). + +3.30.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +3.30.10. Finished fast OPT passes. + +3.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +3.32. Executing OPT pass (performing simple optimizations). + +3.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 9 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \result_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \result_buffer. +Performed a total of 0 changes. + +3.32.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 9 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.32.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +3.32.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.32.9. Finished fast OPT passes. (There is nothing left to do.) + +3.33. Executing TECHMAP pass (map to technology primitives). + +3.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +3.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +3.33.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $eq. +No more expansions possible. + + +3.34. Executing OPT pass (performing simple optimizations). + +3.34.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.34.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 52 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.34.3. Executing OPT_DFF pass (perform DFF optimizations). + +3.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. +Removed 0 unused cells and 1 unused wires. + + +3.34.5. Finished fast OPT passes. + +3.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +3.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +3.37. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 52 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +3.38. Executing TECHMAP pass (map to technology primitives). + +3.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +3.38.2. Continuing TECHMAP pass. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +No more expansions possible. + + +3.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +3.40. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +3.41. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in result_buffer. + +3.42. Executing ATTRMVCP pass (move or copy attributes). + +3.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. +Removed 0 unused cells and 104 unused wires. + + +3.44. Executing CHECK pass (checking for obvious problems). +Checking module result_buffer... +Found and reported 0 problems. + +3.45. Executing TECHMAP pass (map to technology primitives). + +3.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +3.45.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.46. Executing ABC9 pass. + +3.46.1. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.2. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module result_buffer. +Found 0 SCCs. + +3.46.4. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.5. Executing TECHMAP pass (map to technology primitives). + +3.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +3.46.5.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.46.6. Executing OPT pass (performing simple optimizations). + +3.46.6.1. Executing OPT_EXPR pass (perform const folding). + +3.46.6.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +3.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +3.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +3.46.6.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +3.46.6.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +3.46.6.8. Executing OPT_EXPR pass (perform const folding). + +3.46.6.9. Finished fast OPT passes. (There is nothing left to do.) + +3.46.7. Executing TECHMAP pass (map to technology primitives). + +3.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +3.46.7.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3.46.9. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.10. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +3.46.12. Executing AIGMAP pass (map logic to AIG). +Module result_buffer: replaced 23 cells with 140 new cells, skipped 29 cells. + replaced 3 cell types: + 8 $_MUX_ + 7 $_OR_ + 8 $_XOR_ + not replaced 4 cell types: + 1 $_AND_ + 1 $_NOT_ + 26 TRELLIS_FF + 1 DP16KD + +3.46.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.12.2. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.12.3. Executing XAIGER backend. + +Extracted 56 AND gates and 204 wires from module `result_buffer' to a netlist network with 60 inputs and 26 outputs. + +3.46.12.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +3.46.12.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 60/ 26 and = 56 lev = 6 (0.85) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 60/ 26 and = 119 lev = 6 (0.85) mem = 0.00 MB ch = 13 box = 0 bb = 0 +ABC: cst = 0 cls = 12 lit = 13 unused = 154 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 119. Ch = 12. Total mem = 0.03 MB. Peak cut mem = 0.02 MB. +ABC: P: Del = 1612.00. Ar = 33.0. Edge = 58. Cut = 648. T = 0.00 sec +ABC: P: Del = 1612.00. Ar = 33.0. Edge = 58. Cut = 634. T = 0.00 sec +ABC: P: Del = 1612.00. Ar = 27.0. Edge = 59. Cut = 849. T = 0.00 sec +ABC: F: Del = 1581.00. Ar = 21.0. Edge = 58. Cut = 756. T = 0.00 sec +ABC: A: Del = 1581.00. Ar = 21.0. Edge = 58. Cut = 729. T = 0.00 sec +ABC: A: Del = 1581.00. Ar = 21.0. Edge = 58. Cut = 725. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: Timing manager is given but there is no GIA of boxes. +ABC: Error: Abc_FrameUpdateGia(): Transformation has failed. +ABC: + &ps -l +ABC: /input : i/o = 60/ 26 and = 56 lev = 6 (0.85) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=6) : lut = 16 edge = 58 lev = 3 (0.42) mem = 0.00 MB +ABC: LUT = 16 : 2=1 6.2 % 3=8 50.0 % 4=4 25.0 % 5=2 12.5 % 6=1 6.2 % Ave = 3.62 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.01 sec +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +3.46.12.6. Executing AIGER frontend. + +Removed 89 unused cells and 158 unused wires. + +3.46.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 16 +ABC RESULTS: input signals: 8 +ABC RESULTS: output signals: 5 + +Removing temp directory. + +3.46.13. Executing TECHMAP pass (map to technology primitives). + +3.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +3.46.13.2. Continuing TECHMAP pass. +No more expansions possible. + +Removed 8 unused cells and 233 unused wires. + +3.47. Executing TECHMAP pass (map to technology primitives). + +3.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +3.47.2. Continuing TECHMAP pass. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. +Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut. +Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$977bf81c91b9e0cdfe901822d1642d278c1b0ecd$lut for cells of type $lut. +Using template $paramod$8614da24b3846fe751594d00fba789cfcb7b874c$lut for cells of type $lut. +Using template $paramod$adb3580ae7f1e000bff662054d4f52a48cec1e58$lut for cells of type $lut. +Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. +No more expansions possible. + + +3.48. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in result_buffer. + Optimizing lut $abc$1022$lut$aiger1021$70.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$1022$lut$aiger1021$70.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$1022$lut$aiger1021$88.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$1022$lut$aiger1021$70.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$1022$lut$aiger$o2.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) +Removed 0 unused cells and 37 unused wires. + +3.49. Executing AUTONAME pass. +Renamed 89 objects in module result_buffer. + + +3.50. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `result_buffer'. Setting top module to result_buffer. + +3.50.1. Analyzing design hierarchy.. +Top module: \result_buffer + +3.50.2. Analyzing design hierarchy.. +Top module: \result_buffer +Removed 0 unused modules. + +3.51. Printing statistics. + +=== result_buffer === + + +----------Local Count, excluding submodules. + | + 43 wires + 159 wire bits + 43 public wires + 159 public wire bits + 6 ports + 34 port bits + 1 cells + 1 DP16KD + 52 submodules + 1 L6MUX21 + 21 LUT4 + 4 PFUMX + 26 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + 1 result_buffer + + +----------Count including submodules. + | + 43 wires + 159 wire bits + 43 public wires + 159 public wire bits + 6 ports + 34 port bits + - memories + - memory bits + - processes + 1 cells + 1 DP16KD + 52 submodules + 1 L6MUX21 + 21 LUT4 + 4 PFUMX + 26 TRELLIS_FF + +3.52. Executing CHECK pass (checking for obvious problems). +Checking module result_buffer... +Found and reported 0 problems. + +3.53. Executing JSON backend. + +End of script. Logfile hash: a36a36f2d5, time: 0.30s, user: 0.27s, system: 0.01s, MEM: 28.39 MB peak +Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) +Time spent: 57% 20x read_verilog (0 sec), 24% 11x techmap (0 sec), ... diff --git a/hardware/v2/synthesis/result_buffer_d4096/nextpnr.log b/hardware/v2/synthesis/result_buffer_d4096/nextpnr.log new file mode 100644 index 0000000..bd4ef97 --- /dev/null +++ b/hardware/v2/synthesis/result_buffer_d4096/nextpnr.log @@ -0,0 +1,231 @@ + + +Info: Logic utilisation before packing: +Info: Total LUT4s: 37/43848 0% +Info: logic LUTs: 37/43848 0% +Info: carry LUTs: 0/43848 0% +Info: RAM LUTs: 0/ 5481 0% +Info: RAMW LUTs: 0/10962 0% + +Info: Total DFFs: 30/43848 0% + +Info: Packing IOs.. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 0 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0x72c9a928 + +Info: Device utilisation: +Info: TRELLIS_IO: 42/ 245 17% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 2/ 108 1% +Info: MULT18X18D: 0/ 72 0% +Info: ALU54B: 0/ 36 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 160 0% +Info: SIOLOGIC: 0/ 85 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 10 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 30/ 43848 0% +Info: TRELLIS_COMB: 39/ 43848 0% +Info: TRELLIS_RAMW: 0/ 5481 0% + +Info: Placed 0 cells based on constraints. +Info: Creating initial analytic placement for 52 cells, random placement wirelen = 6761. +Info: at initial placer iter 0, wirelen = 2512 +Info: at initial placer iter 1, wirelen = 2493 +Info: at initial placer iter 2, wirelen = 2489 +Info: at initial placer iter 3, wirelen = 2489 +Info: Running main analytical placer, max placement attempts per cell = 10000. +Info: at iteration #1, type ALL: wirelen solved = 2490, spread = 2980, legal = 3609; time = 0.00s +Info: at iteration #2, type ALL: wirelen solved = 2499, spread = 2882, legal = 3446; time = 0.00s +Info: at iteration #3, type ALL: wirelen solved = 2487, spread = 2864, legal = 3310; time = 0.00s +Info: at iteration #4, type ALL: wirelen solved = 2497, spread = 2893, legal = 3455; time = 0.00s +Info: at iteration #5, type ALL: wirelen solved = 2495, spread = 2888, legal = 3449; time = 0.00s +Info: at iteration #6, type ALL: wirelen solved = 2516, spread = 2855, legal = 3121; time = 0.00s +Info: HeAP Placer Time: 0.02s +Info: of which solving equations: 0.00s +Info: of which spreading cells: 0.00s +Info: of which strict legalisation: 0.00s + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 17, wirelen = 3121 +Info: at iteration #5: temp = 0.000000, timing cost = 13, wirelen = 2026 +Info: at iteration #10: temp = 0.000000, timing cost = 11, wirelen = 1982 +Info: at iteration #15: temp = 0.000000, timing cost = 9, wirelen = 1976 +Info: at iteration #15: temp = 0.000000, timing cost = 9, wirelen = 1977 +Info: SA placement time 0.01s + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 287.77 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.73 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 10.33 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 9025, 9161) |* +Info: [ 9161, 9297) | +Info: [ 9297, 9433) | +Info: [ 9433, 9569) | +Info: [ 9569, 9705) | +Info: [ 9705, 9841) | +Info: [ 9841, 9977) | +Info: [ 9977, 10113) | +Info: [ 10113, 10249) | +Info: [ 10249, 10385) |* +Info: [ 10385, 10521) |***** +Info: [ 10521, 10657) |******** +Info: [ 10657, 10793) |************ +Info: [ 10793, 10929) |* +Info: [ 10929, 11065) |* +Info: [ 11065, 11201) | +Info: [ 11201, 11337) |* +Info: [ 11337, 11473) |***** +Info: [ 11473, 11609) |** +Info: [ 11609, 11745) |****** +Info: Checksum: 0x8fd0df74 +Info: Routing globals... +Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 211 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 221 | 10 200 | 10 200 | 0| 0.05 0.05| +Info: Routing complete. +Info: Router1 time 0.05s +Info: Checksum: 0xb7c8fedd + +Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source mem.0.1_ADA5_TRELLIS_FF_Q_1.Q +Info: routing 0.52 0.92 Net mem.0.1_ADA5[2] (27,17) -> (29,17) +Info: Sink mem.0.1_ADA11_LUT4_D_Z_LUT4_Z_1.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 1.10 Source mem.0.1_ADA11_LUT4_D_Z_LUT4_Z_1.F +Info: routing 0.51 1.61 Net mem.0.1_ADA11_LUT4_D_Z[5] (29,17) -> (29,18) +Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.19 1.80 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.00 1.80 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1 (29,18) -> (29,18) +Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72 +Info: logic 0.18 1.98 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.55 2.53 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z[5] (29,18) -> (27,17) +Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.19 2.72 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.35 3.08 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI (27,17) -> (27,17) +Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1.M +Info: setup 0.00 3.08 Source mem.0.0_DOB0_TRELLIS_FF_Q_1.M +Info: 1.14 ns logic, 1.93 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': +Info: type curr total name +Info: source 0.00 0.00 Source rd_addr[2]$tr_io.O +Info: routing 3.38 3.38 Net rd_addr[2]$TRELLIS_IO_IN (90,14) -> (28,18) +Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 3.56 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F +Info: routing 0.00 3.56 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT (28,18) -> (28,18) +Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1 +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32 +Info: logic 0.13 3.69 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 0.00 3.69 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1 (28,18) -> (28,18) +Info: Sink mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40 +Info: logic 0.18 3.87 Source mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.53 4.40 Net mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z[2] (28,18) -> (27,17) +Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 4.58 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F +Info: routing 0.00 4.58 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT (27,17) -> (27,17) +Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1 +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32 +Info: logic 0.13 4.70 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 0.00 4.70 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1 (27,17) -> (27,17) +Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40 +Info: logic 0.18 4.88 Source mem.0.0_DOB0_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.35 5.23 Net mem.0.0_DOB0_TRELLIS_FF_Q_1_DI (27,17) -> (27,17) +Info: Sink mem.0.0_DOB0_TRELLIS_FF_Q_1.M +Info: setup 0.00 5.23 Source mem.0.0_DOB0_TRELLIS_FF_Q_1.M +Info: 0.97 ns logic, 4.26 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': +Info: type curr total name +Info: clk-to-q 4.26 4.26 Source mem.0.0.DOB2 +Info: routing 0.94 5.20 Net mem.0.0_DOB2[1] (26,10) -> (26,11) +Info: Sink rd_data_LUT4_Z_4.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v:46.13-46.16 +Info: logic 0.18 5.38 Source rd_data_LUT4_Z_4.F +Info: routing 3.77 9.15 Net rd_data[2]$TRELLIS_IO_OUT (26,11) -> (15,71) +Info: Sink rd_data[2]$tr_io.I +Info: Defined in: +Info: hardware/v2/rtl/result_buffer.v:33.41-33.48 +Info: 4.44 ns logic, 4.71 ns routing + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 325.20 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.23 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 9.15 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 9425, 9544) |* +Info: [ 9544, 9663) | +Info: [ 9663, 9782) | +Info: [ 9782, 9901) | +Info: [ 9901, 10020) | +Info: [ 10020, 10139) | +Info: [ 10139, 10258) | +Info: [ 10258, 10377) | +Info: [ 10377, 10496) | +Info: [ 10496, 10615) | +Info: [ 10615, 10734) |*** +Info: [ 10734, 10853) |**** +Info: [ 10853, 10972) |************** +Info: [ 10972, 11091) |**** +Info: [ 11091, 11210) | +Info: [ 11210, 11329) |********* +Info: [ 11329, 11448) | +Info: [ 11448, 11567) |* +Info: [ 11567, 11686) |** +Info: [ 11686, 11805) |***** + +Info: Program finished normally. diff --git a/hardware/v2/synthesis/result_buffer_d4096/top.config b/hardware/v2/synthesis/result_buffer_d4096/top.config new file mode 100644 index 0000000..6a94c2e --- /dev/null +++ b/hardware/v2/synthesis/result_buffer_d4096/top.config @@ -0,0 +1,3388 @@ +.device LFE5U-45F + +.comment Part: LFE5U-45F-8CABGA381 + +.tile CIB_R10C13:CIB_EBR +arc: E3_H06E0003 W3_H06E0303 + +.tile CIB_R10C19:CIB_EBR +arc: E3_H06E0003 W3_H06E0003 + +.tile CIB_R10C1:CIB_LR_S +arc: E3_H06E0303 S3_V06N0303 + +.tile CIB_R10C25:CIB_EBR +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V06N0203 + +.tile CIB_R10C26:CIB_EBR +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V06S0203 +arc: H00L0100 V02S0301 +arc: H00R0000 V02N0601 +arc: H00R0100 V02S0701 +arc: JB5 H00R0000 +arc: JB7 V00B0000 +arc: JD4 H00R0100 +arc: JD6 H00L0100 +arc: N1_V02N0601 JQ4 +arc: S1_V02S0401 JQ6 +arc: S1_V02S0501 JQ5 +arc: V00B0000 V02N0001 +arc: V01S0000 JQ7 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JLSR1MUX 0 +enum: CIB.JCLK1MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 + +.tile CIB_R10C27:CIB_EBR +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0501 +arc: JA0 W1_H02E0701 +arc: JA1 H00R0000 +arc: JA2 S1_V02N0701 +arc: JA3 H02W0501 +arc: JA6 S1_V02N0301 +arc: JA7 H02W0701 +arc: JC0 H02W0401 +arc: JC1 H00R0100 +arc: JC2 V02N0601 +arc: JC3 V02N0401 +arc: JC6 V02N0001 +arc: JC7 V00B0100 +arc: JCLK0 G_HPBX0000 +arc: JLSR1 V00T0000 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 S1_V02N0601 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JCE1MUX 1 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 + +.tile CIB_R10C28:CIB_EBR +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02N0501 +arc: JA0 V02N0701 +arc: JA1 H00R0000 +arc: JA2 V00T0000 +arc: JA3 V02S0701 +arc: JA4 W1_H02E0701 +arc: JA5 W1_H02E0501 +arc: JC0 V02N0401 +arc: JC1 S1_V02N0601 +arc: JC2 N1_V01S0100 +arc: JC3 S1_V02N0401 +arc: JC4 H02W0601 +arc: JC5 H02E0401 +arc: JCLK0 G_HPBX0000 +arc: JD6 V00B0000 +arc: JD7 H00R0100 +arc: N1_V02N0501 JQ7 +arc: N1_V02N0601 E1_H01W0000 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 JQ6 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V01N0101 +enum: CIB.JB7MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JLSR1MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB5MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JCE1MUX 1 + +.tile CIB_R10C29:CIB_EBR +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 H02E0201 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0501 +arc: H01W0000 JQ0 +arc: H01W0100 JQ1 +arc: JA0 H00L0000 +arc: JA1 H00L0100 +arc: JA2 W1_H02E0701 +arc: JA3 H02E0501 +arc: JA6 V00T0100 +arc: JA7 H00R0000 +arc: JB1 W1_H02E0101 +arc: JC0 H02E0401 +arc: JC1 H00R0100 +arc: JC2 W1_H02E0601 +arc: JC3 S1_V02N0401 +arc: JC6 V02N0001 +arc: JC7 E1_H01E0101 +arc: JCLK0 G_HPBX0000 +arc: JD0 W1_H02E0201 +arc: JLSR1 W1_H02E0501 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E3_H06W0203 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JCE1MUX 1 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 + +.tile CIB_R10C30:CIB_EBR +arc: H00R0000 W1_H02E0601 +arc: JA0 H02W0701 +arc: JA1 S1_V02N0701 +arc: JA4 E1_H01W0000 +arc: JA5 V02N0101 +arc: JA6 H00R0000 +arc: JA7 W1_H02E0701 +arc: JC0 H02E0601 +arc: JC1 H02E0401 +arc: JC4 S1_V02N0001 +arc: JC5 H02W0401 +arc: JC6 V01N0101 +arc: JC7 S1_V02N0201 +arc: JCLK0 G_HPBX0000 +arc: W1_H02W0201 S1_V02N0201 +enum: CIB.JLSR1MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JCE1MUX 1 + +.tile CIB_R10C31:CIB_EBR +arc: H01W0000 W3_H06E0103 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 W3_H06E0203 + +.tile CIB_R10C35:CIB_EBR +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R10C41:CIB_EBR +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R10C47:CIB_EBR +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R10C53:CIB_EBR +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R10C59:CIB_EBR +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R10C65:CIB_EBR +arc: W3_H06W0103 E3_H06W0103 + +.tile CIB_R10C71:CIB_EBR +arc: W3_H06W0103 E3_H06W0103 + +.tile CIB_R10C77:CIB_EBR +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R10C7:CIB_EBR +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R10C83:CIB_EBR +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R10C89:CIB_LR_S +arc: W3_H06W0303 S3_V06N0303 + +.tile CIB_R11C1:CIB_LR +arc: E1_H01E0101 JQ5 +arc: E3_H06E0303 V06N0303 +arc: N3_V06N0303 JF5 +arc: S1_V02S0701 E3_H06W0203 + +.tile CIB_R11C89:CIB_LR +arc: JA3 W1_H02E0701 +arc: W3_H06W0303 JF5 +enum: CIB.JB3MUX 0 + +.tile CIB_R13C1:CIB_LR +arc: E3_H06E0303 JQ5 +arc: JA0 N1_V02S0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R13C89:CIB_LR +arc: W3_H06W0303 JF5 + +.tile CIB_R14C1:CIB_LR +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0303 JQ5 +arc: N3_V06N0303 JF5 +arc: S3_V06S0303 JF5 + +.tile CIB_R14C89:CIB_LR +arc: H01W0100 JQ5 +arc: S1_V02S0701 W3_H06E0203 +arc: W3_H06W0303 JF5 + +.tile CIB_R16C1:CIB_LR +arc: E3_H06E0303 JF5 +arc: N1_V02N0701 JQ5 +arc: N3_V06N0303 JF5 + +.tile CIB_R16C89:CIB_LR +arc: JA0 N1_V02S0701 +arc: N3_V06N0303 JQ5 +arc: S1_V02S0501 W3_H06E0303 +arc: W3_H06W0303 JQ5 +enum: CIB.JB0MUX 0 + +.tile CIB_R17C1:CIB_LR +arc: E1_H01E0101 JQ5 +arc: E3_H06E0303 V06S0303 +arc: S1_V02S0701 JF5 + +.tile CIB_R17C89:CIB_LR +arc: JA0 V02S0501 +arc: W3_H06W0303 JQ5 +enum: CIB.JB0MUX 0 + +.tile CIB_R18C1:CIB_LR +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 V01N0001 + +.tile CIB_R18C89:CIB_LR +arc: W3_H06W0103 V01N0101 + +.tile CIB_R19C1:CIB_LR +arc: E3_H06E0303 JF5 +arc: N1_V01N0001 JQ5 + +.tile CIB_R19C89:CIB_LR +arc: N1_V01N0101 JF5 +arc: W3_H06W0303 JQ5 + +.tile CIB_R1C24:CIB +arc: S3_V06S0003 JQ0 + +.tile CIB_R1C25:CIB +arc: S3_V06S0003 JQ0 +arc: S3_V06S0103 H06W0103 + +.tile CIB_R1C26:CIB +arc: S3_V06S0203 H06W0203 + +.tile CIB_R1C27:CIB +arc: S3_V06S0003 JQ0 +arc: S3_V06S0103 E1_H01W0100 + +.tile CIB_R1C28:CIB +arc: H01W0100 JQ0 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 H06W0203 +arc: W3_H06W0103 E1_H01W0100 + +.tile CIB_R1C29:CIB +arc: H01W0100 JQ0 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R1C30:CIB +arc: H01W0100 JQ0 +arc: S3_V06S0103 E3_H06W0103 + +.tile CIB_R1C31:CIB +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R1C32:CIB +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R1C35:CIB +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R1C36:CIB +arc: W3_H06W0103 E3_H06W0103 + +.tile CIB_R1C37:CIB +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R1C38:CIB +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R1C40:CIB +arc: E1_H02E0501 S1_V02N0501 + +.tile CIB_R1C41:CIB +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R1C42:CIB +arc: JA0 W1_H02E0501 +arc: W3_H06W0103 E3_H06W0003 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C43:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C44:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C45:CIB +arc: JA0 S1_V02N0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C46:CIB +arc: E1_H02E0001 S1_V02N0001 + +.tile CIB_R1C47:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C48:CIB +arc: JD7 W1_H02E0001 +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C50:CIB +arc: JA0 S1_V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R20C89:CIB_LR +arc: W3_H06W0303 JQ5 + +.tile CIB_R22C13:CIB_DSP +arc: E3_H06E0103 W3_H06E0003 + +.tile CIB_R22C19:CIB_DSP +arc: E3_H06E0103 W3_H06E0103 + +.tile CIB_R22C1:CIB_LR_S +arc: E3_H06E0303 JF5 + +.tile CIB_R22C25:CIB_DSP +arc: E3_H06E0203 W3_H06E0103 + +.tile CIB_R22C27:CIB_DSP +arc: N1_V02N0001 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 + +.tile CIB_R22C29:CIB_DSP +arc: N3_V06N0303 E3_H06W0303 + +.tile CIB_R22C31:CIB_DSP +arc: N1_V02N0401 W3_H06E0203 + +.tile CIB_R22C35:CIB_DSP +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C41:CIB_DSP +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R22C47:CIB_DSP +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R22C53:CIB_DSP +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R22C59:CIB_DSP +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R22C65:CIB_DSP +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R22C71:CIB_DSP +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R22C77:CIB_DSP +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R22C7:CIB_DSP +arc: E3_H06E0003 W3_H06E0303 + +.tile CIB_R22C83:CIB_DSP +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R22C89:CIB_LR_S +arc: W3_H06W0303 JQ5 + +.tile CIB_R34C27:CIB_EBR +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile CIB_R46C27:CIB_DSP +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 + +.tile CIB_R58C27:CIB_EBR +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile CIB_R5C1:CIB_PLL1 +arc: E3_H06E0303 S3_V06N0303 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C89:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C15:CIB +arc: E3_H06E0003 JQ0 + +.tile CIB_R70C16:CIB +arc: JA0 N1_V02S0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R70C18:CIB +arc: E3_H06E0003 JQ0 + +.tile CIB_R70C21:CIB +arc: E3_H06E0103 W3_H06E0003 + +.tile CIB_R70C24:CIB +arc: E3_H06E0003 W3_H06E0003 + +.tile CIB_R70C27:CIB +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 W3_H06E0103 + +.tile CIB_R70C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C42:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C43:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C44:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C45:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C46:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C47:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C48:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C49:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C50:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C51:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C52:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C53:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C69:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C70:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C71:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C72:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C73:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C74:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C75:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C76:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C77:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C78:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C79:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile CIB_R70C80:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C87:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile MIB_R0C24:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C25:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C27:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C28:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C29:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C30:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C40:TMID_0 +arc: G_TDCC0CLKI G_JTRQPCLKCIB1 + +.tile MIB_R0C42:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C43:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C44:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C45:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C47:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C48:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C50:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C87:BANKREF1 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C0:BANKREF7 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C30:EBR_SPINE_UL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C40:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_VPFS0000 + +.tile MIB_R10C41:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_VPFS0000 + +.tile MIB_R10C90:BANKREF2 +enum: BANK.VCCIO 3V3 + +.tile MIB_R11C0:PICL0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R11C90:PICR0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R12C0:PICL1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R12C90:PICR1 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R13C0:PICL2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R13C90:PICR2 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R14C0:PICL0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R14C90:PICR0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R15C0:PICL1_DQS0 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON + +.tile MIB_R15C90:PICR1_DQS0 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R16C0:PICL2_DQS1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R16C90:PICR2_DQS1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R17C0:PICL0_DQS2 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R17C90:PICR0_DQS2 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R18C0:PICL1_DQS3 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON + +.tile MIB_R18C90:PICR1_DQS3 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R19C0:PICL2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R19C90:PICR2 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C24:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C25:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C27:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C28:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C29:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C30:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C42:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C43:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C44:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C45:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C47:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C48:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C50:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R20C90:PICR0 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R21C0:PICL1 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON + +.tile MIB_R21C90:PICR1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R22C0:MIB_CIB_LR +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R22C90:MIB_CIB_LR_A +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R58C40:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_VPFS0000 + +.tile MIB_R58C41:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_VPFS0000 + +.tile MIB_R71C15:PICB0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R71C16:PICB1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R71C18:SPICB0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R71C3:BANKREF8 +enum: BANK.VCCIO 3V3 + +.tile MIB_R71C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile R11C13:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R11C14:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: S3_V06S0303 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 + +.tile R11C19:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R11C20:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R11C25:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0103 + +.tile R11C26:PLC2 +arc: E1_H02E0501 V02S0501 +arc: H00L0100 N1_V02S0301 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0201 S3_V06N0103 +arc: V00T0000 V02S0401 +arc: B3 H01W0100 +arc: B7 V00T0000 +arc: C3 H02W0601 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D3 N1_V01S0000 +arc: D7 H00R0100 +arc: E1_H02E0401 Q6 +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0100 Q1 +arc: M1 V01S0100 +arc: M2 E1_H02W0601 +arc: M6 H02E0401 +arc: M7 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0601 Q6 +arc: V01S0100 Q2 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F7 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICED.K1.INIT 1111110000001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R11C27:PLC2 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0601 S3_V06N0303 +arc: A3 H02E0501 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D3 V01S0100 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: H00R0100 Q5 +arc: M5 H00R0000 +arc: MUXCLK2 CLK0 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R11C28:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 H06E0203 +arc: S3_V06S0203 N1_V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0601 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: M7 H00R0100 +arc: MUXCLK3 CLK0 +arc: N1_V02N0501 Q7 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C29:PLC2 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 S1_V02N0601 + +.tile R11C2:PLC2 +arc: E3_H06E0303 H01E0101 + +.tile R11C30:PLC2 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 W1_H02E0101 + +.tile R11C31:PLC2 +arc: N1_V02N0401 W3_H06E0203 + +.tile R11C33:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R11C35:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R11C39:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R11C41:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C45:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R11C47:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C51:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R11C53:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C57:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R11C59:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C63:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R11C65:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C69:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R11C71:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C75:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R11C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R11C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: W3_H06W0203 E1_H01W0000 + +.tile R11C81:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R11C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R11C87:PLC2 +arc: E1_H02E0701 W3_H06E0203 + +.tile R11C8:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0000 E3_H06W0103 + +.tile R12C25:PLC2 +arc: E1_H02E0701 S1_V02N0701 + +.tile R12C27:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 W1_H02E0701 + +.tile R12C28:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: W1_H02W0301 S1_V02N0301 + +.tile R12C29:PLC2 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 S1_V02N0401 + +.tile R12C30:PLC2 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0701 H06E0203 + +.tile R13C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R13C19:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R13C25:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: N3_V06N0203 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 + +.tile R13C26:PLC2 +arc: N3_V06N0303 H01E0101 + +.tile R13C27:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 + +.tile R13C28:PLC2 +arc: N1_V02N0701 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 + +.tile R13C29:PLC2 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V01S0000 N3_V06S0103 + +.tile R13C30:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R13C35:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R13C41:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R13C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R13C53:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R13C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R13C65:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R13C71:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R13C77:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R13C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R13C83:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R14C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R14C15:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R14C19:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R14C21:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R14C25:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 + +.tile R14C27:PLC2 +arc: E1_H02E0601 W3_H06E0303 + +.tile R14C28:PLC2 +arc: N1_V02N0301 E3_H06W0003 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 E3_H06W0303 +arc: A6 V00T0100 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D6 S1_V02N0601 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R14C29:PLC2 +arc: N1_V02N0401 E3_H06W0203 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0003 N1_V01S0000 + +.tile R14C34:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R14C35:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R14C3:PLC2 +arc: E3_H06E0203 W1_H02E0701 + +.tile R14C40:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R14C41:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R14C46:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R14C47:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R14C52:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R14C53:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R14C58:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile R14C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R14C64:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 + +.tile R14C65:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R14C70:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0003 + +.tile R14C71:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R14C76:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0303 + +.tile R14C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R14C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R14C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: W3_H06W0303 E3_H06W0303 + +.tile R14C83:PLC2 +arc: E3_H06E0203 H01E0001 +arc: W3_H06W0003 E3_H06W0303 + +.tile R14C88:PLC2 +arc: W3_H06W0303 E1_H01W0100 + +.tile R14C9:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R15C27:PLC2 +arc: N3_V06N0103 S1_V02N0101 + +.tile R15C28:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N3_V06N0303 S1_V02N0501 + +.tile R16C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R16C19:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R16C25:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R16C27:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: N3_V06N0103 E1_H01W0100 + +.tile R16C28:PLC2 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H02W0701 +arc: V01S0000 N3_V06S0103 +arc: A0 H00L0100 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: H00L0100 Q3 +arc: H00R0100 Q7 +arc: H01W0100 Q7 +arc: M3 H00R0100 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R16C29:PLC2 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 N1_V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0701 E3_H06W0203 + +.tile R16C34:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R16C35:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R16C40:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R16C41:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R16C46:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R16C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R16C52:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R16C53:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R16C58:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R16C59:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R16C64:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R16C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R16C70:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R16C71:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R16C76:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R16C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R16C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R16C82:PLC2 +arc: E1_H01E0101 W3_H06E0203 + +.tile R16C83:PLC2 +arc: E3_H06E0303 H01E0101 +arc: W3_H06W0003 E3_H06W0303 + +.tile R17C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R17C14:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: S3_V06S0003 N3_V06S0303 + +.tile R17C19:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R17C20:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R17C25:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R17C26:PLC2 +arc: E1_H02E0401 W3_H06E0203 +arc: N3_V06N0103 E1_H01W0100 + +.tile R17C27:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: A1 H02W0701 +arc: A4 H02W0501 +arc: B1 V01N0001 +arc: B4 H02W0301 +arc: C1 F4 +arc: C4 E1_H02W0401 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: D4 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q4 +arc: E1_H02E0401 Q4 +arc: E3_H06E0203 Q4 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q5 +arc: M0 E1_H02W0601 +arc: M1 E1_H02W0001 +arc: M2 E1_H02W0601 +arc: M4 H02E0401 +arc: M5 V01S0000 +arc: MUXCLK2 CLK0 +arc: N3_V06N0303 Q5 +arc: S1_V02S0501 F7 +arc: V00B0000 Q4 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 1111001101010001 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0100000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C28:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0100 V02S0101 +arc: W1_H02W0501 V06S0303 +arc: A1 H02W0501 +arc: A6 N1_V01N0101 +arc: B1 Q1 +arc: B5 S1_V02N0701 +arc: B6 V02S0701 +arc: C1 V02S0601 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0201 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q4 +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q4 +arc: S1_V02S0401 Q4 +arc: V00B0000 F6 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +arc: W1_H02W0301 Q3 +arc: W1_H02W0701 F5 +word: SLICEC.K1.INIT 0011001100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111001101010001 +word: SLICED.K0.INIT 1010001011110011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R17C29:PLC2 +arc: H00R0100 H02E0701 +arc: S1_V02S0401 E3_H06W0203 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 N1_V01S0100 +arc: A3 V00T0000 +arc: B3 H00R0100 +arc: C3 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D3 V01S0100 +arc: F3 F3_SLICE +arc: H01W0100 Q0 +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +arc: N3_V06N0003 Q0 +arc: S1_V02S0301 F3 +arc: V01S0100 Q0 +word: SLICEB.K1.INIT 1111010100110001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R17C2:PLC2 +arc: E3_H06E0103 H01E0101 + +.tile R17C30:PLC2 +arc: N3_V06N0203 H06E0203 + +.tile R17C35:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R17C41:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R17C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R17C53:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R17C59:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R17C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R17C71:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R17C77:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R17C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R17C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R17C8:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R18C13:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R18C15:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R18C19:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R18C21:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R18C25:PLC2 +arc: E1_H02E0401 W3_H06E0203 + +.tile R18C27:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 E1_H01W0000 +arc: A3 V02N0701 +arc: B3 Q3 +arc: C3 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D3 H00R0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: M4 E1_H02W0401 +arc: M5 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F1 +arc: N3_V06N0003 Q3 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: V00B0100 Q5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000001001000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R18C28:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0000 S1_V02N0601 +arc: V00B0100 V02N0301 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A7 S1_V02N0301 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B7 S1_V02N0701 +arc: C0 S1_V02N0401 +arc: C2 S1_V02N0401 +arc: C4 Q4 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D7 V02S0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q6 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0000 F1 +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 H02E0401 +arc: M6 V00B0100 +arc: M7 H02W0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 Q4 +arc: N1_V02N0701 Q7 +arc: N3_V06N0003 Q3 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: V00B0000 Q6 +arc: V00T0100 Q3 +arc: V01S0000 Q7 +arc: V01S0100 Q3 +word: SLICED.K1.INIT 1000101011001111 +word: SLICEC.K0.INIT 0000110000001100 +word: SLICEA.K0.INIT 0000100000000010 +word: SLICEA.K1.INIT 1000100000100010 +word: SLICEB.K0.INIT 0000110000000011 +word: SLICEB.K1.INIT 1100110000110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C29:PLC2 +arc: H00L0100 V02S0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E3_H06W0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 H02E0501 +arc: B0 S1_V02N0301 +arc: C0 V02N0401 +arc: D0 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H01E0001 +arc: M1 H00L0100 +arc: M2 H02E0601 +arc: M3 H00R0100 +arc: M4 H02E0401 +arc: M5 H00L0100 +arc: M6 H02E0401 +arc: N1_V01N0001 F3 +word: SLICEA.K0.INIT 1100001101000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R18C35:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R18C3:PLC2 +arc: E3_H06E0203 W1_H02E0701 + +.tile R18C41:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R18C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R18C53:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R18C59:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R18C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R18C71:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R18C77:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R18C7:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R18C83:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R18C9:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R19C13:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R19C19:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R19C25:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0701 N3_V06S0203 + +.tile R19C27:PLC2 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 W1_H02E0701 + +.tile R19C28:PLC2 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 N3_V06S0203 + +.tile R19C29:PLC2 +arc: N1_V01N0001 N3_V06S0003 +arc: W1_H02W0301 E3_H06W0003 +arc: CLK0 G_HPBX0000 +arc: M6 E1_H02W0401 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 Q6 +arc: N3_V06N0303 Q6 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C30:PLC2 +arc: W1_H02W0601 N3_V06S0303 + +.tile R19C31:PLC2 +arc: W1_H02W0401 V02N0401 + +.tile R19C35:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R19C41:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R19C47:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R19C53:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R19C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R19C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R19C71:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R19C77:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R19C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R19C83:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R20C27:PLC2 +arc: N1_V02N0001 S1_V02N0001 + +.tile R20C28:PLC2 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N3_V06S0203 + +.tile R20C29:PLC2 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0301 N3_V06S0003 + +.tile R20C31:PLC2 +arc: N1_V02N0401 S1_V02N0401 + +.tile R20C35:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R20C41:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C47:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C53:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C59:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C65:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C71:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R23C14:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R26C39:PLC2 +word: SLICEC.K1.INIT 1111111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R28C27:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 + +.tile R28C28:PLC2 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R29C14:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R35C14:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R3C26:PLC2 +arc: E3_H06E0103 S3_V06N0103 + +.tile R3C28:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 S3_V06N0303 + +.tile R3C32:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R3C34:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 + +.tile R3C38:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R3C40:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0501 W3_H06E0303 + +.tile R3C44:PLC2 +arc: E1_H01E0101 W3_H06E0203 + +.tile R3C45:PLC2 +arc: N1_V02N0501 H01E0101 + +.tile R3C46:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0501 + +.tile R3C47:PLC2 +arc: E3_H06E0203 H01E0001 + +.tile R3C50:PLC2 +arc: N1_V02N0701 H06E0203 + +.tile R40C27:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R41C14:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R47C14:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R52C27:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 + +.tile R53C14:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R59C14:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R5C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R5C19:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R5C25:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R5C31:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R5C37:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R5C43:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R5C46:PLC2 +arc: N1_V02N0501 H06E0303 + +.tile R5C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R64C27:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R65C14:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R68C14:PLC2 +arc: E1_H02E0501 V06S0303 + +.tile R68C16:PLC2 +arc: S1_V02S0501 W1_H02E0501 + +.tile R7C24:PLC2 +arc: S1_V02S0001 N3_V06S0003 + +.tile R7C25:PLC2 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 + +.tile R7C26:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R7C27:PLC2 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 + +.tile R7C28:PLC2 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 + +.tile R7C29:PLC2 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 + +.tile R7C30:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R9C24:PLC2 +arc: E1_H02E0001 N1_V02S0001 + +.tile R9C25:PLC2 +arc: E1_H02E0001 N1_V02S0001 + +.tile R9C26:PLC2 +arc: H00L0000 H02E0001 +arc: B2 H01W0100 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D2 S1_V02N0201 +arc: F2 F2_SLICE +arc: H00R0100 Q7 +arc: H01W0100 Q5 +arc: M1 W1_H02E0001 +arc: M5 H00R0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 F2 +arc: S1_V02S0301 Q1 +arc: S1_V02S0701 Q7 +word: SLICEB.K0.INIT 1100110011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R9C27:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q0 +arc: M0 V00B0100 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V00B0100 Q5 +arc: V01S0000 Q5 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C28:PLC2 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0100 H02E0501 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: A3 V02N0501 +arc: A6 H02E0501 +arc: C3 H00L0000 +arc: C6 H01E0001 +arc: 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"CH0_TDRV_SLICE5_CUR": "DONTCARE", + "CH0_TDRV_SLICE5_SEL": "DONTCARE", + "CH0_TPWDNB": "DONTCARE", + "CH0_TXAMPLITUDE": "DONTCARE", + "CH0_TXDEPOST": "DONTCARE", + "CH0_TXDEPRE": "DONTCARE", + "CH0_TX_CM_SEL": "DONTCARE", + "CH0_TX_DIV11_SEL": "DONTCARE", + "CH0_TX_GEAR_BYPASS": "DONTCARE", + "CH0_TX_GEAR_MODE": "DONTCARE", + "CH0_TX_POST_SIGN": "DONTCARE", + "CH0_TX_PRE_SIGN": "DONTCARE", + "CH0_UC_MODE": "DONTCARE", + "CH0_UDF_COMMA_A": "DONTCARE", + "CH0_UDF_COMMA_B": "DONTCARE", + "CH0_UDF_COMMA_MASK": "DONTCARE", + "CH0_WA_BYPASS": "DONTCARE", + "CH0_WA_MODE": "DONTCARE", + "CH1_AUTO_CALIB_EN": "DONTCARE", + "CH1_AUTO_FACQ_EN": "DONTCARE", + "CH1_BAND_THRESHOLD": "DONTCARE", + "CH1_CALIB_CK_MODE": "DONTCARE", + "CH1_CC_MATCH_1": "DONTCARE", + "CH1_CC_MATCH_2": "DONTCARE", + "CH1_CC_MATCH_3": "DONTCARE", + "CH1_CC_MATCH_4": "DONTCARE", + "CH1_CDR_CNT4SEL": "DONTCARE", + "CH1_CDR_CNT8SEL": "DONTCARE", + "CH1_CDR_MAX_RATE": "DONTCARE", + "CH1_CTC_BYPASS": "DONTCARE", + "CH1_DCOATDCFG": "DONTCARE", + "CH1_DCOATDDLY": "DONTCARE", + "CH1_DCOBYPSATD": "DONTCARE", + "CH1_DCOCALDIV": "DONTCARE", + "CH1_DCOCTLGI": "DONTCARE", + "CH1_DCODISBDAVOID": "DONTCARE", + "CH1_DCOFLTDAC": "DONTCARE", + "CH1_DCOFTNRG": "DONTCARE", + "CH1_DCOIOSTUNE": "DONTCARE", + "CH1_DCOITUNE": "DONTCARE", + "CH1_DCOITUNE4LSB": "DONTCARE", + "CH1_DCOIUPDNX2": "DONTCARE", + "CH1_DCONUOFLSB": "DONTCARE", + "CH1_DCOSCALEI": "DONTCARE", + "CH1_DCOSTARTVAL": "DONTCARE", + "CH1_DCOSTEP": "DONTCARE", + "CH1_DEC_BYPASS": "DONTCARE", + "CH1_ENABLE_CG_ALIGN": "DONTCARE", + "CH1_ENC_BYPASS": "DONTCARE", + "CH1_FF_RX_F_CLK_DIS": "DONTCARE", + "CH1_FF_RX_H_CLK_EN": "DONTCARE", + "CH1_FF_TX_F_CLK_DIS": "DONTCARE", + "CH1_FF_TX_H_CLK_EN": "DONTCARE", + "CH1_GE_AN_ENABLE": "DONTCARE", + "CH1_INVERT_RX": "DONTCARE", + "CH1_INVERT_TX": "DONTCARE", + "CH1_LDR_CORE2TX_SEL": "DONTCARE", + "CH1_LDR_RX2CORE_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_TRIM": "DONTCARE", + "CH1_LSM_DISABLE": "DONTCARE", + "CH1_MATCH_2_ENABLE": "DONTCARE", + "CH1_MATCH_4_ENABLE": "DONTCARE", + "CH1_MIN_IPG_CNT": "DONTCARE", + "CH1_PCIE_EI_EN": "DONTCARE", + "CH1_PCIE_MODE": "DONTCARE", + "CH1_PCS_DET_TIME_SEL": "DONTCARE", + "CH1_PDEN_SEL": "DONTCARE", + "CH1_PRBS_ENABLE": "DONTCARE", + "CH1_PRBS_LOCK": "DONTCARE", + "CH1_PRBS_SELECTION": "DONTCARE", + "CH1_PROTOCOL": "DONTCARE", + "CH1_RATE_MODE_RX": "DONTCARE", + "CH1_RATE_MODE_TX": "DONTCARE", + "CH1_RCV_DCC_EN": "DONTCARE", + "CH1_REG_BAND_OFFSET": "DONTCARE", + "CH1_REG_BAND_SEL": "DONTCARE", + "CH1_REG_IDAC_EN": "DONTCARE", + "CH1_REG_IDAC_SEL": "DONTCARE", + "CH1_REQ_EN": "DONTCARE", + "CH1_REQ_LVL_SET": "DONTCARE", + "CH1_RIO_MODE": "DONTCARE", + "CH1_RLOS_SEL": "DONTCARE", + "CH1_RPWDNB": "DONTCARE", + "CH1_RTERM_RX": "DONTCARE", + "CH1_RTERM_TX": "DONTCARE", + "CH1_RXIN_CM": "DONTCARE", + "CH1_RXTERM_CM": "DONTCARE", + "CH1_RX_DCO_CK_DIV": "DONTCARE", + "CH1_RX_DIV11_SEL": "DONTCARE", + "CH1_RX_GEAR_BYPASS": "DONTCARE", + "CH1_RX_GEAR_MODE": "DONTCARE", + "CH1_RX_LOS_CEQ": "DONTCARE", + "CH1_RX_LOS_EN": "DONTCARE", + "CH1_RX_LOS_HYST_EN": "DONTCARE", + "CH1_RX_LOS_LVL": "DONTCARE", + "CH1_RX_RATE_SEL": "DONTCARE", + "CH1_RX_SB_BYPASS": "DONTCARE", + "CH1_SB_BYPASS": "DONTCARE", + "CH1_SEL_SD_RX_CLK": "DONTCARE", + "CH1_TDRV_DAT_SEL": "DONTCARE", + "CH1_TDRV_POST_EN": "DONTCARE", + "CH1_TDRV_PRE_EN": "DONTCARE", + "CH1_TDRV_SLICE0_CUR": "DONTCARE", + "CH1_TDRV_SLICE0_SEL": "DONTCARE", + "CH1_TDRV_SLICE1_CUR": "DONTCARE", + "CH1_TDRV_SLICE1_SEL": "DONTCARE", + "CH1_TDRV_SLICE2_CUR": "DONTCARE", + "CH1_TDRV_SLICE2_SEL": "DONTCARE", + "CH1_TDRV_SLICE3_CUR": "DONTCARE", + "CH1_TDRV_SLICE3_SEL": "DONTCARE", + "CH1_TDRV_SLICE4_CUR": "DONTCARE", + "CH1_TDRV_SLICE4_SEL": "DONTCARE", + "CH1_TDRV_SLICE5_CUR": "DONTCARE", + "CH1_TDRV_SLICE5_SEL": "DONTCARE", + "CH1_TPWDNB": "DONTCARE", + "CH1_TXAMPLITUDE": "DONTCARE", + "CH1_TXDEPOST": "DONTCARE", + "CH1_TXDEPRE": "DONTCARE", + "CH1_TX_CM_SEL": "DONTCARE", + "CH1_TX_DIV11_SEL": "DONTCARE", + "CH1_TX_GEAR_BYPASS": "DONTCARE", + "CH1_TX_GEAR_MODE": "DONTCARE", + "CH1_TX_POST_SIGN": "DONTCARE", + "CH1_TX_PRE_SIGN": "DONTCARE", + "CH1_UC_MODE": "DONTCARE", + "CH1_UDF_COMMA_A": "DONTCARE", + "CH1_UDF_COMMA_B": "DONTCARE", + "CH1_UDF_COMMA_MASK": "DONTCARE", + "CH1_WA_BYPASS": "DONTCARE", + "CH1_WA_MODE": "DONTCARE", + "D_BITCLK_FROM_ND_EN": "DONTCARE", + "D_BITCLK_LOCAL_EN": "DONTCARE", + "D_BITCLK_ND_EN": "DONTCARE", + "D_BUS8BIT_SEL": "DONTCARE", + "D_CDR_LOL_SET": "DONTCARE", + "D_CMUSETBIASI": "DONTCARE", + "D_CMUSETI4CPP": "DONTCARE", + "D_CMUSETI4CPZ": "DONTCARE", + "D_CMUSETI4VCO": "DONTCARE", + "D_CMUSETICP4P": "DONTCARE", + "D_CMUSETICP4Z": "DONTCARE", + "D_CMUSETINITVCT": "DONTCARE", + "D_CMUSETISCL4VCO": "DONTCARE", + "D_CMUSETP1GM": "DONTCARE", + "D_CMUSETP2AGM": "DONTCARE", + "D_CMUSETZGM": "DONTCARE", + "D_DCO_CALIB_TIME_SEL": "DONTCARE", + "D_HIGH_MARK": "DONTCARE", + "D_IB_PWDNB": "DONTCARE", + "D_ISETLOS": "DONTCARE", + "D_LOW_MARK": "DONTCARE", + "D_MACROPDB": "DONTCARE", + "D_PD_ISET": "DONTCARE", + "D_PLL_LOL_SET": "DONTCARE", + "D_REFCK_MODE": "DONTCARE", + "D_REQ_ISET": "DONTCARE", + "D_RG_EN": "DONTCARE", + "D_RG_SET": "DONTCARE", + "D_SETICONST_AUX": "DONTCARE", + "D_SETICONST_CH": "DONTCARE", + "D_SETIRPOLY_AUX": "DONTCARE", + "D_SETIRPOLY_CH": "DONTCARE", + "D_SETPLLRC": "DONTCARE", + "D_SYNC_LOCAL_EN": "DONTCARE", + "D_SYNC_ND_EN": "DONTCARE", + "D_TXPLL_PWDNB": "DONTCARE", + "D_TX_MAX_RATE": "DONTCARE", + "D_TX_VCO_CK_DIV": "DONTCARE", + "D_XGE_MODE": "DONTCARE" + }, + "ports": { + "CH0_HDINP": { + "direction": "input", + "bits": [ 2 ] + }, + "CH1_HDINP": { + "direction": "input", + "bits": [ 3 ] + }, + "CH0_HDINN": { + "direction": "input", + "bits": [ 4 ] + }, + "CH1_HDINN": { + "direction": "input", + "bits": [ 5 ] + }, + "D_TXBIT_CLKP_FROM_ND": { + "direction": "input", + "bits": [ 6 ] + }, + "D_TXBIT_CLKN_FROM_ND": { + "direction": "input", + "bits": [ 7 ] + }, + "D_SYNC_ND": { + "direction": "input", + "bits": [ 8 ] + }, + "D_TXPLL_LOL_FROM_ND": { + "direction": "input", + "bits": [ 9 ] + }, + "CH0_RX_REFCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "CH1_RX_REFCLK": { + "direction": "input", + "bits": [ 11 ] + }, + "CH0_FF_RXI_CLK": { + "direction": "input", + "bits": [ 12 ] + }, + "CH1_FF_RXI_CLK": { + "direction": "input", + "bits": [ 13 ] + }, + "CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 86 ] + }, + "CH1_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 87 ] + }, + "CH0_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 88 ] + }, + "CH1_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 89 ] + }, + "CH0_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 90 ] + }, + "CH1_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 91 ] + }, + "CH0_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 92 ] + }, + "CH1_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 93 ] + }, + "CH0_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 94 ] + }, + "CH1_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 95 ] + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 96 ] + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 97 ] + }, + "CH0_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 98 ] + }, + "CH1_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 99 ] + }, + "CH0_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 100 ] + }, + "CH1_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 101 ] + }, + "CH0_FFC_RRST": { + "direction": "input", + "bits": [ 102 ] + }, + "CH1_FFC_RRST": { + "direction": "input", + "bits": [ 103 ] + }, + "CH0_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 104 ] + }, + "CH1_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 105 ] + }, + "CH0_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 106 ] + }, + "CH1_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 107 ] + }, + "CH0_LDR_CORE2TX": { + "direction": "input", + "bits": [ 108 ] + }, + "CH1_LDR_CORE2TX": { + "direction": "input", + "bits": [ 109 ] + }, + "D_SCIWDATA0": { + "direction": "input", + "bits": [ 110 ] + }, + "D_SCIWDATA1": { + "direction": "input", + "bits": [ 111 ] + }, + "D_SCIWDATA2": { + "direction": "input", + "bits": [ 112 ] + }, + "D_SCIWDATA3": { + "direction": "input", + "bits": [ 113 ] + }, + "D_SCIWDATA4": { + "direction": "input", + "bits": [ 114 ] + }, + "D_SCIWDATA5": { + "direction": "input", + "bits": [ 115 ] + }, + "D_SCIWDATA6": { + "direction": "input", + "bits": [ 116 ] + }, + "D_SCIWDATA7": { + "direction": "input", + "bits": [ 117 ] + }, + "D_SCIADDR0": { + "direction": "input", + "bits": [ 118 ] + }, + "D_SCIADDR1": { + "direction": "input", + "bits": [ 119 ] + }, + "D_SCIADDR2": { + "direction": "input", + "bits": [ 120 ] + }, + "D_SCIADDR3": { + "direction": "input", + "bits": [ 121 ] + }, + "D_SCIADDR4": { + "direction": "input", + "bits": [ 122 ] + }, + "D_SCIADDR5": { + "direction": "input", + "bits": [ 123 ] + }, + "D_SCIENAUX": { + "direction": "input", + "bits": [ 124 ] + }, + "D_SCISELAUX": { + "direction": "input", + "bits": [ 125 ] + }, + "CH0_SCIEN": { + "direction": "input", + "bits": [ 126 ] + }, + "CH1_SCIEN": { + "direction": "input", + "bits": [ 127 ] + }, + "CH0_SCISEL": { + "direction": "input", + "bits": [ 128 ] + }, + "CH1_SCISEL": { + "direction": "input", + "bits": [ 129 ] + }, + "D_SCIRD": { + "direction": "input", + "bits": [ 130 ] + }, + "D_SCIWSTN": { + "direction": "input", + "bits": [ 131 ] + }, + "D_CYAWSTN": { + "direction": "input", + "bits": [ 132 ] + }, + "D_FFC_SYNC_TOGGLE": { + "direction": "input", + "bits": [ 133 ] + }, + "D_FFC_DUAL_RST": { + "direction": "input", + "bits": [ 134 ] + }, + "D_FFC_MACRO_RST": { + "direction": "input", + "bits": [ 135 ] + }, + "D_FFC_MACROPDB": { + "direction": "input", + "bits": [ 136 ] + }, + "D_FFC_TRST": { + "direction": "input", + "bits": [ 137 ] + }, + "CH0_FFC_CDR_EN_BITSLIP": { + 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"bits": [ 185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "mem.0.1_ADA11_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "mem.0.1_ADA11_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 34, 31, 46, 55, 168, 165, 162 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_ADA3": { + "hide_name": 0, + "bits": [ 25, 24, 49, 48 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_ADA5": { + "hide_name": 0, + "bits": [ 32, 27, 44, 51 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DIA0": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + } + }, + "mem.0.1_DIA1": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + } + }, + "mem.0.1_DIA2": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + } + }, + "mem.0.1_DIA3": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + } + }, + "mem.0.1_DOA3": { + "hide_name": 0, + "bits": [ 119, 120, 129, 130 ], + "attributes": { + "unused_bits": "0 1 2 3" + } + }, + "mem.0.1_DOA9": { + "hide_name": 0, + "bits": [ 119, 120, 129, 130, 131, 132, 133, 134, 135, 136, 121, 122, 123, 124, 125, 126, 127, 128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v:45.13-45.16", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" + } + }, + "mem.0.1_DOB0": { + "hide_name": 0, + "bits": [ 188, 137, 99 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB1": { + "hide_name": 0, + "bits": [ 138, 189, 99 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB2": { + "hide_name": 0, + "bits": [ 190, 147, 99 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB3": { + "hide_name": 0, + "bits": [ 148, 191, 99 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB9": { + "hide_name": 0, + "bits": [ 137, 138, 147, 148, 149, 150, 151, 152, 153, 154, 139, 140, 141, 142, 143, 144, 145, 146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v:46.13-46.16", + "unused_bits": "4 5 6 7 8 9 10 11 12 13 14 15 16 17" + } + }, + "rd_addr": { + "hide_name": 0, + "bits": [ 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35 ], + "attributes": { + "src": "hardware/v2/rtl/result_buffer.v:32.41-32.48" + } + }, + "rd_data": { + "hide_name": 0, + "bits": [ 36, 37, 38, 39, 40, 41, 42, 43 ], + "signed": 1, + "attributes": { + "src": "hardware/v2/rtl/result_buffer.v:33.41-33.48" + } + }, + "wr_addr": { + "hide_name": 0, + "bits": [ 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 ], + "attributes": { + "src": "hardware/v2/rtl/result_buffer.v:29.41-29.48" + } + }, + "wr_addr_TRELLIS_FF_DI_Q": { + "hide_name": 0, + "bits": [ 30, 29, 26, 54, 53, 50 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "wr_data": { + "hide_name": 0, + "bits": [ 16, 17, 18, 19, 20, 21, 22, 23 ], + "signed": 1, + "attributes": { + "src": "hardware/v2/rtl/result_buffer.v:30.41-30.48" + } + }, + "wr_en": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "hardware/v2/rtl/result_buffer.v:28.41-28.46" + } + }, + "wr_en_TRELLIS_FF_DI_Q": { + "hide_name": 0, + "bits": [ 35, 28, 47, 52, 96, 179 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + } + } + } + } +} diff --git a/hardware/v2/synthesis/result_buffer_d4096/yosys.log b/hardware/v2/synthesis/result_buffer_d4096/yosys.log new file mode 100644 index 0000000..495b477 --- /dev/null +++ b/hardware/v2/synthesis/result_buffer_d4096/yosys.log @@ -0,0 +1,1175 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) + +-- Parsing `hardware/v2/rtl/result_buffer.v' using frontend ` -vlog2k' -- + +1. Executing Verilog-2005 frontend: hardware/v2/rtl/result_buffer.v +Parsing Verilog input from `hardware/v2/rtl/result_buffer.v' to AST representation. +Storing AST representation for module `$abstract\result_buffer'. +Successfully finished Verilog frontend. + +-- Running command `synth_ecp5 -json hardware/v2/synthesis/result_buffer_d4096/top.json -top result_buffer' -- + +2. Executing SYNTH_LATTICE pass. + +2.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +2.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +2.3. Executing HIERARCHY pass (managing design hierarchy). + +2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\result_buffer'. +Generating RTLIL representation for module `\result_buffer'. + +2.4.1. Analyzing design hierarchy.. +Top module: \result_buffer + +2.4.2. Analyzing design hierarchy.. +Top module: \result_buffer +Removing unused module `$abstract\result_buffer'. +Removed 1 unused modules. + +2.5. Executing PROC pass (convert processes to netlists). + +2.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +2.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/result_buffer.v:38$227 in module result_buffer. +Removed a total of 0 dead cases. + +2.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 4 assignments to connections. + +2.5.4. Executing PROC_INIT pass (extract init attributes). + +2.5.5. Executing PROC_ARST pass (detect async resets in processes). + +2.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +2.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:43$234'. +Creating decoders for process `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:38$227'. + 1/3: $1$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_EN[7:0]$233 + 2/3: $1$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_DATA[7:0]$232 + 3/3: $1$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_ADDR[11:0]$231 + +2.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +2.5.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\result_buffer.\rd_data' using process `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:43$234'. + created $dff cell `$procdff$245' with positive edge clock. +Creating register for signal `\result_buffer.$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_ADDR' using process `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:38$227'. + created $dff cell `$procdff$246' with positive edge clock. +Creating register for signal `\result_buffer.$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_DATA' using process `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:38$227'. + created $dff cell `$procdff$247' with positive edge clock. +Creating register for signal `\result_buffer.$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_EN' using process `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:38$227'. + created $dff cell `$procdff$248' with positive edge clock. + +2.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +2.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `result_buffer.$proc$hardware/v2/rtl/result_buffer.v:43$234'. +Found and cleaned up 1 empty switch in `\result_buffer.$proc$hardware/v2/rtl/result_buffer.v:38$227'. +Removing empty process `result_buffer.$proc$hardware/v2/rtl/result_buffer.v:38$227'. +Cleaned up 1 empty switch. + +2.5.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.6. Executing CHECK pass (checking for obvious problems). +Checking module result_buffer... +Found and reported 0 problems. + +2.7. Executing FLATTEN pass (flatten design). + +2.8. Executing TRIBUF pass. + +2.9. Executing DEMINOUT pass (demote inout ports to input or output). + +2.10. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.11. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. +Removed 3 unused cells and 13 unused wires. + + +2.12. Executing CHECK pass (checking for obvious problems). +Checking module result_buffer... +Found and reported 0 problems. + +2.13. Executing OPT pass (performing simple optimizations). + +2.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \result_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \result_buffer. + Consolidated identical input bits for $mux cell $procmux$237: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_EN[7:0]$230 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_EN[7:0]$230 [0] + New connections: $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_EN[7:0]$230 [7:1] = { $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_EN[7:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_EN[7:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_EN[7:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_EN[7:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_EN[7:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_EN[7:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/result_buffer.v:40$226_EN[7:0]$230 [0] } + Optimizing cells in module \result_buffer. +Performed a total of 1 changes. + +2.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +2.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \result_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \result_buffer. +Performed a total of 0 changes. + +2.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +2.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.13.16. Finished fast OPT passes. (There is nothing left to do.) + +2.14. Executing FSM pass (extract and optimize FSM). + +2.14.1. Executing FSM_DETECT pass (finding FSMs in design). + +2.14.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +2.14.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +2.14.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +2.14.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +2.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +2.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +2.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +2.15. Executing OPT pass (performing simple optimizations). + +2.15.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.15.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \result_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \result_buffer. +Performed a total of 0 changes. + +2.15.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.15.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +2.15.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.15.9. Finished fast OPT passes. (There is nothing left to do.) + +2.16. Executing WREDUCE pass (reducing word size of cells). + +2.17. Executing PEEPOPT pass (run peephole optimizers). + +2.18. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +2.19. Executing SHARE pass (SAT-based resource sharing). + +2.20. Executing TECHMAP pass (map to technology primitives). + +2.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +2.20.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.21. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.22. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +2.23. Executing TECHMAP pass (map to technology primitives). + +2.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +2.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.24. Executing TECHMAP pass (map to technology primitives). + +2.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +2.24.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.25. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module result_buffer: + created 0 $alu and 0 $macc cells. + +2.26. Executing OPT pass (performing simple optimizations). + +2.26.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.26.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \result_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \result_buffer. +Performed a total of 0 changes. + +2.26.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 6 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.26.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.26.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +2.26.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.26.9. Finished fast OPT passes. (There is nothing left to do.) + +2.27. Executing MEMORY pass. + +2.27.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +2.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +2.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing result_buffer.mem write port 0. + +2.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +2.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\mem'[0] in module `\result_buffer': merging output FF to cell. + Write port 0: non-transparent. + +2.27.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. +Removed 1 unused cells and 9 unused wires. + + +2.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +2.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +2.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +2.27.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +2.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +2.29. Executing MEMORY_LIBMAP pass (mapping memories to cells). +mapping memory result_buffer.mem via $__DP16KD_ + + +2.30. Executing TECHMAP pass (map to technology primitives). + +2.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +2.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +2.30.3. Continuing TECHMAP pass. +Using template $paramod$c4aea9a221b3d95ca47d9df3d018cdac65e6baac$__DP16KD_ for cells of type $__DP16KD_. +No more expansions possible. + + +2.31. Executing OPT pass (performing simple optimizations). + +2.31.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + + +2.31.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 10 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.31.3. Executing OPT_DFF pass (perform DFF optimizations). +Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$267 ($dffe) from module result_buffer. + +2.31.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. +Removed 0 unused cells and 51 unused wires. + + +2.31.5. Rerunning OPT passes. (Removed registers in this run.) + +2.31.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.31.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 10 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.31.8. Executing OPT_DFF pass (perform DFF optimizations). + +2.31.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +2.31.10. Finished fast OPT passes. + +2.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +2.33. Executing OPT pass (performing simple optimizations). + +2.33.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.33.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 10 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \result_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \result_buffer. +Performed a total of 0 changes. + +2.33.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 10 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.33.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +2.33.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.33.9. Finished fast OPT passes. (There is nothing left to do.) + +2.34. Executing TECHMAP pass (map to technology primitives). + +2.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +2.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +2.34.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $eq. +No more expansions possible. + + +2.35. Executing OPT pass (performing simple optimizations). + +2.35.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.35.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 65 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.35.3. Executing OPT_DFF pass (perform DFF optimizations). + +2.35.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. +Removed 0 unused cells and 1 unused wires. + + +2.35.5. Finished fast OPT passes. + +2.36. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. + +2.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +2.38. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\result_buffer'. +Computing hashes of 65 cells of `\result_buffer'. +Finding duplicate cells in `\result_buffer'. +Removed a total of 0 cells. + +2.39. Executing TECHMAP pass (map to technology primitives). + +2.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +2.39.2. Continuing TECHMAP pass. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +No more expansions possible. + + +2.40. Executing OPT_EXPR pass (perform const folding). +Optimizing module result_buffer. + +2.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +2.42. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in result_buffer. + +2.43. Executing ATTRMVCP pass (move or copy attributes). + +2.44. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \result_buffer.. +Removed 0 unused cells and 120 unused wires. + + +2.45. Executing CHECK pass (checking for obvious problems). +Checking module result_buffer... +Found and reported 0 problems. + +2.46. Executing TECHMAP pass (map to technology primitives). + +2.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +2.46.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.47. Executing ABC9 pass. + +2.47.1. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.2. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module result_buffer. +Found 0 SCCs. + +2.47.4. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.5. Executing TECHMAP pass (map to technology primitives). + +2.47.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +2.47.5.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.47.6. Executing OPT pass (performing simple optimizations). + +2.47.6.1. Executing OPT_EXPR pass (perform const folding). + +2.47.6.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +2.47.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +2.47.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +2.47.6.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +2.47.6.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.47.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +2.47.6.8. Executing OPT_EXPR pass (perform const folding). + +2.47.6.9. Finished fast OPT passes. (There is nothing left to do.) + +2.47.7. Executing TECHMAP pass (map to technology primitives). + +2.47.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +2.47.7.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.47.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +2.47.9. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.10. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +2.47.12. Executing AIGMAP pass (map logic to AIG). +Module result_buffer: replaced 31 cells with 184 new cells, skipped 34 cells. + replaced 3 cell types: + 8 $_MUX_ + 11 $_OR_ + 12 $_XOR_ + not replaced 4 cell types: + 1 $_AND_ + 1 $_NOT_ + 30 TRELLIS_FF + 2 DP16KD + +2.47.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.12.2. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.12.3. Executing XAIGER backend. + +Extracted 72 AND gates and 260 wires from module `result_buffer' to a netlist network with 72 inputs and 30 outputs. + +2.47.12.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +2.47.12.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 72/ 30 and = 72 lev = 7 (0.77) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 72/ 30 and = 99 lev = 6 (0.73) mem = 0.00 MB ch = 9 box = 0 bb = 0 +ABC: cst = 0 cls = 9 lit = 9 unused = 153 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 99. Ch = 9. Total mem = 0.03 MB. Peak cut mem = 0.01 MB. +ABC: P: Del = 1756.00. Ar = 43.0. Edge = 76. Cut = 391. T = 0.00 sec +ABC: P: Del = 1756.00. Ar = 43.0. Edge = 76. Cut = 390. T = 0.00 sec +ABC: P: Del = 1756.00. Ar = 37.0. Edge = 76. Cut = 505. T = 0.00 sec +ABC: F: Del = 1756.00. Ar = 37.0. Edge = 76. Cut = 348. T = 0.00 sec +ABC: A: Del = 1756.00. Ar = 37.0. Edge = 76. Cut = 347. T = 0.00 sec +ABC: A: Del = 1756.00. Ar = 37.0. Edge = 76. Cut = 342. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: Timing manager is given but there is no GIA of boxes. +ABC: Error: Abc_FrameUpdateGia(): Transformation has failed. +ABC: + &ps -l +ABC: /input : i/o = 72/ 30 and = 72 lev = 6 (0.73) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=7) : lut = 20 edge = 76 lev = 3 (0.37) mem = 0.00 MB +ABC: LUT = 20 : 2=3 15.0 % 3=8 40.0 % 4=4 20.0 % 5=1 5.0 % 6=3 15.0 % 7=1 5.0 % Ave = 3.80 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.00 sec +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +2.47.12.6. Executing AIGER frontend. + +Removed 119 unused cells and 200 unused wires. + +2.47.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 20 +ABC RESULTS: input signals: 8 +ABC RESULTS: output signals: 5 + +Removing temp directory. + +2.47.13. Executing TECHMAP pass (map to technology primitives). + +2.47.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +2.47.13.2. Continuing TECHMAP pass. +No more expansions possible. + +Removed 8 unused cells and 290 unused wires. + +2.48. Executing TECHMAP pass (map to technology primitives). + +2.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +2.48.2. Continuing TECHMAP pass. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de$lut for cells of type $lut. +Using template $paramod$fe6a5d9c4f188f47ec07e4f5827baa5f3bf54c47$lut for cells of type $lut. +Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673$lut for cells of type $lut. +Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. +Using template $paramod$96f88ffdf52d3059c17d970c5fe3f19815bfce25$lut for cells of type $lut. +Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86$lut for cells of type $lut. +Using template $paramod$233b70872b0d11ad6386b65bc4d8864ac02395bb$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$977bf81c91b9e0cdfe901822d1642d278c1b0ecd$lut for cells of type $lut. +Using template $paramod$a7dad16c080c08c1647c7e1b9706a59a123d8bcd$lut for cells of type $lut. +No more expansions possible. + + +2.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in result_buffer. + Optimizing lut $abc$1122$lut$aiger$o2.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger$o2.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$90.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$1122$lut$aiger1121$100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$83.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$1122$lut$aiger1121$90.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$1122$lut$aiger1121$90.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$1122$lut$aiger$o2.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) +Removed 0 unused cells and 51 unused wires. + +2.50. Executing AUTONAME pass. +Renamed 149 objects in module result_buffer. + + +2.51. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `result_buffer'. Setting top module to result_buffer. + +2.51.1. Analyzing design hierarchy.. +Top module: \result_buffer + +2.51.2. Analyzing design hierarchy.. +Top module: \result_buffer +Removed 0 unused modules. + +2.52. Printing statistics. + +=== result_buffer === + + +----------Local Count, excluding submodules. + | + 71 wires + 229 wire bits + 71 public wires + 229 public wire bits + 6 ports + 42 port bits + 2 cells + 2 DP16KD + 84 submodules + 6 L6MUX21 + 37 LUT4 + 11 PFUMX + 30 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + 2 result_buffer + + +----------Count including submodules. + | + 71 wires + 229 wire bits + 71 public wires + 229 public wire bits + 6 ports + 42 port bits + - memories + - memory bits + - processes + 2 cells + 2 DP16KD + 84 submodules + 6 L6MUX21 + 37 LUT4 + 11 PFUMX + 30 TRELLIS_FF + +2.53. Executing CHECK pass (checking for obvious problems). +Checking module result_buffer... +Found and reported 0 problems. + +2.54. Executing JSON backend. + +End of script. Logfile hash: dfb30af4ca, time: 0.30s, user: 0.27s, system: 0.01s, MEM: 30.16 MB peak +Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) +Time spent: 55% 20x read_verilog (0 sec), 24% 11x techmap (0 sec), ... diff --git a/hardware/v2/synthesis/weight_buffer_d512/nextpnr.log b/hardware/v2/synthesis/weight_buffer_d512/nextpnr.log new file mode 100644 index 0000000..5be8f53 --- /dev/null +++ b/hardware/v2/synthesis/weight_buffer_d512/nextpnr.log @@ -0,0 +1,215 @@ + + +Info: Logic utilisation before packing: +Info: Total LUT4s: 88/43848 0% +Info: logic LUTs: 88/43848 0% +Info: carry LUTs: 0/43848 0% +Info: RAM LUTs: 0/ 5481 0% +Info: RAMW LUTs: 0/10962 0% + +Info: Total DFFs: 139/43848 0% + +Info: Packing IOs.. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 1 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0x8d179719 + +Info: Device utilisation: +Info: TRELLIS_IO: 148/ 245 60% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 2/ 108 1% +Info: MULT18X18D: 0/ 72 0% +Info: ALU54B: 0/ 36 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 160 0% +Info: SIOLOGIC: 0/ 85 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 10 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 139/ 43848 0% +Info: TRELLIS_COMB: 90/ 43848 0% +Info: TRELLIS_RAMW: 0/ 5481 0% + +Info: Placed 0 cells based on constraints. +Info: Creating initial analytic placement for 214 cells, random placement wirelen = 21853. +Info: at initial placer iter 0, wirelen = 8761 +Info: at initial placer iter 1, wirelen = 8682 +Info: at initial placer iter 2, wirelen = 8664 +Info: at initial placer iter 3, wirelen = 8654 +Info: Running main analytical placer, max placement attempts per cell = 18050. +Info: at iteration #1, type ALL: wirelen solved = 8649, spread = 9182, legal = 10156; time = 0.00s +Info: HeAP Placer Time: 0.02s +Info: of which solving equations: 0.00s +Info: of which spreading cells: 0.00s +Info: of which strict legalisation: 0.00s + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 85, wirelen = 10156 +Info: at iteration #5: temp = 0.000000, timing cost = 31, wirelen = 8157 +Info: at iteration #10: temp = 0.000000, timing cost = 12, wirelen = 8054 +Info: at iteration #13: temp = 0.000000, timing cost = 10, wirelen = 7961 +Info: SA placement time 0.03s + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 366.57 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.42 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 10.27 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 9772, 9871) |* +Info: [ 9871, 9970) | +Info: [ 9970, 10069) |* +Info: [ 10069, 10168) | +Info: [ 10168, 10267) |*** +Info: [ 10267, 10366) |** +Info: [ 10366, 10465) |** +Info: [ 10465, 10564) |******* +Info: [ 10564, 10663) |**** +Info: [ 10663, 10762) |************* +Info: [ 10762, 10861) |***** +Info: [ 10861, 10960) |****** +Info: [ 10960, 11059) |********** +Info: [ 11059, 11158) |******* +Info: [ 11158, 11257) |*************** +Info: [ 11257, 11356) |****** +Info: [ 11356, 11455) |************************* +Info: [ 11455, 11554) |********** +Info: [ 11554, 11653) |************* +Info: [ 11653, 11752) |************************* +Info: Checksum: 0x6f062bf9 +Info: Routing globals... +Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 568 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 586 | 18 560 | 18 560 | 0| 0.09 0.09| +Info: Routing complete. +Info: Router1 time 0.09s +Info: Checksum: 0x1cfed5f0 + +Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source mem.0.0_ADA8_TRELLIS_FF_Q.Q +Info: routing 0.67 1.06 Net mem.0.0_ADA8[1] (41,26) -> (41,27) +Info: Sink wr_en_TRELLIS_FF_DI_Q_LUT4_Z.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 1.24 Source wr_en_TRELLIS_FF_DI_Q_LUT4_Z.F +Info: routing 0.56 1.80 Net wr_en_TRELLIS_FF_DI_Q[6] (41,27) -> (40,28) +Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.19 2.00 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.65 2.65 Net mem.0.0_ADA5_LUT4_D_Z[2] (40,28) -> (40,26) +Info: Sink mem.0.0_DOA0_TRELLIS_FF_Q_1_DI_LUT4_Z.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 2.83 Source mem.0.0_DOA0_TRELLIS_FF_Q_1_DI_LUT4_Z.F +Info: routing 0.12 2.94 Net mem.0.0_DOA0_TRELLIS_FF_Q_1_DI (40,26) -> (40,26) +Info: Sink mem.0.0_DOA0_TRELLIS_FF_Q_1.DI +Info: setup 0.00 2.94 Source mem.0.0_DOA0_TRELLIS_FF_Q_1.DI +Info: 0.95 ns logic, 2.00 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': +Info: type curr total name +Info: source 0.00 0.00 Source rd_addr[6]$tr_io.O +Info: routing 4.15 4.15 Net rd_addr[6]$TRELLIS_IO_IN (13,71) -> (41,25) +Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.A +Info: Defined in: +Info: hardware/v2/rtl/weight_buffer.v:33.48-33.55 +Info: logic 0.18 4.33 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.F +Info: routing 0.00 4.33 Net mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT (41,25) -> (41,25) +Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.F1 +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24 +Info: logic 0.13 4.45 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 0.00 4.45 Net mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 (41,25) -> (41,25) +Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXA +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52 +Info: logic 0.18 4.63 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.00 4.63 Net mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0 (41,25) -> (41,25) +Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68 +Info: logic 0.18 4.81 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.52 5.34 Net mem.0.0_ADA5_LUT4_D_Z[3] (41,25) -> (40,26) +Info: Sink mem.0.0_DOA0_TRELLIS_FF_Q_1_DI_LUT4_Z.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 5.52 Source mem.0.0_DOA0_TRELLIS_FF_Q_1_DI_LUT4_Z.F +Info: routing 0.12 5.63 Net mem.0.0_DOA0_TRELLIS_FF_Q_1_DI (40,26) -> (40,26) +Info: Sink mem.0.0_DOA0_TRELLIS_FF_Q_1.DI +Info: setup 0.00 5.63 Source mem.0.0_DOA0_TRELLIS_FF_Q_1.DI +Info: 0.84 ns logic, 4.79 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': +Info: type curr total name +Info: clk-to-q 4.26 4.26 Source mem.0.0.DOB10 +Info: routing 1.07 5.33 Net mem.0.0_DOB10[0] (37,34) -> (37,35) +Info: Sink rd_data_LUT4_Z_30.B +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 5.51 Source rd_data_LUT4_Z_30.F +Info: routing 3.27 8.78 Net rd_data[28]$TRELLIS_IO_OUT (37,35) -> (67,0) +Info: Sink rd_data[28]$tr_io.I +Info: Defined in: +Info: hardware/v2/rtl/weight_buffer.v:34.48-34.55 +Info: 4.44 ns logic, 4.33 ns routing + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 339.67 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.63 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 8.78 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 9556, 9668) |* +Info: [ 9668, 9780) | +Info: [ 9780, 9892) | +Info: [ 9892, 10004) | +Info: [ 10004, 10116) | +Info: [ 10116, 10228) | +Info: [ 10228, 10340) | +Info: [ 10340, 10452) | +Info: [ 10452, 10564) | +Info: [ 10564, 10676) |**** +Info: [ 10676, 10788) |***** +Info: [ 10788, 10900) |***** +Info: [ 10900, 11012) |************************ +Info: [ 11012, 11124) |******************** +Info: [ 11124, 11236) |*************** +Info: [ 11236, 11348) |***************** +Info: [ 11348, 11460) |*********** +Info: [ 11460, 11572) |************* +Info: [ 11572, 11684) |*********** +Info: [ 11684, 11796) |***************************** + +Info: Program finished normally. diff --git a/hardware/v2/synthesis/weight_buffer_d512/top.config b/hardware/v2/synthesis/weight_buffer_d512/top.config new file mode 100644 index 0000000..369f9f8 --- /dev/null +++ b/hardware/v2/synthesis/weight_buffer_d512/top.config @@ -0,0 +1,8923 @@ +.device LFE5U-45F + +.comment Part: LFE5U-45F-8CABGA381 + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R10C49:CIB_EBR +arc: N3_V06N0203 S3_V06N0103 + +.tile CIB_R17C89:CIB_LR +arc: W3_H06W0303 JQ5 + +.tile CIB_R19C1:CIB_LR +arc: S1_V02S0501 S3_V06N0303 + +.tile CIB_R1C17:CIB +arc: E1_H02E0501 S1_V02N0501 + +.tile CIB_R1C18:CIB +arc: JA0 H02W0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C19:CIB +arc: JA0 W1_H02E0501 +arc: W1_H02W0701 S1_V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C20:CIB +arc: E3_H06E0003 JQ0 + +.tile CIB_R1C21:CIB +arc: E3_H06E0003 JQ0 + +.tile CIB_R1C22:CIB +arc: JA0 E1_H02W0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C23:CIB +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 JQ0 + +.tile CIB_R1C24:CIB +arc: JA0 H02E0701 +arc: W1_H02W0701 V06N0203 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C25:CIB +arc: E3_H06E0003 JQ0 + +.tile CIB_R1C26:CIB +arc: E3_H06E0103 W3_H06E0003 + +.tile CIB_R1C27:CIB +arc: E1_H01E0001 JQ0 +arc: E3_H06E0003 W3_H06E0003 + +.tile CIB_R1C28:CIB +arc: E3_H06E0003 JQ0 +arc: E3_H06E0203 H01E0001 + +.tile CIB_R1C29:CIB +arc: E3_H06E0003 JQ0 +arc: E3_H06E0103 W3_H06E0003 + +.tile CIB_R1C30:CIB +arc: E1_H02E0501 S3_V06N0303 +arc: JA0 H02W0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C31:CIB +arc: E1_H01E0101 JQ0 +arc: E3_H06E0003 W3_H06E0003 +arc: W1_H02W0701 V02N0701 + +.tile CIB_R1C32:CIB +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 W3_H06E0103 +arc: JA0 W1_H02E0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C33:CIB +arc: E3_H06E0103 W3_H06E0003 +arc: JA0 E1_H02W0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C34:CIB +arc: E3_H06E0003 W3_H06E0003 +arc: S3_V06S0003 JQ0 +arc: S3_V06S0203 W3_H06E0203 + +.tile CIB_R1C35:CIB +arc: E3_H06E0103 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0701 S1_V02N0701 + +.tile CIB_R1C36:CIB +arc: S3_V06S0003 JQ0 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 E1_H01W0100 + +.tile CIB_R1C37:CIB +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0003 W3_H06E0003 +arc: H01W0100 JQ0 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 + +.tile CIB_R1C38:CIB +arc: E3_H06E0103 W3_H06E0103 +arc: JA0 H02W0501 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 H06W0303 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C39:CIB +arc: JA0 W1_H02E0701 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 E3_H06W0203 +arc: W1_H02W0501 S1_V02N0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C40:CIB +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R1C41:CIB +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R1C42:CIB +arc: E1_H02E0501 V01N0101 +arc: H01W0100 JQ0 +arc: S1_V02S0001 JQ0 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 + +.tile CIB_R1C43:CIB +arc: E1_H02E0501 V01N0101 +arc: H01W0000 JQ0 +arc: S3_V06S0003 H06W0003 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R1C44:CIB +arc: JA0 W1_H02E0501 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C45:CIB +arc: JA0 W1_H02E0501 +arc: S3_V06S0303 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C46:CIB +arc: S3_V06S0203 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R1C47:CIB +arc: H01W0100 JQ0 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R1C48:CIB +arc: JD7 E1_H01W0100 +arc: W3_H06W0003 JQ0 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R1C49:CIB +arc: E1_H02E0501 V06N0303 +arc: H01W0100 E3_H06W0303 +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C50:CIB +arc: JA0 H02E0501 +arc: W3_H06W0203 E3_H06W0103 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C51:CIB +arc: JA0 H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C52:CIB +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 JQ0 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E1_H01W0000 + +.tile CIB_R1C53:CIB +arc: H01W0000 JQ0 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R1C54:CIB +arc: JA0 V02N0701 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0203 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C55:CIB +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R1C56:CIB +arc: H01W0100 JQ0 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R1C57:CIB +arc: E1_H02E0701 S1_V02N0701 +arc: W3_H06W0003 JQ0 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R1C58:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C59:CIB +arc: JA0 W1_H02E0701 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C60:CIB +arc: JA0 H02W0501 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C61:CIB +arc: JA0 V02N0501 +arc: W1_H02W0501 S1_V02N0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C62:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C63:CIB +arc: W3_H06W0003 JQ0 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R1C65:CIB +arc: W3_H06W0003 JQ0 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R1C66:CIB +arc: W3_H06W0003 JQ0 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R1C67:CIB +arc: E1_H02E0701 S3_V06N0203 +arc: JA0 S1_V02N0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C68:CIB +arc: JA0 H02E0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C69:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C70:CIB +arc: JA0 S1_V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C71:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C72:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C73:CIB +arc: E1_H02E0501 V02N0501 + +.tile CIB_R1C75:CIB +arc: JA0 W1_H02E0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R20C1:CIB_LR +arc: JA0 E1_H02W0701 +arc: JA3 V02S0501 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R20C89:CIB_LR +arc: S3_V06S0303 JF5 +arc: W3_H06W0303 JQ5 + +.tile CIB_R22C13:CIB_DSP +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R22C19:CIB_DSP +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R22C1:CIB_LR_S +arc: E3_H06E0303 JQ5 +arc: S3_V06S0303 JF5 + +.tile CIB_R22C25:CIB_DSP +arc: E3_H06E0003 W3_H06E0303 + +.tile CIB_R22C31:CIB_DSP +arc: E3_H06E0103 W3_H06E0003 + +.tile CIB_R22C37:CIB_DSP +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 S3_V06N0303 +arc: S3_V06S0103 W3_H06E0103 + +.tile CIB_R22C41:CIB_DSP +arc: S3_V06S0103 E3_H06W0103 + +.tile CIB_R22C43:CIB_DSP +arc: E3_H06E0003 W3_H06E0303 +arc: S3_V06S0203 W3_H06E0203 + +.tile CIB_R22C47:CIB_DSP +arc: W3_H06W0103 E3_H06W0103 + +.tile CIB_R22C49:CIB_DSP +arc: N3_V06N0003 W3_H06E0003 + +.tile CIB_R22C53:CIB_DSP +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R22C59:CIB_DSP +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R22C65:CIB_DSP +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R22C71:CIB_DSP +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R22C77:CIB_DSP +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R22C7:CIB_DSP +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R22C83:CIB_DSP +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R22C89:CIB_LR_S +arc: S3_V06S0303 JF5 +arc: W3_H06W0303 JQ5 + +.tile CIB_R23C1:CIB_LR +arc: JA0 E1_H02W0501 +arc: JA3 V02N0701 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R23C89:CIB_LR +arc: S3_V06S0303 JF5 +arc: W3_H06W0303 JQ5 + +.tile CIB_R24C1:CIB_LR +arc: N1_V02N0701 S1_V02N0701 + +.tile CIB_R25C1:CIB_LR +arc: E3_H06E0303 JQ5 +arc: N3_V06N0303 S3_V06N0303 +arc: S3_V06S0303 JF5 + +.tile CIB_R25C89:CIB_LR +arc: S3_V06S0303 JF5 +arc: W3_H06W0303 JQ5 + +.tile CIB_R26C1:CIB_LR +arc: E1_H01E0101 JQ5 +arc: E3_H06E0303 JF5 +arc: N1_V02N0701 H06W0203 + +.tile CIB_R26C89:CIB_LR +arc: JA0 W1_H02E0501 +arc: JA3 W1_H02E0701 +arc: W3_H06W0303 N3_V06S0303 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R27C89:CIB_LR +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 + +.tile CIB_R28C1:CIB_LR +arc: E3_H06E0303 N3_V06S0303 +arc: S1_V02S0501 JF5 +arc: S3_V06S0303 JQ5 + +.tile CIB_R28C89:CIB_LR +arc: JA3 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 JF5 +arc: W3_H06W0303 V06S0303 +enum: CIB.JB3MUX 0 + +.tile CIB_R29C1:CIB_LR +arc: E3_H06E0303 JQ5 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0303 JF5 + +.tile CIB_R29C89:CIB_LR +arc: JA0 N1_V02S0501 +arc: JA3 N1_V02S0701 +arc: W3_H06W0303 N3_V06S0303 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R30C1:CIB_LR +arc: S3_V06S0303 N1_V02S0501 + +.tile CIB_R31C1:CIB_LR +arc: E3_H06E0303 V06S0303 +arc: JA0 E1_H02W0501 +arc: JA3 N1_V02S0701 +arc: N3_V06N0303 E3_H06W0303 +arc: V01S0100 N3_V06S0303 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R31C89:CIB_LR +arc: JA3 S1_V02N0701 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 V06S0003 +arc: W3_H06W0303 JF5 +enum: CIB.JB3MUX 0 + +.tile CIB_R32C1:CIB_LR +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 JF5 +arc: E3_H06E0303 N1_V01S0100 +arc: JA3 E1_H02W0501 +arc: S1_V02S0701 H06W0203 +enum: CIB.JB3MUX 0 + +.tile CIB_R32C89:CIB_LR +arc: JA3 W1_H02E0501 +arc: W3_H06W0303 JF5 +enum: CIB.JB3MUX 0 + +.tile CIB_R33C1:CIB_LR +arc: E3_H06E0303 V06S0303 + +.tile CIB_R33C89:CIB_LR +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 + +.tile CIB_R34C13:CIB_EBR +arc: E3_H06E0103 W3_H06E0003 + +.tile CIB_R34C19:CIB_EBR +arc: E3_H06E0103 W3_H06E0103 + +.tile CIB_R34C1:CIB_LR_S +arc: E3_H06E0303 JF5 +arc: JA3 N1_V02S0701 +enum: CIB.JB3MUX 0 + +.tile CIB_R34C25:CIB_EBR +arc: E3_H06E0103 W3_H06E0103 + +.tile CIB_R34C27:CIB_EBR +arc: E1_H02E0401 E3_H06W0203 + +.tile CIB_R34C28:CIB_EBR +arc: N1_V02N0401 H02E0401 + +.tile CIB_R34C29:CIB_EBR +arc: S1_V02S0501 E1_H02W0501 + +.tile CIB_R34C30:CIB_EBR +arc: E1_H02E0601 E3_H06W0303 +arc: S1_V02S0101 H02W0101 + +.tile CIB_R34C31:CIB_EBR +arc: E3_H06E0203 W3_H06E0103 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0501 E3_H06W0303 + +.tile CIB_R34C32:CIB_EBR +arc: S1_V02S0601 W1_H02E0601 + +.tile CIB_R34C33:CIB_EBR +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R34C34:CIB_EBR +arc: N1_V02N0201 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 N1_V02S0001 + +.tile CIB_R34C35:CIB_EBR +arc: N1_V02N0201 H02W0201 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H06W0303 +arc: V01S0100 S3_V06N0303 + +.tile CIB_R34C36:CIB_EBR +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E3_H06W0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R34C37:CIB_EBR +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0100 H02E0501 +arc: H01W0100 JF7 +arc: JB6 H02E0101 +arc: JB7 V02S0701 +arc: JD6 V00B0000 +arc: JD7 H00R0100 +arc: N1_V01N0001 JQ7 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 V01N0001 +arc: N3_V06N0303 JF6 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0201 +arc: V01S0100 N3_V06S0303 +arc: W3_H06W0103 E1_H02W0201 +arc: W3_H06W0303 JQ6 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 + +.tile CIB_R34C38:CIB_EBR +arc: E1_H01E0001 JF0 +arc: E1_H01E0101 JQ4 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 W1_H02E0601 +arc: H01W0000 JF6 +arc: H01W0100 JQ2 +arc: JA0 H00L0000 +arc: JA1 E1_H02W0701 +arc: JA2 V02N0701 +arc: JA3 H02E0701 +arc: JA5 E1_H02W0501 +arc: JA7 E1_H02W0501 +arc: JB0 H02E0101 +arc: JB1 H02W0101 +arc: JB2 H00R0000 +arc: JB3 N1_V02S0301 +arc: JB4 V00B0100 +arc: JB5 N1_V01S0000 +arc: JB6 N1_V02S0501 +arc: JB7 W1_H02E0301 +arc: JC2 E1_H02W0401 +arc: JC3 H02W0601 +arc: JC4 E1_H02W0601 +arc: JC6 E1_H02W0601 +arc: JCLK0 G_HPBX0000 +arc: JD0 V02S0201 +arc: JD1 V02S0001 +arc: JD2 W1_H02E0001 +arc: JD3 S1_V02N0201 +arc: JD4 N1_V02S0401 +arc: JD5 H02W0001 +arc: JD6 W1_H02E0201 +arc: JD7 V02S0401 +arc: N1_V01N0001 JF5 +arc: N1_V01N0101 JQ3 +arc: N1_V02N0101 JF1 +arc: N1_V02N0201 JQ0 +arc: N1_V02N0301 JQ1 +arc: N1_V02N0401 JQ6 +arc: N1_V02N0501 JQ7 +arc: S1_V02S0201 JF2 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 JF3 +arc: W1_H02W0501 JF7 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 JF4 +arc: W3_H06W0303 JQ5 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JCE1MUX 1 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 + +.tile CIB_R34C39:CIB_EBR +arc: E1_H01E0001 JF1 +arc: E3_H06E0003 JQ3 +arc: H00L0100 H02E0301 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0501 +arc: H01W0000 JF4 +arc: H01W0100 JQ2 +arc: JA0 H00L0100 +arc: JA1 V02N0701 +arc: JA4 H02E0701 +arc: JA5 W1_H02E0501 +arc: JA6 S1_V02N0301 +arc: JA7 N1_V02S0101 +arc: JB0 S1_V02N0101 +arc: JB1 H02W0301 +arc: JB2 V02S0301 +arc: JB3 H00R0100 +arc: JB4 V02S0501 +arc: JB5 W1_H02E0301 +arc: JB6 V02S0701 +arc: JB7 H02E0101 +arc: JC0 H02E0601 +arc: JC1 V02S0601 +arc: JC4 W1_H02E0601 +arc: JC5 H02E0401 +arc: JC6 W1_H02E0401 +arc: JC7 V00T0100 +arc: JCLK0 G_HPBX0000 +arc: JD0 W1_H02E0201 +arc: JD1 H02E0001 +arc: JD2 H00R0000 +arc: JD3 H02W0201 +arc: JD4 S1_V02N0601 +arc: JD5 W1_H02E0001 +arc: JD6 V00B0000 +arc: JD7 H02E0201 +arc: N1_V01N0101 JQ5 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 JF3 +arc: N1_V02N0401 JQ6 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 JF6 +arc: N3_V06N0003 JF0 +arc: N3_V06N0203 JQ4 +arc: N3_V06N0303 JF5 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0203 JF7 +arc: V00B0000 V02N0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 JF2 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 JQ0 +arc: W3_H06W0103 JQ1 +arc: W3_H06W0203 JQ7 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JCE1MUX 1 + +.tile CIB_R34C40:CIB_EBR +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0601 H06E0303 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 N1_V01S0100 + +.tile CIB_R34C41:CIB_EBR +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V02S0701 +arc: N1_V02N0401 E1_H01W0000 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0601 V06S0303 + +.tile CIB_R34C42:CIB_EBR +arc: E1_H01E0001 JQ6 +arc: E1_H01E0101 JF4 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0103 JQ1 +arc: E3_H06E0203 JF7 +arc: E3_H06E0303 JF6 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02N0601 +arc: H01W0000 JQ7 +arc: H01W0100 JF0 +arc: JA0 H00L0100 +arc: JA1 W1_H02E0701 +arc: JA2 H02W0501 +arc: JA3 W1_H02E0501 +arc: JA5 V00B0000 +arc: JA7 H00R0000 +arc: JB0 S1_V02N0301 +arc: JB1 V02N0301 +arc: JB2 H00L0000 +arc: JB3 H02E0301 +arc: JB4 V02N0501 +arc: JB5 N1_V01S0000 +arc: JB6 N1_V02S0701 +arc: JB7 V02S0701 +arc: JC2 W1_H02E0401 +arc: JC3 H02E0601 +arc: JC4 W1_H02E0601 +arc: JC6 W1_H02E0601 +arc: JCLK0 G_HPBX0000 +arc: JD0 V02N0201 +arc: JD1 V00T0100 +arc: JD2 V00B0100 +arc: JD3 V02S0201 +arc: JD4 S1_V02N0601 +arc: JD5 H02E0001 +arc: JD6 E1_H02W0201 +arc: JD7 H02W0201 +arc: N1_V01N0001 JF5 +arc: N1_V02N0101 JF3 +arc: N1_V02N0201 JQ2 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 JF1 +arc: S1_V02S0201 JQ0 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 JQ5 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W3_H06W0003 JQ3 +arc: W3_H06W0103 JF2 +arc: W3_H06W0203 JQ4 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JCE1MUX 1 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 + +.tile CIB_R34C43:CIB_EBR +arc: E1_H01E0001 JF2 +arc: E1_H01E0101 JF0 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02E0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 H02E0501 +arc: H01W0000 JF3 +arc: H01W0100 JF1 +arc: JA0 H00L0000 +arc: JA1 S1_V02N0701 +arc: JA4 N1_V01N0101 +arc: JA5 V02S0101 +arc: JA6 V00T0100 +arc: JA7 N1_V02S0101 +arc: JB0 E1_H02W0101 +arc: JB1 V02S0301 +arc: JB3 W1_H02E0101 +arc: JB5 N1_V01S0000 +arc: JB7 H02E0301 +arc: JC0 H00L0100 +arc: JC1 H02E0401 +arc: JC4 V00B0100 +arc: JC5 H02E0601 +arc: JC6 W1_H02E0401 +arc: JC7 V02S0001 +arc: JCLK0 G_HPBX0000 +arc: JD0 V02N0201 +arc: JD1 V02S0201 +arc: JD2 H00R0000 +arc: JD4 N1_V02S0401 +arc: JD6 H00R0100 +arc: N1_V01N0001 JF5 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 JQ0 +arc: N1_V02N0101 JQ1 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 JF6 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0203 JF7 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 H01E0101 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 JF4 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 E1_H01W0000 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JCE2MUX 1 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE1MUX 1 + +.tile CIB_R34C44:CIB_EBR +arc: H01W0000 JF0 +arc: JB1 H02E0101 +arc: JD0 W1_H02E0001 +arc: N1_V02N0101 JF1 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H01E0101 +arc: W1_H02W0201 V02N0201 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 + +.tile CIB_R34C45:CIB_EBR +arc: N1_V02N0401 H06E0203 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0303 H06E0303 +arc: W1_H02W0101 N1_V01S0100 + +.tile CIB_R34C46:CIB_EBR +arc: S1_V02S0601 N1_V02S0301 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R34C47:CIB_EBR +arc: H01W0100 E3_H06W0303 + +.tile CIB_R34C52:CIB_EBR +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R34C53:CIB_EBR +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R34C58:CIB_EBR +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R34C59:CIB_EBR +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R34C64:CIB_EBR +arc: W3_H06W0303 E3_H06W0203 + +.tile CIB_R34C65:CIB_EBR +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R34C70:CIB_EBR +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R34C71:CIB_EBR +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R34C76:CIB_EBR +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R34C77:CIB_EBR +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R34C7:CIB_EBR +arc: E3_H06E0003 W3_H06E0303 + +.tile CIB_R34C82:CIB_EBR +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R34C83:CIB_EBR +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R34C88:CIB_EBR +arc: W3_H06W0203 E1_H01W0000 + +.tile CIB_R34C89:CIB_LR_S +arc: H01W0000 JQ5 +arc: W3_H06W0303 JF5 + +.tile CIB_R35C1:CIB_LR +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0701 S1_V02N0701 +arc: JA0 E1_H02W0501 +arc: JA3 E1_H01E0001 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 H06W0103 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R35C89:CIB_LR +arc: H01W0000 JQ5 +arc: S1_V02S0701 W1_H02E0701 +arc: W3_H06W0303 JF5 + +.tile CIB_R36C1:CIB_LR +arc: E1_H02E0601 S1_V02N0601 + +.tile CIB_R37C1:CIB_LR +arc: E3_H06E0303 S3_V06N0303 +arc: JA0 N1_V02S0701 +arc: N1_V02N0701 JQ5 +enum: CIB.JB0MUX 0 + +.tile CIB_R37C89:CIB_LR +arc: H01W0100 JQ5 +arc: JA0 N1_V02S0701 +arc: S3_V06S0203 H01E0001 +arc: W1_H02W0601 V06N0303 +arc: W3_H06W0303 S3_V06N0303 +enum: CIB.JB0MUX 0 + +.tile CIB_R38C1:CIB_LR +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: E3_H06E0303 JQ5 +arc: JA0 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +enum: CIB.JB0MUX 0 + +.tile CIB_R38C89:CIB_LR +arc: JA0 W1_H02E0501 +arc: JA3 W1_H02E0701 +arc: S1_V02S0701 H06E0203 +arc: W3_H06W0303 V06N0303 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R39C1:CIB_LR +arc: E3_H06E0003 V01N0001 + +.tile CIB_R40C1:CIB_LR +arc: E3_H06E0303 JQ5 +arc: N1_V01N0001 JF5 +arc: N1_V02N0601 S3_V06N0303 + +.tile CIB_R40C89:CIB_LR +arc: JA3 N1_V02S0701 +arc: N3_V06N0303 JF5 +arc: W3_H06W0303 S3_V06N0303 +enum: CIB.JB3MUX 0 + +.tile CIB_R41C1:CIB_LR +arc: JA0 H02W0701 +arc: JA3 H02W0501 +arc: S3_V06S0203 N3_V06S0103 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R41C89:CIB_LR +arc: N3_V06N0303 JQ5 +arc: S1_V02S0501 W1_H02E0501 +arc: W3_H06W0303 JF5 + +.tile CIB_R42C1:CIB_LR +arc: S1_V02S0501 E1_H02W0501 + +.tile CIB_R43C1:CIB_LR +arc: E3_H06E0303 JQ5 +arc: N3_V06N0303 JF5 + +.tile CIB_R43C89:CIB_LR +arc: JA0 N1_V02S0501 +arc: N3_V06N0303 JQ5 +arc: S1_V02S0701 N3_V06S0203 +enum: CIB.JB0MUX 0 + +.tile CIB_R44C1:CIB_LR +arc: JA0 E1_H02W0501 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 JQ5 +arc: S1_V02S0501 N1_V02S0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R44C89:CIB_LR +arc: JA0 H02E0701 +arc: JA3 V02S0701 +arc: W3_H06W0303 S3_V06N0303 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R45C89:CIB_LR +arc: S1_V02S0401 W1_H02E0401 + +.tile CIB_R46C13:CIB_DSP +arc: E3_H06E0103 W3_H06E0003 + +.tile CIB_R46C19:CIB_DSP +arc: E3_H06E0203 W3_H06E0103 + +.tile CIB_R46C1:CIB_LR_S +arc: E3_H06E0303 S3_V06N0303 +arc: JA3 N1_V02S0501 +arc: N3_V06N0303 JF5 +enum: CIB.JB3MUX 0 + +.tile CIB_R46C25:CIB_DSP +arc: E3_H06E0203 W3_H06E0203 + +.tile CIB_R46C31:CIB_DSP +arc: E3_H06E0203 W3_H06E0203 + +.tile CIB_R46C33:CIB_DSP +arc: N3_V06N0103 S3_V06N0103 + +.tile CIB_R46C34:CIB_DSP +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R46C35:CIB_DSP +arc: N3_V06N0203 S3_V06N0203 + +.tile CIB_R46C36:CIB_DSP +arc: N3_V06N0003 S3_V06N0003 + +.tile CIB_R46C37:CIB_DSP +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 W3_H06E0203 + +.tile CIB_R46C38:CIB_DSP +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R46C41:CIB_DSP +arc: N3_V06N0203 E3_H06W0203 + +.tile CIB_R46C43:CIB_DSP +arc: N3_V06N0203 S3_V06N0203 + +.tile CIB_R46C47:CIB_DSP +arc: W3_H06W0203 E3_H06W0203 + +.tile CIB_R46C53:CIB_DSP +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R46C59:CIB_DSP +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R46C65:CIB_DSP +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R46C71:CIB_DSP +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R46C77:CIB_DSP +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R46C7:CIB_DSP +arc: E3_H06E0003 W3_H06E0303 + +.tile CIB_R46C83:CIB_DSP +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R46C89:CIB_LR_S +arc: N3_V06N0303 JF5 +arc: W3_H06W0303 JQ5 + +.tile CIB_R47C1:CIB_LR +arc: E3_H06E0303 JQ5 +arc: JA0 H02W0701 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 N3_V06S0203 +enum: CIB.JB0MUX 0 + +.tile CIB_R47C89:CIB_LR +arc: JA0 H02E0701 +arc: JA3 H02E0501 +arc: S1_V02S0501 N1_V02S0401 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R49C1:CIB_LR +arc: JA0 N1_V02S0701 +arc: JA3 N1_V02S0501 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R49C89:CIB_LR +arc: JA0 N1_V02S0501 +arc: W3_H06W0303 JQ5 +enum: CIB.JB0MUX 0 + +.tile CIB_R50C1:CIB_LR +arc: E3_H06E0303 JQ5 +arc: N3_V06N0303 JF5 +arc: S1_V02S0701 E1_H02W0701 + +.tile CIB_R50C89:CIB_LR +arc: N3_V06N0303 JQ5 +arc: W3_H06W0303 JF5 + +.tile CIB_R52C1:CIB_LR +arc: JA3 N1_V02S0701 +arc: N3_V06N0303 JF5 +enum: CIB.JB3MUX 0 + +.tile CIB_R52C89:CIB_LR +arc: JA0 H02E0501 +arc: W3_H06W0303 JQ5 +enum: CIB.JB0MUX 0 + +.tile CIB_R55C89:CIB_LR +arc: JA0 W1_H02E0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R58C33:CIB_EBR +arc: N3_V06N0003 S3_V06N0003 + +.tile CIB_R58C34:CIB_EBR +arc: N3_V06N0203 S3_V06N0103 + +.tile CIB_R58C35:CIB_EBR +arc: N3_V06N0203 S3_V06N0103 + +.tile CIB_R58C36:CIB_EBR +arc: N3_V06N0303 S3_V06N0303 + +.tile CIB_R58C37:CIB_EBR +arc: N3_V06N0103 S3_V06N0103 + +.tile CIB_R58C43:CIB_EBR +arc: N3_V06N0203 S3_V06N0103 + +.tile CIB_R5C1:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C89:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C10:CIB +arc: E3_H06E0003 JQ0 + +.tile CIB_R70C11:CIB +arc: JA0 N1_V02S0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R70C12:CIB +arc: JA0 N1_V02S0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R70C13:CIB +arc: E3_H06E0003 JQ0 + +.tile CIB_R70C14:CIB +arc: E3_H06E0003 JQ0 + +.tile CIB_R70C15:CIB +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0003 JQ0 +arc: E3_H06E0103 W3_H06E0003 + +.tile CIB_R70C16:CIB +arc: E3_H06E0103 W3_H06E0003 +arc: JA0 H02E0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R70C18:CIB +arc: JA0 N1_V02S0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R70C19:CIB +arc: E3_H06E0003 W3_H06E0003 + +.tile CIB_R70C20:CIB +arc: E3_H06E0003 W3_H06E0003 + +.tile CIB_R70C21:CIB +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 + +.tile CIB_R70C22:CIB +arc: E3_H06E0103 W3_H06E0103 + +.tile CIB_R70C25:CIB +arc: E3_H06E0003 W3_H06E0003 + +.tile CIB_R70C26:CIB +arc: E3_H06E0103 W3_H06E0003 + +.tile CIB_R70C27:CIB +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 + +.tile CIB_R70C28:CIB +arc: E3_H06E0103 W3_H06E0103 + +.tile CIB_R70C31:CIB +arc: E3_H06E0003 W3_H06E0003 + +.tile CIB_R70C32:CIB +arc: E3_H06E0103 W3_H06E0103 + +.tile CIB_R70C33:CIB +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 + +.tile CIB_R70C34:CIB +arc: N3_V06N0103 W3_H06E0103 + +.tile CIB_R70C35:CIB +arc: N3_V06N0103 H06E0103 + +.tile CIB_R70C36:CIB +arc: N3_V06N0303 H06E0303 + +.tile CIB_R70C37:CIB +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 + +.tile CIB_R70C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C42:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C43:VCIB_DCUA +arc: N3_V06N0103 W3_H06E0103 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C44:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C45:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C46:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C47:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C48:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C49:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C50:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C51:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C52:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C53:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C69:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C70:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C71:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C72:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C73:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C74:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C75:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C76:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C77:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C78:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C79:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile CIB_R70C80:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C87:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C9:CIB +arc: E3_H06E0003 JQ0 + +.tile MIB_R0C18:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C19:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C20:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C21:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C22:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C23:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C24:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C25:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C27:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C28:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C29:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C30:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C31:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C32:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C33:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C34:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C36:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C37:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C38:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C39:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C3:BANKREF0 +enum: BANK.VCCIO 3V3 + +.tile MIB_R0C40:TMID_0 +arc: G_TDCC0CLKI G_JTRQPCLKCIB1 + +.tile MIB_R0C42:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C43:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C44:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C45:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C47:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C48:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C49:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C50:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C51:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C52:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C53:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C54:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C56:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C57:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C58:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C59:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C60:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C61:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C62:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C63:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C65:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C66:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C67:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C68:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C69:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C70:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C71:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C72:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C75:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C87:BANKREF1 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C0:BANKREF7 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C30:EBR_SPINE_UL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C40:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_VPFS0000 + +.tile MIB_R10C41:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_VPFS0000 + +.tile MIB_R10C50:EBR_SPINE_UR0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C90:BANKREF2 +enum: BANK.VCCIO 3V3 + +.tile MIB_R17C90:PICR0_DQS2 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R18C90:PICR1_DQS3 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R1C18:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C19:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C20:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C21:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C22:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C23:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C24:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C25:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C27:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C28:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C29:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C30:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C31:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C32:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C33:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C34:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C36:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C37:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C38:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C39:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C42:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C43:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C44:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C45:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C47:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C48:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C49:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C50:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C51:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C52:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C53:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C54:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C56:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C57:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C58:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C59:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C60:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C61:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C62:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C63:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C65:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C66:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C67:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C68:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C69:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C70:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C71:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C72:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C75:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R20C0:PICL0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R20C90:PICR0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R21C0:PICL1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON + +.tile MIB_R21C90:PICR1 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON + +.tile MIB_R22C0:MIB_CIB_LR +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R22C90:MIB_CIB_LR_A +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R23C0:PICL0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R23C90:PICR0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R24C0:PICL1 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON + +.tile MIB_R24C90:PICR1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R25C0:PICL2 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R25C90:PICR2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R26C0:PICL0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R26C90:PICR0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R27C0:PICL1_DQS0 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R27C90:PICR1_DQS0 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R28C0:PICL2_DQS1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R28C90:PICR2_DQS1 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R29C0:PICL0_DQS2 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R29C90:PICR0_DQS2 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R30C0:PICL1_DQS3 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R30C90:PICR1_DQS3 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R31C0:PICL2 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R31C90:PICR2 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R32C0:PICL0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R32C90:PICR0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R33C0:PICL1 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R33C90:PICR1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R34C0:MIB_CIB_LR +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R34C90:MIB_CIB_LR_A +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R35C0:PICL0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R35C90:PICR0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R36C0:PICL1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R36C90:PICR1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R37C0:PICL2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R37C90:PICR2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R38C0:PICL0 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R38C90:PICR0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R39C0:PICL1_DQS0 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R39C90:PICR1_DQS0 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R40C0:PICL2_DQS1 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R40C90:PICR2_DQS1 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R41C0:PICL0_DQS2 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R41C90:PICR0_DQS2 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R42C0:PICL1_DQS3 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R42C90:PICR1_DQS3 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R43C0:PICL2 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R43C90:PICR2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R44C0:PICL0 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R44C90:PICR0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R45C0:PICL1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R45C90:PICR1 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R46C0:MIB_CIB_LR +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R46C90:MIB_CIB_LR_A +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R47C0:PICL0 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R47C90:PICR0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R48C0:PICL1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R48C90:PICR1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R49C0:PICL2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R49C90:PICR2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R50C0:PICL0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R50C90:PICR0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R51C0:PICL1_DQS0 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R51C90:PICR1_DQS0 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R52C0:PICL2_DQS1 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R52C90:PICR2_DQS1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R54C90:PICR1_DQS3 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R55C90:PICR2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R58C30:EBR_SPINE_LL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R58C40:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_VPFS0000 + +.tile MIB_R58C41:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_VPFS0000 + +.tile MIB_R58C50:EBR_SPINE_LR0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R71C10:PICB1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R71C11:PICB0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R71C12:PICB1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R71C13:PICB0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R71C14:PICB1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R71C15:PICB0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R71C16:PICB1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R71C18:SPICB0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R71C1:BANKREF6 +enum: BANK.VCCIO 3V3 + +.tile MIB_R71C3:BANKREF8 +enum: BANK.VCCIO 3V3 + +.tile MIB_R71C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile MIB_R71C89:BANKREF3 +enum: BANK.VCCIO 3V3 + +.tile MIB_R71C9:PICB0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile R11C35:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R11C67:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R12C24:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R13C30:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R13C34:PLC2 +arc: E3_H06E0103 N3_V06S0103 +arc: S3_V06S0003 N3_V06S0303 + +.tile R13C35:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R13C36:PLC2 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 + +.tile R13C37:PLC2 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 + +.tile R13C38:PLC2 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 + +.tile R13C39:PLC2 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 + +.tile R13C40:PLC2 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 + +.tile R13C41:PLC2 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 + +.tile R13C42:PLC2 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 + +.tile R13C43:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R13C44:PLC2 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 + +.tile R13C45:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R13C46:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R13C67:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R14C31:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R14C42:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0003 N3_V06S0303 + +.tile R14C43:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R14C54:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R14C61:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R14C73:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R15C15:PLC2 +word: SLICEA.K0.INIT 1111111111111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R15C17:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R15C19:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R15C23:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R15C37:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R15C39:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R15C41:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R15C42:PLC2 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 + +.tile R15C52:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R15C57:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R15C61:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R15C67:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R16C49:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R17C35:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R17C41:PLC2 +arc: S3_V06S0103 E3_H06W0103 + +.tile R17C47:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R17C53:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R17C59:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R17C65:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R17C67:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R17C71:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R17C77:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R17C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R18C24:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R19C30:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R19C34:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R19C35:PLC2 +arc: S3_V06S0003 N3_V06S0303 + +.tile R19C36:PLC2 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 + +.tile R19C37:PLC2 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0100 N3_V06S0303 + +.tile R19C38:PLC2 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 + +.tile R19C39:PLC2 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 + +.tile R19C40:PLC2 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 + +.tile R19C41:PLC2 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 + +.tile R19C42:PLC2 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 + +.tile R19C43:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R19C44:PLC2 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 + +.tile R19C45:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R19C46:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R19C67:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R20C31:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R20C37:PLC2 +arc: E3_H06E0103 S3_V06N0103 +arc: S3_V06S0103 N1_V01S0100 + +.tile R20C3:PLC2 +arc: W1_H02W0701 V02N0701 + +.tile R20C42:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0103 N3_V06S0003 + +.tile R20C43:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R20C44:PLC2 +arc: S3_V06S0303 H06W0303 + +.tile R20C47:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R20C53:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R20C54:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R20C59:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R20C61:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R20C65:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R20C71:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R20C73:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R20C77:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R20C83:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R21C17:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R21C19:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R21C23:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R21C37:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R21C39:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R21C3:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R21C41:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R21C42:PLC2 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 + +.tile R21C52:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R21C57:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R21C61:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R21C67:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R23C35:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R23C3:PLC2 +arc: W1_H02W0501 S1_V02N0501 + +.tile R23C41:PLC2 +arc: S1_V02S0201 N3_V06S0103 + +.tile R23C44:PLC2 +arc: S3_V06S0303 H06W0303 + +.tile R23C47:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R23C53:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R23C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R23C65:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R23C67:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R23C69:PLC2 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R23C71:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R23C77:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R23C83:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R24C24:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R25C13:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R25C19:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R25C25:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R25C30:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R25C31:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R25C34:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R25C35:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R25C36:PLC2 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 + +.tile R25C37:PLC2 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0303 + +.tile R25C38:PLC2 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 N3_V06S0203 + +.tile R25C39:PLC2 +arc: E3_H06E0103 N3_V06S0103 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0701 N3_V06S0203 + +.tile R25C3:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R25C40:PLC2 +arc: S1_V02S0201 E1_H01W0000 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 V02N0301 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0401 Q4 +arc: M4 V00B0100 +arc: MUXCLK2 CLK0 +arc: S3_V06S0203 Q4 +arc: W3_H06W0203 Q4 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C41:PLC2 +arc: E1_H02E0201 V06S0103 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W3_H06W0203 E1_H01W0000 +arc: A7 E1_H02W0701 +arc: B7 V02N0501 +arc: C7 H02E0401 +arc: D7 V01N0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 E1_H02W0601 +arc: M1 H00L0000 +arc: M2 E1_H02W0601 +arc: M3 H00L0100 +arc: M4 E1_H02W0401 +arc: M5 H00L0000 +arc: M6 E1_H02W0401 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1000010000100001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R25C42:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: B3 H02W0301 +arc: CLK0 G_HPBX0000 +arc: D3 V00T0100 +arc: E1_H01E0001 F3 +arc: F3 F3_SLICE +arc: H01W0000 Q3 +arc: M3 H02E0201 +arc: MUXCLK1 CLK0 +arc: S3_V06S0003 Q3 +arc: V00T0100 Q3 +word: SLICEB.K1.INIT 1100110000110011 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R25C43:PLC2 +arc: S3_V06S0003 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 V06S0203 + +.tile R25C44:PLC2 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N3_V06S0303 + +.tile R25C45:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R25C46:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R25C47:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R25C48:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R25C53:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R25C54:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R25C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R25C60:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R25C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R25C66:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R25C67:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R25C71:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R25C72:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R25C77:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R25C78:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R25C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R25C83:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R25C84:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R25C87:PLC2 +arc: S3_V06S0203 H06E0203 + +.tile R26C10:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R26C13:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R26C14:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R26C16:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R26C19:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R26C20:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R26C22:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R26C25:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R26C26:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R26C28:PLC2 +arc: S3_V06S0103 E3_H06W0103 +arc: W3_H06W0303 S3_V06N0303 + +.tile R26C2:PLC2 +arc: E3_H06E0303 H01E0101 + +.tile R26C31:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0003 S3_V06N0303 + +.tile R26C32:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R26C34:PLC2 +arc: S3_V06S0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 + +.tile R26C37:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 S1_V02N0601 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 V02N0601 +arc: A2 E1_H02W0701 +arc: A7 H00L0000 +arc: C2 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D2 V00B0100 +arc: D7 E1_H02W0001 +arc: E3_H06E0203 F7 +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: M2 V00T0000 +arc: M5 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N3_V06N0103 F2 +arc: V00B0100 Q5 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 1010111110100000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R26C38:PLC2 +arc: E1_H02E0701 W3_H06E0203 +arc: S3_V06S0203 H06W0203 + +.tile R26C39:PLC2 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 + +.tile R26C40:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0701 +arc: N1_V02N0301 N1_V01S0100 +arc: S1_V02S0201 H06E0103 +arc: S3_V06S0203 N1_V01S0000 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V01N0101 +arc: B0 S1_V02N0301 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: S3_V06S0003 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C41:PLC2 +arc: H00L0000 H02E0201 +arc: H00L0100 V02S0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0501 E1_H02W0501 +arc: S1_V02S0201 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A6 H00L0000 +arc: B1 V02N0101 +arc: B6 E1_H02W0101 +arc: C0 H02E0601 +arc: C6 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D6 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q7 +arc: M1 H00R0100 +arc: M4 H02W0401 +arc: M7 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0001 F0 +arc: N1_V02N0101 F1 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q4 +arc: V00B0000 Q4 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +arc: W1_H02W0601 F6 +word: SLICED.K0.INIT 1100111101000101 +word: SLICEA.K1.INIT 0000000011001100 +word: SLICEA.K0.INIT 0000111100000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C42:PLC2 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0401 N1_V01S0000 +arc: A3 V00T0000 +arc: A6 H02W0701 +arc: C3 H02W0401 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D3 V01S0100 +arc: D6 W1_H02E0001 +arc: E3_H06E0303 F6 +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: M2 V00B0000 +arc: M6 E1_H02W0401 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0003 F3 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V01S0100 Q2 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111101001010000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R26C43:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 + +.tile R26C44:PLC2 +arc: S3_V06S0003 N3_V06S0303 +arc: W1_H02W0401 V02S0401 + +.tile R26C46:PLC2 +arc: S3_V06S0003 W3_H06E0003 + +.tile R26C47:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R26C48:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R26C49:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R26C4:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R26C53:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R26C54:PLC2 +arc: N3_V06N0303 W3_H06E0303 + +.tile R26C55:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R26C59:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R26C61:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R26C65:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R26C67:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R26C71:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R26C73:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0203 S3_V06N0103 + +.tile R26C77:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R26C79:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R26C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R26C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R26C85:PLC2 +arc: E1_H02E0701 W3_H06E0203 + +.tile R26C87:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 W1_H02E0701 + +.tile R26C8:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R27C17:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R27C19:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R27C23:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R27C36:PLC2 +arc: S1_V02S0401 N1_V02S0101 + +.tile R27C37:PLC2 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S3_V06S0303 H06W0303 +arc: V00T0000 N1_V02S0401 +arc: B6 V00B0000 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D6 V02S0601 +arc: E1_H01E0101 Q0 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: M0 V00T0000 +arc: M3 H02W0201 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S3_V06S0003 Q0 +arc: V00B0000 Q4 +arc: V01S0000 Q3 +word: SLICED.K0.INIT 1100110011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R27C38:PLC2 +arc: W1_H02W0201 N1_V02S0201 + +.tile R27C39:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: W1_H02W0601 V02N0601 + +.tile R27C3:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R27C40:PLC2 +arc: V00B0000 V02S0201 +arc: W3_H06W0303 E1_H01W0100 +arc: C3 E1_H01W0000 +arc: C6 Q6 +arc: CLK0 G_HPBX0000 +arc: D3 H02W0201 +arc: D6 V00B0000 +arc: E1_H01E0001 Q6 +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: M6 H02W0401 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F3 +arc: S1_V02S0601 F6 +arc: S3_V06S0303 Q6 +word: SLICED.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R27C41:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: A6 N1_V01S0100 +arc: B6 W1_H02E0101 +arc: C6 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D6 H01W0000 +arc: F6 F6_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: M2 E1_H02W0601 +arc: MUXCLK1 CLK0 +arc: S3_V06S0103 Q2 +arc: V01S0000 F6 +word: SLICED.K0.INIT 1101000011011101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C42:PLC2 +arc: H00R0100 V02N0701 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: CLK0 G_HPBX0000 +arc: M0 V00B0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0201 Q0 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C43:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: W1_H02W0601 V02N0601 + +.tile R27C44:PLC2 +arc: S1_V02S0701 N1_V02S0601 + +.tile R27C45:PLC2 +arc: E3_H06E0103 S3_V06N0103 + +.tile R27C49:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R27C51:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R27C52:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R27C55:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R27C57:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: N3_V06N0003 S3_V06N0303 + +.tile R27C61:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R27C63:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R27C67:PLC2 +arc: N1_V02N0001 W3_H06E0003 +arc: N3_V06N0003 S3_V06N0303 + +.tile R27C69:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R27C75:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R27C81:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R27C87:PLC2 +arc: N1_V02N0501 W3_H06E0303 + +.tile R28C13:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R28C19:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R28C25:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R28C31:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R28C37:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N1_V02S0601 +arc: V01S0100 S3_V06N0303 +arc: B5 S1_V02N0501 +arc: C5 N1_V02S0001 +arc: CLK0 G_HPBX0000 +arc: D5 H01W0000 +arc: E1_H01E0101 Q7 +arc: F5 F5_SLICE +arc: H00R0100 Q7 +arc: H01W0000 Q5 +arc: M5 H00R0100 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 F5 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R28C38:PLC2 +arc: S3_V06S0103 H01E0101 + +.tile R28C39:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 + +.tile R28C40:PLC2 +arc: H00R0000 V02S0601 +arc: V00T0100 V02N0501 +arc: A3 H02W0701 +arc: B3 H02W0301 +arc: C3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D3 V02N0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q7 +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H02W0201 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: M7 H02E0201 +arc: MUXCLK3 CLK0 +arc: N1_V02N0301 F3 +arc: S3_V06S0203 Q7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R28C41:PLC2 +arc: S1_V02S0601 E3_H06W0303 +arc: S3_V06S0103 N1_V02S0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0701 V06S0203 + +.tile R28C42:PLC2 +arc: N1_V02N0701 N1_V01S0100 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0303 N1_V02S0601 + +.tile R28C43:PLC2 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S3_V06S0303 N3_V06S0203 + +.tile R28C47:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R28C53:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R28C59:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R28C65:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R28C71:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R28C77:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R28C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R28C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R28C87:PLC2 +arc: E1_H02E0701 V06S0203 + +.tile R29C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: W3_H06W0103 E3_H06W0003 + +.tile R29C19:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: W3_H06W0003 E3_H06W0003 + +.tile R29C25:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: W3_H06W0003 E3_H06W0003 + +.tile R29C31:PLC2 +arc: S1_V02S0401 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 + +.tile R29C35:PLC2 +arc: N3_V06N0003 E3_H06W0003 + +.tile R29C36:PLC2 +arc: E1_H02E0401 N1_V02S0401 + +.tile R29C37:PLC2 +arc: V00B0000 H02E0401 +arc: A0 V02S0701 +arc: C0 N1_V01S0100 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: H00R0000 Q4 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S3_V06S0103 Q2 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 1111101001010000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R29C39:PLC2 +arc: E1_H02E0701 N1_V02S0701 +arc: S3_V06S0203 E1_H01W0000 + +.tile R29C40:PLC2 +arc: H00R0100 H02E0701 +arc: CLK0 G_HPBX0000 +arc: H01W0000 Q2 +arc: M2 H02W0601 +arc: M5 H00R0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0201 Q2 +arc: N1_V02N0501 Q5 +arc: S3_V06S0103 Q2 +arc: S3_V06S0303 Q5 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C41:PLC2 +arc: N1_V02N0401 E3_H06W0203 +arc: W1_H02W0601 V02S0601 +arc: B3 E1_H01W0100 +arc: C3 N1_V01S0100 +arc: D3 E1_H02W0001 +arc: F3 F3_SLICE +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R29C42:PLC2 +arc: H00R0100 H02W0701 +arc: S3_V06S0103 E1_H01W0100 +arc: CLK0 G_HPBX0000 +arc: H01W0100 Q3 +arc: M3 H00R0100 +arc: MUXCLK1 CLK0 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C43:PLC2 +arc: H00R0100 H02W0701 +arc: W1_H02W0001 V06S0003 +arc: CLK0 G_HPBX0000 +arc: H01W0100 Q5 +arc: M5 H00R0100 +arc: MUXCLK2 CLK0 +arc: W1_H02W0701 Q5 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C44:PLC2 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0701 N1_V02S0701 + +.tile R29C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R29C53:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R29C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R29C65:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R29C67:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R29C71:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R29C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R29C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: W3_H06W0203 E3_H06W0103 + +.tile R29C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R2C31:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R2C42:PLC2 +arc: N1_V01N0101 S3_V06N0203 + +.tile R2C43:PLC2 +arc: N1_V01N0101 S3_V06N0203 + +.tile R2C54:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R2C61:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R2C73:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R30C24:PLC2 +arc: N3_V06N0003 E3_H06W0003 + +.tile R30C30:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R30C36:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R30C37:PLC2 +arc: N1_V02N0501 E1_H02W0501 + +.tile R30C39:PLC2 +arc: W1_H02W0501 S1_V02N0501 + +.tile R30C42:PLC2 +arc: V00T0100 V02N0701 +arc: A5 V00B0000 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D5 S1_V02N0601 +arc: F5 F5_SLICE +arc: M6 V00T0100 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 1010111110100000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R31C12:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R31C13:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R31C18:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R31C19:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: W3_H06W0203 E3_H06W0203 + +.tile R31C24:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R31C25:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile R31C30:PLC2 +arc: N3_V06N0303 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 + +.tile R31C31:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: S1_V02S0401 N1_V02S0401 +arc: W3_H06W0103 E3_H06W0103 + +.tile R31C34:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0601 H06E0303 + +.tile R31C35:PLC2 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 H02E0401 + +.tile R31C36:PLC2 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0501 +arc: B6 V02N0501 +arc: B7 E1_H02W0101 +arc: C6 E1_H02W0601 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0101 Q4 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M4 V00B0100 +arc: MUXCLK2 CLK0 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F6 +word: SLICED.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1100110011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R31C37:PLC2 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: B1 V02N0101 +arc: C1 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D1 H01E0101 +arc: F1 F1_SLICE +arc: M5 E1_H02W0001 +arc: MUXCLK2 CLK0 +arc: S1_V02S0701 Q5 +arc: W1_H02W0501 Q5 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R31C38:PLC2 +arc: S1_V02S0101 E1_H02W0101 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0601 V02N0601 + +.tile R31C39:PLC2 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0401 E3_H06W0203 + +.tile R31C3:PLC2 +arc: N3_V06N0303 H06W0303 +arc: W1_H02W0501 S1_V02N0501 + +.tile R31C40:PLC2 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0101 N3_V06S0103 + +.tile R31C41:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0303 N3_V06S0203 +arc: W1_H02W0001 E3_H06W0003 + +.tile R31C42:PLC2 +arc: E1_H02E0701 N3_V06S0203 +arc: H00R0100 H02E0501 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: A0 V01N0101 +arc: B0 V02N0301 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: F0 F0_SLICE +arc: H01W0100 Q7 +arc: M0 H02E0601 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 Q7 +arc: N3_V06N0003 F0 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 1010101011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 + +.tile R31C43:PLC2 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 H02E0701 + +.tile R31C45:PLC2 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 N3_V06S0303 + +.tile R31C46:PLC2 +arc: S1_V02S0601 N3_V06S0303 +arc: W3_H06W0203 E1_H01W0000 + +.tile R31C47:PLC2 +arc: H01W0000 E3_H06W0103 +arc: W3_H06W0003 E3_H06W0003 + +.tile R31C51:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R31C53:PLC2 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 + +.tile R31C57:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R31C59:PLC2 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R31C63:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R31C65:PLC2 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0203 + +.tile R31C69:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R31C6:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R31C71:PLC2 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R31C75:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R31C77:PLC2 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R31C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R31C81:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R31C83:PLC2 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 + +.tile R31C87:PLC2 +arc: W3_H06W0303 E1_H02W0601 + +.tile R32C10:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R32C11:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R32C13:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R32C15:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 + +.tile R32C16:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R32C17:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R32C19:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R32C21:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 + +.tile R32C22:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R32C23:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R32C25:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R32C27:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 + +.tile R32C28:PLC2 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0303 +arc: B5 V01S0000 +arc: C5 V01N0101 +arc: D5 S1_V02N0401 +arc: F5 F5_SLICE +arc: N3_V06N0303 F5 +word: SLICEC.K1.INIT 1111001111000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R32C29:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R32C31:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0303 E3_H06W0303 + +.tile R32C33:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 + +.tile R32C34:PLC2 +arc: E1_H02E0601 V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 +arc: A5 E1_H02W0701 +arc: B5 E1_H02W0101 +arc: D5 V02S0401 +arc: F5 F5_SLICE +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 1010101011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 + +.tile R32C35:PLC2 +arc: E1_H02E0001 V02S0001 +arc: W3_H06W0203 E3_H06W0203 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q7 +arc: M0 H02E0601 +arc: M7 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0501 Q7 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C36:PLC2 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0301 H02W0301 +arc: W1_H02W0101 S1_V02N0101 +arc: CLK0 G_HPBX0000 +arc: M1 H02E0001 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0701 Q7 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C37:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 H02W0101 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 N3_V06S0003 +arc: A2 V00B0000 +arc: B2 H02W0101 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: C5 V01N0101 +arc: C6 E1_H02W0601 +arc: CLK0 G_HPBX0000 +arc: D2 V00B0100 +arc: D5 E1_H02W0001 +arc: D6 V01N0001 +arc: E1_H01E0101 Q2 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F6 +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q5 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M5 V01S0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 Q1 +arc: V00B0000 Q6 +arc: V00T0000 Q2 +arc: V01S0000 Q1 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICED.K0.INIT 1111110000110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R32C38:PLC2 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: CLK0 G_HPBX0000 +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q4 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C39:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: N1_V02N0501 S1_V02N0401 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0601 S1_V02N0601 + +.tile R32C3:PLC2 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: W1_H02W0501 E1_H02W0501 + +.tile R32C40:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 S1_V02N0601 +arc: S1_V02S0301 N3_V06S0003 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0701 N3_V06S0203 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0201 Q0 +arc: M0 H01E0001 +arc: MUXCLK0 CLK0 +arc: W1_H02W0201 Q0 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C41:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: H00R0000 H02E0601 +arc: H00R0100 W1_H02E0501 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 E1_H01W0100 +arc: W1_H02W0101 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0303 +arc: B4 H02E0301 +arc: C4 V00B0100 +arc: CLK0 G_HPBX0000 +arc: D4 S1_V02N0401 +arc: E1_H01E0101 Q3 +arc: E1_H02E0301 Q1 +arc: F4 F4_SLICE +arc: M1 H00R0000 +arc: M3 H00R0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0301 Q1 +arc: V00B0100 Q5 +arc: V01S0000 Q3 +arc: W3_H06W0203 F4 +word: SLICEC.K0.INIT 1111001111000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C42:PLC2 +arc: H00L0000 V02S0201 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 H01E0101 +arc: V00T0000 H02W0001 +arc: V00T0100 H02E0301 +arc: V01S0000 N3_V06S0103 +arc: A4 S1_V02N0101 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D4 V00B0000 +arc: E3_H06E0203 F4 +arc: F4 F4_SLICE +arc: H01W0100 Q7 +arc: M1 H00L0000 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q1 +arc: V00B0000 Q6 +arc: V01S0100 Q5 +word: SLICEC.K0.INIT 1111101000001010 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C43:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 V02S0401 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 H02W0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: CLK0 G_HPBX0000 +arc: H01W0000 Q1 +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q6 +arc: V01S0000 Q1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C44:PLC2 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 V06S0303 + +.tile R32C46:PLC2 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 + +.tile R32C47:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R32C48:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R32C49:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 + +.tile R32C4:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R32C53:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R32C54:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R32C55:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 + +.tile R32C59:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R32C5:PLC2 +arc: W1_H02W0501 E3_H06W0303 + +.tile R32C60:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R32C61:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0203 W3_H06E0203 + +.tile R32C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R32C66:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R32C67:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R32C71:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R32C72:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R32C73:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R32C77:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R32C78:PLC2 +arc: E1_H01E0101 W3_H06E0203 + +.tile R32C79:PLC2 +arc: E3_H06E0303 H01E0101 + +.tile R32C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R32C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R32C85:PLC2 +arc: E1_H02E0501 W3_H06E0303 + +.tile R32C87:PLC2 +arc: E1_H02E0501 W1_H02E0501 + +.tile R32C9:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 + +.tile R33C12:PLC2 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R33C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R33C17:PLC2 +arc: N3_V06N0303 E3_H06W0303 + +.tile R33C18:PLC2 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R33C19:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0003 E3_H06W0003 + +.tile R33C23:PLC2 +arc: N3_V06N0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 + +.tile R33C24:PLC2 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile R33C25:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: W3_H06W0003 E3_H06W0003 + +.tile R33C28:PLC2 +arc: H00L0100 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: M1 H00L0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C29:PLC2 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R33C30:PLC2 +arc: H00R0000 H02W0401 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: CLK0 G_HPBX0000 +arc: E3_H06E0103 Q1 +arc: M1 H00R0000 +arc: MUXCLK0 CLK0 +arc: W1_H02W0101 Q1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C31:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: W1_H02W0401 N1_V02S0401 +arc: W3_H06W0003 E3_H06W0303 + +.tile R33C32:PLC2 +arc: S1_V02S0601 H06W0303 + +.tile R33C34:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V02S0401 + +.tile R33C35:PLC2 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 S1_V02N0501 +arc: V00B0100 S1_V02N0101 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 H01W0100 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: E3_H06E0003 Q3 +arc: F0 F0_SLICE +arc: H01W0100 Q7 +arc: M1 V01S0100 +arc: M3 H00R0000 +arc: M6 V00B0100 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 Q6 +arc: V01S0100 Q3 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R33C36:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: S1_V02S0201 N1_V01S0000 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 E1_H02W0701 +arc: W3_H06W0103 E3_H06W0103 +arc: B0 V02S0301 +arc: C0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: H00R0000 Q6 +arc: H00R0100 Q5 +arc: H01W0100 Q7 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: M7 W1_H02E0201 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0000 Q6 +arc: V01S0100 Q7 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R33C37:PLC2 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V01S0100 N3_V06S0303 +arc: A5 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: C0 V02N0401 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D5 H02W0201 +arc: E1_H01E0001 Q4 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q5 +arc: W3_H06W0303 F5 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1111000011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R33C38:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V01N0001 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H06E0003 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0701 V01N0101 +arc: B1 E1_H02W0301 +arc: C1 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D1 V01S0100 +arc: E1_H02E0701 Q7 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q5 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: M7 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0401 Q6 +arc: V00B0000 Q6 +arc: V01S0000 Q7 +arc: V01S0100 Q2 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R33C39:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E3_H06E0103 V01N0101 +arc: H00R0100 H02W0701 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0101 V02N0101 +arc: B4 V02N0501 +arc: C4 V02S0001 +arc: D4 H00R0100 +arc: E3_H06E0203 F4 +arc: F4 F4_SLICE +word: SLICEC.K0.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R33C3:PLC2 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0103 H06W0103 + +.tile R33C40:PLC2 +arc: E1_H02E0301 V02S0301 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02S0301 +arc: A6 V02S0301 +arc: B3 V02S0301 +arc: B6 W1_H02E0101 +arc: C3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D3 W1_H02E0201 +arc: D6 V00B0000 +arc: E1_H01E0001 Q2 +arc: E3_H06E0003 F3 +arc: E3_H06E0303 F6 +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q2 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: M4 E1_H02W0401 +arc: M5 H02E0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V00B0000 Q4 +arc: W1_H02W0701 Q5 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 1110111001000100 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R33C41:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: W1_H02W0201 N1_V02S0201 +arc: B2 H02E0301 +arc: C2 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D2 V00T0100 +arc: F2 F2_SLICE +arc: M3 H00L0100 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q3 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R33C42:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 V02S0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0003 E1_H01W0000 +arc: A3 H02E0701 +arc: B1 V01N0001 +arc: B6 E1_H02W0101 +arc: C1 H00L0000 +arc: C3 H00L0000 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D1 V00B0100 +arc: D3 H02W0001 +arc: D6 H01W0000 +arc: E1_H01E0101 Q4 +arc: E3_H06E0003 F3 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q2 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0601 Q4 +arc: V00B0100 Q7 +arc: V01S0000 Q6 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K1.INIT 1010111110100000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R33C43:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02S0301 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0100 V02S0301 +arc: H00R0000 V02N0601 +arc: H00R0100 N1_V02S0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 V01N0001 +arc: A4 V02S0301 +arc: B3 H01W0100 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D3 V02N0201 +arc: D4 E1_H02W0201 +arc: E3_H06E0203 F4 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q4 +arc: M0 W1_H02E0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0501 Q5 +arc: V00T0000 Q0 +arc: V01S0000 Q3 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111010110100000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C44:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 W1_H02E0501 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 V02N0101 +arc: B0 H02E0301 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: E1_H02E0501 Q5 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: M5 H00R0100 +arc: MUXCLK2 CLK0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C45:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: V00B0000 H02W0601 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0201 W3_H06E0103 +arc: A2 H02E0501 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D2 V00T0100 +arc: F2 F2_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q7 +arc: M6 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 F2 +arc: V01S0100 Q6 +word: SLICEB.K0.INIT 1010101011110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C46:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: W1_H02W0601 N1_V02S0601 + +.tile R33C48:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R33C49:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 + +.tile R33C50:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 + +.tile R33C51:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R33C52:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N3_V06N0003 W3_H06E0003 + +.tile R33C54:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R33C55:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 + +.tile R33C56:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 + +.tile R33C57:PLC2 +arc: N3_V06N0303 W3_H06E0303 + +.tile R33C58:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R33C60:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R33C61:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0203 W3_H06E0203 + +.tile R33C62:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 + +.tile R33C64:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R33C66:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R33C67:PLC2 +arc: N3_V06N0303 W3_H06E0303 + +.tile R33C68:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 + +.tile R33C6:PLC2 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R33C70:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R33C72:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R33C74:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 + +.tile R33C76:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R33C78:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R33C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R33C80:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 + +.tile R33C82:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R33C84:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R33C86:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 + +.tile R33C87:PLC2 +arc: S3_V06S0103 H06E0103 + +.tile R33C88:PLC2 +arc: E1_H01E0101 W3_H06E0203 + +.tile R35C10:PLC2 +arc: S3_V06S0003 E3_H06W0003 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0103 + +.tile R35C11:PLC2 +arc: H01W0100 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 + +.tile R35C12:PLC2 +arc: H01W0100 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 + +.tile R35C13:PLC2 +arc: S3_V06S0303 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile R35C14:PLC2 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R35C15:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R35C16:PLC2 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 + +.tile R35C17:PLC2 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R35C18:PLC2 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R35C19:PLC2 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 + +.tile R35C20:PLC2 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 + +.tile R35C21:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R35C22:PLC2 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 + +.tile R35C23:PLC2 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R35C24:PLC2 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 + +.tile R35C25:PLC2 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0303 + +.tile R35C26:PLC2 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R35C27:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R35C28:PLC2 +arc: E1_H02E0401 V06S0203 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 + +.tile R35C29:PLC2 +arc: H00L0100 H02W0101 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 V02S0501 +arc: C1 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 V00T0100 +arc: F1 F1_SLICE +arc: M3 H00L0100 +arc: MUXCLK1 CLK0 +arc: V00T0100 Q3 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R35C2:PLC2 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 E3_H06W0203 +arc: S3_V06S0303 H06W0303 + +.tile R35C30:PLC2 +arc: H00R0000 V02N0401 +arc: W3_H06W0103 E3_H06W0003 +arc: A6 V02S0101 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D6 E1_H02W0001 +arc: E3_H06E0103 Q1 +arc: F6 F6_SLICE +arc: M1 H00R0000 +arc: M2 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1111000010101010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R35C31:PLC2 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R35C32:PLC2 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 E1_H02W0001 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H00L0000 +arc: C0 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: F0 F0_SLICE +arc: H00L0000 Q2 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R35C33:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 + +.tile R35C34:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 S1_V02N0401 +arc: W1_H02W0001 V06S0003 +arc: W3_H06W0003 E1_H01W0000 +arc: B1 V02S0101 +arc: C1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0001 +arc: E1_H02E0301 Q3 +arc: F1 F1_SLICE +arc: H00R0100 Q5 +arc: M3 H00R0000 +arc: M5 V01S0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 Q3 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1111001111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R35C35:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 H02E0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 V01N0101 +arc: V00B0000 V02S0001 +arc: V00B0100 H02E0501 +arc: W3_H06W0203 E1_H01W0000 +arc: B0 H01W0100 +arc: B2 V01N0001 +arc: B3 N1_V02S0101 +arc: C0 H00L0000 +arc: C2 H00L0000 +arc: C3 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 H00R0000 +arc: D2 V02S0201 +arc: D3 H02E0001 +arc: E1_H01E0001 Q6 +arc: E1_H02E0601 Q6 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q4 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: M7 W1_H02E0201 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0501 Q7 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R35C36:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V02S0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0301 W1_H02E0301 +arc: V00B0100 H02E0701 +arc: W3_H06W0003 E3_H06W0003 +arc: B3 H02W0101 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D3 V02S0201 +arc: E1_H01E0101 Q2 +arc: E3_H06E0103 Q2 +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +word: SLICEB.K1.INIT 1111001111000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R35C37:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 V02S0001 +arc: H00L0100 H02E0101 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H01E0101 +arc: V00B0000 V02N0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 V06S0103 +arc: A5 N1_V01S0100 +arc: B3 H02W0301 +arc: B4 V01S0000 +arc: B6 H02E0301 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C5 V00T0000 +arc: C6 V02S0001 +arc: CLK0 G_HPBX0000 +arc: D3 V00T0100 +arc: D4 V02S0601 +arc: D5 H02W0201 +arc: D6 H01W0000 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 Q7 +arc: E3_H06E0303 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: M0 V00B0100 +arc: M1 H02W0001 +arc: M2 W1_H02E0601 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: M7 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0303 F5 +arc: V00B0100 Q7 +arc: V00T0000 Q2 +arc: V01S0000 Q5 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 Q6 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1100111111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R35C38:PLC2 +arc: N1_V02N0701 H02E0701 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02S0201 +arc: B1 H02E0101 +arc: C1 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D1 V00B0100 +arc: F1 F1_SLICE +arc: H00R0000 Q4 +arc: M1 H00R0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 Q4 +arc: W1_H02W0301 Q1 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1111001111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C39:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: W1_H02W0701 V02S0701 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0001 Q0 +arc: H00L0000 Q0 +arc: H01W0000 Q7 +arc: M0 V00B0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C3:PLC2 +arc: E3_H06E0203 W1_H02E0701 +arc: S3_V06S0303 H06W0303 +arc: W1_H02W0501 E1_H02W0501 + +.tile R35C40:PLC2 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: V01S0000 N3_V06S0103 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0201 Q0 +arc: M0 H02W0601 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C41:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 W1_H02E0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0601 V06N0303 +arc: CLK0 G_HPBX0000 +arc: M0 V00B0100 +arc: MUXCLK0 CLK0 +arc: W1_H02W0001 Q0 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C42:PLC2 +arc: E1_H02E0001 V02S0001 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0601 N1_V02S0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A3 V01N0101 +arc: B2 H00R0100 +arc: C2 V02S0601 +arc: C3 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: E1_H02E0201 Q0 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: H01W0000 Q7 +arc: M0 H02E0601 +arc: M4 W1_H02E0401 +arc: M5 H00R0000 +arc: M7 W1_H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: V01S0100 Q0 +arc: W3_H06W0003 F3 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R35C43:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0201 H06W0103 +arc: W1_H02W0201 V06S0103 +arc: A2 V02S0701 +arc: B3 V02N0301 +arc: C2 W1_H02E0401 +arc: C3 N1_V01N0001 +arc: CLK0 G_HPBX0000 +arc: D2 H00R0000 +arc: D3 H02E0001 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q6 +arc: M6 H02W0401 +arc: M7 H00R0100 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 1111000010101010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R35C44:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 W1_H02E0201 +arc: N1_V02N0201 E1_H01W0000 +arc: W1_H02W0401 E1_H02W0401 + +.tile R35C45:PLC2 +arc: E1_H02E0101 V02S0101 +arc: H00R0000 S1_V02N0401 +arc: B3 H02E0101 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D3 W1_H02E0201 +arc: E1_H01E0101 Q3 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: H01W0000 Q1 +arc: M1 H00R0000 +arc: M3 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V01S0000 Q1 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C46:PLC2 +arc: W1_H02W0401 E3_H06W0203 +arc: B3 H02E0101 +arc: C3 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D3 H01E0101 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q7 +arc: M1 H02W0001 +arc: M7 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: W3_H06W0103 Q1 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C47:PLC2 +arc: W1_H02W0001 E3_H06W0003 + +.tile R35C48:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R35C49:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 + +.tile R35C4:PLC2 +arc: S3_V06S0203 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E1_H01W0000 + +.tile R35C51:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R35C52:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: W3_H06W0203 E3_H06W0203 + +.tile R35C53:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R35C54:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R35C55:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 + +.tile R35C57:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R35C58:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile R35C59:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R35C5:PLC2 +arc: H01W0000 E3_H06W0103 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R35C60:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R35C61:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 + +.tile R35C63:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R35C64:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile R35C65:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R35C66:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R35C67:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 + +.tile R35C69:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R35C6:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R35C70:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: W3_H06W0103 E3_H06W0103 + +.tile R35C71:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R35C72:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R35C73:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 + +.tile R35C75:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R35C76:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: W3_H06W0103 E3_H06W0003 + +.tile R35C77:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R35C78:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R35C79:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 + +.tile R35C7:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R35C81:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R35C82:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: W3_H06W0003 E3_H06W0003 + +.tile R35C83:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R35C84:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R35C85:PLC2 +arc: S3_V06S0303 W3_H06E0303 + +.tile R35C87:PLC2 +arc: E1_H02E0701 W3_H06E0203 +arc: S3_V06S0203 H06E0203 + +.tile R35C88:PLC2 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 + +.tile R35C8:PLC2 +arc: S3_V06S0303 E3_H06W0303 +arc: W3_H06W0203 E3_H06W0103 + +.tile R35C9:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R36C12:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R36C15:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R36C18:PLC2 +arc: S3_V06S0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile R36C21:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R36C24:PLC2 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 + +.tile R36C27:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R36C30:PLC2 +arc: N1_V02N0401 H06E0203 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0203 + +.tile R36C33:PLC2 +arc: E1_H02E0001 V02N0001 + +.tile R36C34:PLC2 +arc: E1_H02E0601 S1_V02N0601 + +.tile R36C35:PLC2 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 Q5 +arc: M2 H02E0601 +arc: M5 W1_H02E0001 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q5 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C36:PLC2 +arc: E3_H06E0103 H01E0101 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R36C37:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q1 +arc: M1 H00R0100 +arc: MUXCLK0 CLK0 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C38:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 N1_V01S0000 + +.tile R36C39:PLC2 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 S1_V02N0301 + +.tile R36C3:PLC2 +arc: E3_H06E0303 W1_H02E0601 +arc: S3_V06S0303 H06W0303 + +.tile R36C40:PLC2 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0201 S1_V02N0701 + +.tile R36C41:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0301 S1_V02N0201 + +.tile R36C42:PLC2 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 H02W0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0201 N1_V02S0201 +arc: V00B0000 V02N0201 +arc: V00T0000 V02S0601 +arc: A6 H00L0000 +arc: B7 V01S0000 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0101 Q6 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M0 V00T0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q3 +arc: V01S0000 Q4 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1100111111000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C43:PLC2 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 H06E0203 +arc: W1_H02W0401 N1_V02S0401 + +.tile R36C44:PLC2 +arc: E1_H02E0001 N1_V02S0001 + +.tile R36C45:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: V00B0100 V02N0101 +arc: A0 H00R0000 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: H00R0000 Q4 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: W1_H02W0401 Q6 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R36C46:PLC2 +arc: CLK0 G_HPBX0000 +arc: M2 H02E0601 +arc: MUXCLK1 CLK0 +arc: V01S0000 Q2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R36C51:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R36C57:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R36C63:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R36C69:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R36C6:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R36C75:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R36C81:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R36C87:PLC2 +arc: S3_V06S0203 W3_H06E0203 + +.tile R36C9:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R37C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R37C15:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: S3_V06S0203 H06W0203 + +.tile R37C18:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R37C19:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R37C21:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R37C24:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R37C25:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R37C27:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R37C30:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R37C31:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R37C33:PLC2 +arc: N1_V02N0001 W3_H06E0003 + +.tile R37C34:PLC2 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06E0303 + +.tile R37C36:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R37C37:PLC2 +arc: N1_V02N0701 E1_H02W0701 + +.tile R37C38:PLC2 +arc: N1_V02N0701 H06W0203 + +.tile R37C39:PLC2 +arc: W1_H02W0701 E1_H02W0701 + +.tile R37C40:PLC2 +arc: H00R0000 V02N0601 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0501 Q5 +arc: M5 H00R0000 +arc: MUXCLK2 CLK0 +arc: N1_V02N0501 Q5 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C41:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 S1_V02N0601 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0203 S3_V06N0203 + +.tile R37C42:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: H00R0000 H02W0601 +arc: A0 E1_H01E0001 +arc: A5 V02N0101 +arc: B0 V02N0101 +arc: C5 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D5 H01W0000 +arc: E1_H01E0001 Q6 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: M0 H02E0601 +arc: M1 V01S0100 +arc: M3 H00R0000 +arc: M6 V00B0100 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0201 Q0 +arc: V00B0100 Q7 +arc: V01S0100 Q3 +arc: W3_H06W0003 F0 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1011101110001000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C43:PLC2 +arc: V00B0100 H02E0501 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0601 V06N0303 +arc: B1 V00T0000 +arc: C1 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D1 V02N0201 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q2 +word: SLICEA.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C45:PLC2 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H02W0601 + +.tile R37C46:PLC2 +arc: H01W0000 E3_H06W0103 +arc: W1_H02W0601 V01N0001 +arc: B4 N1_V01S0000 +arc: C4 H02E0601 +arc: D4 V01N0001 +arc: E3_H06E0203 F4 +arc: F4 F4_SLICE +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R37C47:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R37C48:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R37C49:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R37C51:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R37C52:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0003 + +.tile R37C53:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R37C54:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R37C55:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R37C57:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R37C58:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0303 + +.tile R37C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R37C60:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R37C61:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R37C63:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R37C64:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: W3_H06W0303 E3_H06W0203 + +.tile R37C65:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R37C66:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R37C67:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R37C69:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R37C70:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: W3_H06W0203 E3_H06W0103 + +.tile R37C71:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R37C72:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R37C73:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R37C75:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R37C76:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: W3_H06W0103 E3_H06W0103 + +.tile R37C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R37C78:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R37C79:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R37C7:PLC2 +arc: E1_H02E0501 S3_V06N0303 +arc: E3_H06E0303 W3_H06E0303 + +.tile R37C81:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R37C82:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: W3_H06W0103 E3_H06W0103 + +.tile R37C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R37C84:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R37C85:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R37C87:PLC2 +arc: S1_V02S0501 H06E0303 +arc: W3_H06W0303 E1_H02W0601 + +.tile R37C88:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: S3_V06S0203 H06E0203 +arc: W3_H06W0103 E1_H01W0100 + +.tile R37C9:PLC2 +arc: E3_H06E0303 W1_H02E0501 + +.tile R38C12:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R38C13:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 + +.tile R38C15:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R38C18:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R38C19:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 + +.tile R38C21:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R38C24:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R38C25:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 + +.tile R38C27:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R38C2:PLC2 +arc: W1_H02W0501 E3_H06W0303 + +.tile R38C30:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R38C31:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 + +.tile R38C33:PLC2 +arc: E1_H02E0101 W3_H06E0103 + +.tile R38C34:PLC2 +arc: V00T0100 H02E0101 +arc: CLK0 G_HPBX0000 +arc: E3_H06E0203 Q4 +arc: M4 V00T0100 +arc: MUXCLK2 CLK0 +arc: N1_V02N0601 Q4 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C36:PLC2 +arc: B4 H02W0101 +arc: C4 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D4 S1_V02N0401 +arc: E3_H06E0003 Q0 +arc: F4 F4_SLICE +arc: M0 H02W0601 +arc: M1 V01S0100 +arc: MUXCLK0 CLK0 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +arc: W3_H06W0203 F4 +word: SLICEC.K0.INIT 1111001111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R38C37:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0601 V02N0601 +arc: A1 E1_H02W0701 +arc: C1 S1_V02N0601 +arc: D1 S1_V02N0001 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +word: SLICEA.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R38C39:PLC2 +arc: N1_V02N0301 H06E0003 +arc: W1_H02W0701 S1_V02N0701 + +.tile R38C3:PLC2 +arc: E3_H06E0303 W1_H02E0601 +arc: S3_V06S0103 H06W0103 + +.tile R38C40:PLC2 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 W3_H06E0203 + +.tile R38C41:PLC2 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 + +.tile R38C42:PLC2 +arc: N1_V02N0101 H02W0101 + +.tile R38C43:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0201 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 + +.tile R38C46:PLC2 +arc: N1_V01N0001 N3_V06S0003 + +.tile R38C47:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R38C49:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R38C53:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R38C55:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R38C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R38C61:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R38C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R38C67:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R38C6:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R38C71:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R38C73:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R38C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R38C79:PLC2 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0103 W3_H06E0003 + +.tile R38C7:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 + +.tile R38C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R38C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 + +.tile R38C86:PLC2 +arc: E3_H06E0203 H01E0001 + +.tile R38C87:PLC2 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V06S0203 + +.tile R38C88:PLC2 +arc: S3_V06S0203 H06E0203 + +.tile R38C8:PLC2 +arc: W3_H06W0303 V06S0303 + +.tile R38C9:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R39C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R39C19:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R39C25:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R39C31:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R39C34:PLC2 +arc: N1_V02N0101 S1_V02N0101 + +.tile R39C37:PLC2 +arc: H00R0000 V02N0401 +arc: N1_V02N0601 W3_H06E0303 +arc: CLK0 G_HPBX0000 +arc: M1 H00R0000 +arc: MUXCLK0 CLK0 +arc: V01S0000 Q1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C41:PLC2 +arc: N1_V02N0601 S1_V02N0601 + +.tile R39C7:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R39C87:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R3C17:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R3C19:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R3C23:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R3C35:PLC2 +arc: N1_V02N0701 S1_V02N0701 + +.tile R3C37:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R3C39:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R3C41:PLC2 +arc: S3_V06S0103 N1_V02S0201 + +.tile R3C42:PLC2 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 N1_V02S0201 + +.tile R3C52:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R3C57:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R3C61:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R3C67:PLC2 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 + +.tile R3C70:PLC2 +arc: N1_V02N0701 H06E0203 + +.tile R40C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R40C19:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R40C25:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R40C31:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R40C33:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R40C34:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R40C35:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R40C36:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 + +.tile R40C37:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S3_V06N0203 +arc: V00T0100 H02E0301 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 Q4 +arc: M4 V00T0100 +arc: MUXCLK2 CLK0 +arc: N1_V02N0401 Q4 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C38:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 H01E0101 +arc: W1_H02W0401 N3_V06S0203 + +.tile R40C39:PLC2 +arc: N1_V02N0701 N3_V06S0203 + +.tile R40C41:PLC2 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 + +.tile R40C43:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 W3_H06E0303 + +.tile R40C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R40C53:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R40C59:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R40C65:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R40C71:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R40C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R40C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R40C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R41C10:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R41C13:PLC2 +arc: S3_V06S0003 N3_V06S0303 + +.tile R41C2:PLC2 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 N3_V06S0203 + +.tile R41C34:PLC2 +arc: N1_V02N0101 S3_V06N0103 + +.tile R41C37:PLC2 +arc: E3_H06E0303 N3_V06S0303 + +.tile R41C3:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R41C41:PLC2 +arc: N1_V02N0601 E3_H06W0303 + +.tile R41C43:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R41C47:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R41C49:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R41C4:PLC2 +arc: W1_H02W0401 N3_V06S0203 + +.tile R41C53:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R41C55:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R41C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R41C61:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R41C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R41C67:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R41C71:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R41C73:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R41C77:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R41C79:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R41C83:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R41C85:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0303 W3_H06E0203 + +.tile R41C87:PLC2 +arc: E1_H02E0501 W1_H02E0501 + +.tile R41C88:PLC2 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 + +.tile R42C18:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R42C3:PLC2 +arc: W1_H02W0501 N3_V06S0303 + +.tile R42C87:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R43C15:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R43C41:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R43C7:PLC2 +arc: N3_V06N0303 W3_H06E0303 + +.tile R43C88:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R44C37:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R44C3:PLC2 +arc: S3_V06S0203 N3_V06S0103 +arc: W1_H02W0501 V06S0303 + +.tile R44C41:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 E3_H06W0203 + +.tile R44C47:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R44C53:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R44C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R44C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R44C71:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R44C77:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R44C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R44C88:PLC2 +arc: E1_H02E0701 V06S0203 +arc: S3_V06S0203 N3_V06S0203 + +.tile R45C87:PLC2 +arc: E1_H02E0401 N3_V06S0203 + +.tile R47C10:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R47C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: S3_V06S0103 N3_V06S0003 + +.tile R47C19:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R47C25:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R47C2:PLC2 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 + +.tile R47C31:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R47C34:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R47C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R47C88:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 V06S0203 + +.tile R48C18:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R48C87:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R49C15:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R49C41:PLC2 +arc: N3_V06N0103 E3_H06W0103 + +.tile R49C47:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R49C53:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R49C59:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R49C65:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R49C71:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R49C77:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R49C83:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R49C88:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R4C24:PLC2 +arc: N3_V06N0203 S1_V02N0401 + +.tile R4C49:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R50C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R50C19:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R50C25:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R50C31:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R50C37:PLC2 +arc: N3_V06N0303 W3_H06E0303 + +.tile R50C3:PLC2 +arc: W1_H02W0701 N3_V06S0203 + +.tile R50C41:PLC2 +arc: N3_V06N0003 E3_H06W0003 + +.tile R50C47:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R50C53:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R50C59:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R50C65:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R50C71:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R50C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R50C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R50C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R52C33:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R52C34:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R52C35:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R52C36:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R52C37:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R52C38:PLC2 +arc: N3_V06N0303 H06W0303 + +.tile R52C41:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R52C43:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R52C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R52C53:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R52C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R52C65:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R52C71:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R52C77:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R52C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R52C88:PLC2 +arc: E1_H02E0501 V06S0303 + +.tile R53C10:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R53C13:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R54C18:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R54C87:PLC2 +arc: V01S0100 N3_V06S0303 + +.tile R55C15:PLC2 +arc: S3_V06S0003 N3_V06S0303 + +.tile R55C87:PLC2 +arc: E1_H02E0501 N1_V01S0100 + +.tile R59C10:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R59C13:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R5C35:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R60C18:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R61C15:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R64C33:PLC2 +arc: N3_V06N0003 S3_V06N0303 + +.tile R64C34:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R64C35:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R64C36:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R64C37:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R64C43:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R65C10:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R65C13:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R66C18:PLC2 +arc: S1_V02S0401 N3_V06S0203 + +.tile R67C15:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R68C10:PLC2 +arc: E1_H02E0501 V06S0303 + +.tile R68C11:PLC2 +arc: S1_V02S0501 H02E0501 + +.tile R68C12:PLC2 +arc: S1_V02S0701 H02W0701 + +.tile R68C13:PLC2 +arc: W1_H02W0701 V06S0203 + +.tile R68C18:PLC2 +arc: S1_V02S0501 N1_V02S0401 + +.tile R6C24:PLC2 +arc: N1_V02N0401 S3_V06N0203 + +.tile R7C30:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R7C34:PLC2 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0203 + +.tile R7C35:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R7C36:PLC2 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 + +.tile R7C37:PLC2 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 + +.tile R7C38:PLC2 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 + +.tile R7C39:PLC2 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 + +.tile R7C40:PLC2 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 + +.tile R7C41:PLC2 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 + +.tile R7C42:PLC2 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0100 N3_V06S0303 + +.tile R7C43:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R7C44:PLC2 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 + +.tile R7C45:PLC2 +arc: S3_V06S0003 N3_V06S0303 + +.tile R7C46:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R7C67:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R8C31:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R8C42:PLC2 +arc: N3_V06N0203 S3_V06N0103 +arc: S3_V06S0303 N1_V01S0100 + +.tile R8C43:PLC2 +arc: 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"DONTCARE", + "CH0_TX_CM_SEL": "DONTCARE", + "CH0_TX_DIV11_SEL": "DONTCARE", + "CH0_TX_GEAR_BYPASS": "DONTCARE", + "CH0_TX_GEAR_MODE": "DONTCARE", + "CH0_TX_POST_SIGN": "DONTCARE", + "CH0_TX_PRE_SIGN": "DONTCARE", + "CH0_UC_MODE": "DONTCARE", + "CH0_UDF_COMMA_A": "DONTCARE", + "CH0_UDF_COMMA_B": "DONTCARE", + "CH0_UDF_COMMA_MASK": "DONTCARE", + "CH0_WA_BYPASS": "DONTCARE", + "CH0_WA_MODE": "DONTCARE", + "CH1_AUTO_CALIB_EN": "DONTCARE", + "CH1_AUTO_FACQ_EN": "DONTCARE", + "CH1_BAND_THRESHOLD": "DONTCARE", + "CH1_CALIB_CK_MODE": "DONTCARE", + "CH1_CC_MATCH_1": "DONTCARE", + "CH1_CC_MATCH_2": "DONTCARE", + "CH1_CC_MATCH_3": "DONTCARE", + "CH1_CC_MATCH_4": "DONTCARE", + "CH1_CDR_CNT4SEL": "DONTCARE", + "CH1_CDR_CNT8SEL": "DONTCARE", + "CH1_CDR_MAX_RATE": "DONTCARE", + "CH1_CTC_BYPASS": "DONTCARE", + "CH1_DCOATDCFG": "DONTCARE", + "CH1_DCOATDDLY": "DONTCARE", + "CH1_DCOBYPSATD": "DONTCARE", + "CH1_DCOCALDIV": "DONTCARE", + "CH1_DCOCTLGI": "DONTCARE", + "CH1_DCODISBDAVOID": "DONTCARE", + "CH1_DCOFLTDAC": "DONTCARE", + "CH1_DCOFTNRG": "DONTCARE", + "CH1_DCOIOSTUNE": "DONTCARE", + "CH1_DCOITUNE": "DONTCARE", + "CH1_DCOITUNE4LSB": "DONTCARE", + "CH1_DCOIUPDNX2": "DONTCARE", + "CH1_DCONUOFLSB": "DONTCARE", + "CH1_DCOSCALEI": "DONTCARE", + "CH1_DCOSTARTVAL": "DONTCARE", + "CH1_DCOSTEP": "DONTCARE", + "CH1_DEC_BYPASS": "DONTCARE", + "CH1_ENABLE_CG_ALIGN": "DONTCARE", + "CH1_ENC_BYPASS": "DONTCARE", + "CH1_FF_RX_F_CLK_DIS": "DONTCARE", + "CH1_FF_RX_H_CLK_EN": "DONTCARE", + "CH1_FF_TX_F_CLK_DIS": "DONTCARE", + "CH1_FF_TX_H_CLK_EN": "DONTCARE", + "CH1_GE_AN_ENABLE": "DONTCARE", + "CH1_INVERT_RX": "DONTCARE", + "CH1_INVERT_TX": "DONTCARE", + "CH1_LDR_CORE2TX_SEL": "DONTCARE", + "CH1_LDR_RX2CORE_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_TRIM": "DONTCARE", + "CH1_LSM_DISABLE": "DONTCARE", + "CH1_MATCH_2_ENABLE": "DONTCARE", + "CH1_MATCH_4_ENABLE": "DONTCARE", + "CH1_MIN_IPG_CNT": "DONTCARE", + "CH1_PCIE_EI_EN": "DONTCARE", + "CH1_PCIE_MODE": "DONTCARE", + "CH1_PCS_DET_TIME_SEL": "DONTCARE", + "CH1_PDEN_SEL": "DONTCARE", + "CH1_PRBS_ENABLE": "DONTCARE", + "CH1_PRBS_LOCK": "DONTCARE", + "CH1_PRBS_SELECTION": "DONTCARE", + "CH1_PROTOCOL": "DONTCARE", + "CH1_RATE_MODE_RX": "DONTCARE", + "CH1_RATE_MODE_TX": "DONTCARE", + "CH1_RCV_DCC_EN": "DONTCARE", + "CH1_REG_BAND_OFFSET": "DONTCARE", + "CH1_REG_BAND_SEL": "DONTCARE", + "CH1_REG_IDAC_EN": "DONTCARE", + "CH1_REG_IDAC_SEL": "DONTCARE", + "CH1_REQ_EN": "DONTCARE", + "CH1_REQ_LVL_SET": "DONTCARE", + "CH1_RIO_MODE": "DONTCARE", + "CH1_RLOS_SEL": "DONTCARE", + "CH1_RPWDNB": "DONTCARE", + "CH1_RTERM_RX": "DONTCARE", + "CH1_RTERM_TX": "DONTCARE", + "CH1_RXIN_CM": "DONTCARE", + "CH1_RXTERM_CM": "DONTCARE", + "CH1_RX_DCO_CK_DIV": "DONTCARE", + "CH1_RX_DIV11_SEL": "DONTCARE", + "CH1_RX_GEAR_BYPASS": "DONTCARE", + "CH1_RX_GEAR_MODE": "DONTCARE", + "CH1_RX_LOS_CEQ": "DONTCARE", + "CH1_RX_LOS_EN": "DONTCARE", + "CH1_RX_LOS_HYST_EN": "DONTCARE", + "CH1_RX_LOS_LVL": "DONTCARE", + "CH1_RX_RATE_SEL": "DONTCARE", + "CH1_RX_SB_BYPASS": "DONTCARE", + "CH1_SB_BYPASS": "DONTCARE", + "CH1_SEL_SD_RX_CLK": "DONTCARE", + "CH1_TDRV_DAT_SEL": "DONTCARE", + "CH1_TDRV_POST_EN": "DONTCARE", + "CH1_TDRV_PRE_EN": "DONTCARE", + "CH1_TDRV_SLICE0_CUR": "DONTCARE", + "CH1_TDRV_SLICE0_SEL": "DONTCARE", + "CH1_TDRV_SLICE1_CUR": "DONTCARE", + "CH1_TDRV_SLICE1_SEL": "DONTCARE", + "CH1_TDRV_SLICE2_CUR": "DONTCARE", + "CH1_TDRV_SLICE2_SEL": "DONTCARE", + "CH1_TDRV_SLICE3_CUR": "DONTCARE", + "CH1_TDRV_SLICE3_SEL": "DONTCARE", + "CH1_TDRV_SLICE4_CUR": "DONTCARE", + "CH1_TDRV_SLICE4_SEL": "DONTCARE", + "CH1_TDRV_SLICE5_CUR": "DONTCARE", + "CH1_TDRV_SLICE5_SEL": "DONTCARE", + "CH1_TPWDNB": "DONTCARE", + "CH1_TXAMPLITUDE": "DONTCARE", + "CH1_TXDEPOST": "DONTCARE", + "CH1_TXDEPRE": "DONTCARE", + "CH1_TX_CM_SEL": "DONTCARE", + "CH1_TX_DIV11_SEL": "DONTCARE", + "CH1_TX_GEAR_BYPASS": "DONTCARE", + "CH1_TX_GEAR_MODE": "DONTCARE", + "CH1_TX_POST_SIGN": "DONTCARE", + "CH1_TX_PRE_SIGN": "DONTCARE", + "CH1_UC_MODE": "DONTCARE", + "CH1_UDF_COMMA_A": "DONTCARE", + "CH1_UDF_COMMA_B": "DONTCARE", + "CH1_UDF_COMMA_MASK": "DONTCARE", + "CH1_WA_BYPASS": "DONTCARE", + "CH1_WA_MODE": "DONTCARE", + "D_BITCLK_FROM_ND_EN": "DONTCARE", + "D_BITCLK_LOCAL_EN": "DONTCARE", + "D_BITCLK_ND_EN": "DONTCARE", + "D_BUS8BIT_SEL": "DONTCARE", + "D_CDR_LOL_SET": "DONTCARE", + "D_CMUSETBIASI": "DONTCARE", + "D_CMUSETI4CPP": "DONTCARE", + "D_CMUSETI4CPZ": "DONTCARE", + "D_CMUSETI4VCO": "DONTCARE", + "D_CMUSETICP4P": "DONTCARE", + "D_CMUSETICP4Z": "DONTCARE", + "D_CMUSETINITVCT": "DONTCARE", + "D_CMUSETISCL4VCO": "DONTCARE", + "D_CMUSETP1GM": "DONTCARE", + "D_CMUSETP2AGM": "DONTCARE", + "D_CMUSETZGM": "DONTCARE", + "D_DCO_CALIB_TIME_SEL": "DONTCARE", + "D_HIGH_MARK": "DONTCARE", + "D_IB_PWDNB": "DONTCARE", + "D_ISETLOS": "DONTCARE", + "D_LOW_MARK": "DONTCARE", + "D_MACROPDB": "DONTCARE", + "D_PD_ISET": "DONTCARE", + "D_PLL_LOL_SET": "DONTCARE", + "D_REFCK_MODE": "DONTCARE", + "D_REQ_ISET": "DONTCARE", + "D_RG_EN": "DONTCARE", + "D_RG_SET": "DONTCARE", + "D_SETICONST_AUX": "DONTCARE", + "D_SETICONST_CH": "DONTCARE", + "D_SETIRPOLY_AUX": "DONTCARE", + "D_SETIRPOLY_CH": "DONTCARE", + "D_SETPLLRC": "DONTCARE", + "D_SYNC_LOCAL_EN": "DONTCARE", + "D_SYNC_ND_EN": "DONTCARE", + "D_TXPLL_PWDNB": "DONTCARE", + "D_TX_MAX_RATE": "DONTCARE", + "D_TX_VCO_CK_DIV": "DONTCARE", + "D_XGE_MODE": "DONTCARE" + }, + "ports": { + "CH0_HDINP": { + "direction": "input", + "bits": [ 2 ] + }, + "CH1_HDINP": { + "direction": "input", + "bits": [ 3 ] + }, + "CH0_HDINN": { + "direction": "input", + "bits": [ 4 ] + }, + "CH1_HDINN": { + "direction": "input", + "bits": [ 5 ] + }, + "D_TXBIT_CLKP_FROM_ND": { + "direction": "input", + "bits": [ 6 ] + }, + "D_TXBIT_CLKN_FROM_ND": { + "direction": "input", + "bits": [ 7 ] + }, + "D_SYNC_ND": { + "direction": "input", + "bits": [ 8 ] + }, + "D_TXPLL_LOL_FROM_ND": { + "direction": "input", + "bits": [ 9 ] + }, + "CH0_RX_REFCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "CH1_RX_REFCLK": { + "direction": "input", + "bits": [ 11 ] + }, + "CH0_FF_RXI_CLK": { + "direction": "input", + "bits": [ 12 ] + }, + "CH1_FF_RXI_CLK": { + "direction": "input", + "bits": [ 13 ] + }, + "CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 86 ] + }, + "CH1_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 87 ] + }, + "CH0_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 88 ] + }, + "CH1_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 89 ] + }, + "CH0_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 90 ] + }, + "CH1_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 91 ] + }, + "CH0_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 92 ] + }, + "CH1_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 93 ] + }, + "CH0_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 94 ] + }, + "CH1_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 95 ] + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 96 ] + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 97 ] + }, + "CH0_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 98 ] + }, + "CH1_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 99 ] + }, + "CH0_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 100 ] + }, + "CH1_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 101 ] + }, + "CH0_FFC_RRST": { + "direction": "input", + "bits": [ 102 ] + }, + "CH1_FFC_RRST": { + "direction": "input", + "bits": [ 103 ] + }, + "CH0_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 104 ] + }, + "CH1_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 105 ] + }, + "CH0_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 106 ] + }, + "CH1_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 107 ] + }, + "CH0_LDR_CORE2TX": { + "direction": "input", + "bits": [ 108 ] + }, + "CH1_LDR_CORE2TX": { + "direction": "input", + "bits": [ 109 ] + }, + "D_SCIWDATA0": { + "direction": "input", + "bits": [ 110 ] + }, + "D_SCIWDATA1": { + "direction": "input", + "bits": [ 111 ] + }, + "D_SCIWDATA2": { + "direction": "input", + "bits": [ 112 ] + }, + "D_SCIWDATA3": { + "direction": "input", + "bits": [ 113 ] + }, + "D_SCIWDATA4": { + "direction": "input", + "bits": [ 114 ] + }, + "D_SCIWDATA5": { + "direction": "input", + "bits": [ 115 ] + }, + "D_SCIWDATA6": { + "direction": "input", + "bits": [ 116 ] + }, + "D_SCIWDATA7": { + "direction": "input", + "bits": [ 117 ] + }, + "D_SCIADDR0": { + "direction": "input", + "bits": [ 118 ] + }, + "D_SCIADDR1": { + "direction": "input", + "bits": [ 119 ] + }, + "D_SCIADDR2": { + "direction": "input", + "bits": [ 120 ] + }, + "D_SCIADDR3": { + "direction": "input", + "bits": [ 121 ] + }, + "D_SCIADDR4": { + "direction": "input", + "bits": [ 122 ] + }, + "D_SCIADDR5": { + "direction": "input", + "bits": [ 123 ] + }, + "D_SCIENAUX": { + "direction": "input", + "bits": [ 124 ] + }, + "D_SCISELAUX": { + "direction": "input", + "bits": [ 125 ] + }, + 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c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) + +-- Parsing `hardware/v2/rtl/weight_buffer.v' using frontend ` -vlog2k' -- + +1. Executing Verilog-2005 frontend: hardware/v2/rtl/weight_buffer.v +Parsing Verilog input from `hardware/v2/rtl/weight_buffer.v' to AST representation. +Storing AST representation for module `$abstract\weight_buffer'. +Successfully finished Verilog frontend. + +-- Running command `synth_ecp5 -json hardware/v2/synthesis/weight_buffer_d512/top.json -top weight_buffer' -- + +2. Executing SYNTH_LATTICE pass. + +2.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +2.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +2.3. Executing HIERARCHY pass (managing design hierarchy). + +2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\weight_buffer'. +Generating RTLIL representation for module `\weight_buffer'. + +2.4.1. Analyzing design hierarchy.. +Top module: \weight_buffer + +2.4.2. Analyzing design hierarchy.. +Top module: \weight_buffer +Removing unused module `$abstract\weight_buffer'. +Removed 1 unused modules. + +2.5. Executing PROC pass (convert processes to netlists). + +2.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +2.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/weight_buffer.v:39$227 in module weight_buffer. +Removed a total of 0 dead cases. + +2.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 4 assignments to connections. + +2.5.4. Executing PROC_INIT pass (extract init attributes). + +2.5.5. Executing PROC_ARST pass (detect async resets in processes). + +2.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +2.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:44$234'. +Creating decoders for process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$227'. + 1/3: $1$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$233 + 2/3: $1$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_DATA[63:0]$232 + 3/3: $1$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_ADDR[8:0]$231 + +2.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +2.5.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\weight_buffer.\rd_data' using process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:44$234'. + created $dff cell `$procdff$245' with positive edge clock. +Creating register for signal `\weight_buffer.$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_ADDR' using process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$227'. + created $dff cell `$procdff$246' with positive edge clock. +Creating register for signal `\weight_buffer.$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_DATA' using process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$227'. + created $dff cell `$procdff$247' with positive edge clock. +Creating register for signal `\weight_buffer.$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN' using process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$227'. + created $dff cell `$procdff$248' with positive edge clock. + +2.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +2.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:44$234'. +Found and cleaned up 1 empty switch in `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$227'. +Removing empty process `weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$227'. +Cleaned up 1 empty switch. + +2.5.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.6. Executing CHECK pass (checking for obvious problems). +Checking module weight_buffer... +Found and reported 0 problems. + +2.7. Executing FLATTEN pass (flatten design). + +2.8. Executing TRIBUF pass. + +2.9. Executing DEMINOUT pass (demote inout ports to input or output). + +2.10. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.11. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. +Removed 3 unused cells and 13 unused wires. + + +2.12. Executing CHECK pass (checking for obvious problems). +Checking module weight_buffer... +Found and reported 0 problems. + +2.13. Executing OPT pass (performing simple optimizations). + +2.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \weight_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \weight_buffer. + Consolidated identical input bits for $mux cell $procmux$237: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] + New connections: $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [63:1] = { $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] } + Optimizing cells in module \weight_buffer. +Performed a total of 1 changes. + +2.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +2.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \weight_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \weight_buffer. +Performed a total of 0 changes. + +2.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +2.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.13.16. Finished fast OPT passes. (There is nothing left to do.) + +2.14. Executing FSM pass (extract and optimize FSM). + +2.14.1. Executing FSM_DETECT pass (finding FSMs in design). + +2.14.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +2.14.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +2.14.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +2.14.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +2.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +2.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +2.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +2.15. Executing OPT pass (performing simple optimizations). + +2.15.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.15.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \weight_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \weight_buffer. +Performed a total of 0 changes. + +2.15.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.15.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +2.15.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.15.9. Finished fast OPT passes. (There is nothing left to do.) + +2.16. Executing WREDUCE pass (reducing word size of cells). + +2.17. Executing PEEPOPT pass (run peephole optimizers). + +2.18. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +2.19. Executing SHARE pass (SAT-based resource sharing). + +2.20. Executing TECHMAP pass (map to technology primitives). + +2.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +2.20.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.21. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.22. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +2.23. Executing TECHMAP pass (map to technology primitives). + +2.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +2.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.24. Executing TECHMAP pass (map to technology primitives). + +2.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +2.24.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.25. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module weight_buffer: + created 0 $alu and 0 $macc cells. + +2.26. Executing OPT pass (performing simple optimizations). + +2.26.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.26.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \weight_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \weight_buffer. +Performed a total of 0 changes. + +2.26.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.26.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.26.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +2.26.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.26.9. Finished fast OPT passes. (There is nothing left to do.) + +2.27. Executing MEMORY pass. + +2.27.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +2.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +2.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing weight_buffer.mem write port 0. + +2.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +2.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\mem'[0] in module `\weight_buffer': merging output FF to cell. + Write port 0: non-transparent. + +2.27.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. +Removed 1 unused cells and 65 unused wires. + + +2.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +2.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +2.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +2.27.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +2.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +2.29. Executing MEMORY_LIBMAP pass (mapping memories to cells). +mapping memory weight_buffer.mem via $__PDPW16KD_ + + +2.30. Executing TECHMAP pass (map to technology primitives). + +2.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +2.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +2.30.3. Continuing TECHMAP pass. +Using template $paramod$02d10cc8049219b734b94ed56325542341e7b150$__PDPW16KD_ for cells of type $__PDPW16KD_. +No more expansions possible. + + +2.31. Executing OPT pass (performing simple optimizations). + +2.31.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + + +2.31.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 10 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.31.3. Executing OPT_DFF pass (perform DFF optimizations). +Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$323 ($dffe) from module weight_buffer. + +2.31.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. +Removed 0 unused cells and 30 unused wires. + + +2.31.5. Rerunning OPT passes. (Removed registers in this run.) + +2.31.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.31.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 10 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.31.8. Executing OPT_DFF pass (perform DFF optimizations). + +2.31.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +2.31.10. Finished fast OPT passes. + +2.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +2.33. Executing OPT pass (performing simple optimizations). + +2.33.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.33.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 10 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \weight_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \weight_buffer. +Performed a total of 0 changes. + +2.33.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 10 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.33.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +2.33.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.33.9. Finished fast OPT passes. (There is nothing left to do.) + +2.34. Executing TECHMAP pass (map to technology primitives). + +2.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +2.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +2.34.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $eq. +No more expansions possible. + + +2.35. Executing OPT pass (performing simple optimizations). + +2.35.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.35.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 224 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.35.3. Executing OPT_DFF pass (perform DFF optimizations). + +2.35.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. +Removed 0 unused cells and 1 unused wires. + + +2.35.5. Finished fast OPT passes. + +2.36. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +2.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +2.38. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 224 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +2.39. Executing TECHMAP pass (map to technology primitives). + +2.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +2.39.2. Continuing TECHMAP pass. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +No more expansions possible. + + +2.40. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +2.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +2.42. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in weight_buffer. + +2.43. Executing ATTRMVCP pass (move or copy attributes). + +2.44. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. +Removed 0 unused cells and 556 unused wires. + + +2.45. Executing CHECK pass (checking for obvious problems). +Checking module weight_buffer... +Found and reported 0 problems. + +2.46. Executing TECHMAP pass (map to technology primitives). + +2.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +2.46.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.47. Executing ABC9 pass. + +2.47.1. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.2. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module weight_buffer. +Found 0 SCCs. + +2.47.4. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.5. Executing TECHMAP pass (map to technology primitives). + +2.47.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +2.47.5.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.47.6. Executing OPT pass (performing simple optimizations). + +2.47.6.1. Executing OPT_EXPR pass (perform const folding). + +2.47.6.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +2.47.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +2.47.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +2.47.6.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +2.47.6.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.47.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +2.47.6.8. Executing OPT_EXPR pass (perform const folding). + +2.47.6.9. Finished fast OPT passes. (There is nothing left to do.) + +2.47.7. Executing TECHMAP pass (map to technology primitives). + +2.47.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +2.47.7.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.47.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +2.47.9. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.10. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +2.47.12. Executing AIGMAP pass (map logic to AIG). +Module weight_buffer: replaced 81 cells with 543 new cells, skipped 143 cells. + replaced 3 cell types: + 64 $_MUX_ + 8 $_OR_ + 9 $_XOR_ + not replaced 4 cell types: + 1 $_AND_ + 1 $_NOT_ + 139 TRELLIS_FF + 2 DP16KD + +2.47.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.12.2. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.12.3. Executing XAIGER backend. + +Extracted 228 AND gates and 834 wires from module `weight_buffer' to a netlist network with 287 inputs and 139 outputs. + +2.47.12.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +2.47.12.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 287/ 139 and = 228 lev = 7 (0.97) mem = 0.01 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 287/ 139 and = 423 lev = 6 (0.96) mem = 0.01 MB ch = 65 box = 0 bb = 0 +ABC: cst = 0 cls = 65 lit = 65 unused = 580 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 423. Ch = 65. Total mem = 0.14 MB. Peak cut mem = 0.01 MB. +ABC: P: Del = 1749.00. Ar = 90.0. Edge = 227. Cut = 993. T = 0.00 sec +ABC: P: Del = 1749.00. Ar = 88.0. Edge = 228. Cut = 993. T = 0.00 sec +ABC: P: Del = 1749.00. Ar = 88.0. Edge = 228. Cut = 1074. T = 0.00 sec +ABC: F: Del = 1749.00. Ar = 88.0. Edge = 228. Cut = 988. T = 0.00 sec +ABC: A: Del = 1749.00. Ar = 88.0. Edge = 228. Cut = 999. T = 0.00 sec +ABC: A: Del = 1749.00. Ar = 88.0. Edge = 228. Cut = 999. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: Timing manager is given but there is no GIA of boxes. +ABC: Error: Abc_FrameUpdateGia(): Transformation has failed. +ABC: + &ps -l +ABC: /input : i/o = 287/ 139 and = 228 lev = 6 (0.96) mem = 0.01 MB box = 0 bb = 0 +ABC: Mapping (K=7) : lut = 74 edge = 228 lev = 3 (0.48) mem = 0.00 MB +ABC: LUT = 74 : 2=5 6.8 % 3=64 86.5 % 4=3 4.1 % 5=0 0.0 % 6=0 0.0 % 7=2 2.7 % Ave = 3.08 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.01 sec +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +2.47.12.6. Executing AIGER frontend. + +Removed 319 unused cells and 671 unused wires. + +2.47.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 74 +ABC RESULTS: input signals: 8 +ABC RESULTS: output signals: 5 + +Removing temp directory. + +2.47.13. Executing TECHMAP pass (map to technology primitives). + +2.47.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +2.47.13.2. Continuing TECHMAP pass. +No more expansions possible. + +Removed 64 unused cells and 976 unused wires. + +2.48. Executing TECHMAP pass (map to technology primitives). + +2.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +2.48.2. Continuing TECHMAP pass. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. +Using template $paramod$9b75b992f20cd900c37cf6bf55004e096e50f153$lut for cells of type $lut. +Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673$lut for cells of type $lut. +Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut. +Using template $paramod$5eae2dbc9c4e3a8910b7bdd34d688ce915a90667$lut for cells of type $lut. +Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. +No more expansions possible. + + +2.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in weight_buffer. + Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) +Removed 0 unused cells and 98 unused wires. + +2.50. Executing AUTONAME pass. +Renamed 407 objects in module weight_buffer. + + +2.51. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `weight_buffer'. Setting top module to weight_buffer. + +2.51.1. Analyzing design hierarchy.. +Top module: \weight_buffer + +2.51.2. Analyzing design hierarchy.. +Top module: \weight_buffer +Removed 0 unused modules. + +2.52. Printing statistics. + +=== weight_buffer === + + +----------Local Count, excluding submodules. + | + 172 wires + 499 wire bits + 172 public wires + 499 public wire bits + 6 ports + 148 port bits + 2 cells + 2 DP16KD + 241 submodules + 6 L6MUX21 + 88 LUT4 + 8 PFUMX + 139 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + 2 weight_buffer + + +----------Count including submodules. + | + 172 wires + 499 wire bits + 172 public wires + 499 public wire bits + 6 ports + 148 port bits + - memories + - memory bits + - processes + 2 cells + 2 DP16KD + 241 submodules + 6 L6MUX21 + 88 LUT4 + 8 PFUMX + 139 TRELLIS_FF + +2.53. Executing CHECK pass (checking for obvious problems). +Checking module weight_buffer... +Found and reported 0 problems. + +2.54. Executing JSON backend. + +End of script. Logfile hash: bf6d270351, time: 0.32s, user: 0.29s, system: 0.01s, MEM: 30.56 MB peak +Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) +Time spent: 54% 20x read_verilog (0 sec), 22% 11x techmap (0 sec), ... diff --git a/hardware/v2/synthesis/weight_buffer_d64/top.json b/hardware/v2/synthesis/weight_buffer_d64/top.json new file mode 100644 index 0000000..4891e11 --- /dev/null +++ b/hardware/v2/synthesis/weight_buffer_d64/top.json @@ -0,0 +1,28712 @@ +{ + "creator": "Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)", + "modules": { + "$__ABC9_DELAY": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000011", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.1-7.10" + }, + "parameter_default_values": { + "DELAY": "00000000000000000000000000000000" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + "$specify$1061": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000000000000", + "T_FALL_MIN": "00000000000000000000000000000000", + "T_FALL_TYP": "00000000000000000000000000000000", + "T_RISE_MAX": "00000000000000000000000000000000", + "T_RISE_MIN": "00000000000000000000000000000000", + "T_RISE_TYP": "00000000000000000000000000000000" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:5.5-5.22" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 3 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + } + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.29-2.30" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.39-2.40" + } + } + } + }, + "$__ABC9_SCC_BREAKER": { + "attributes": { + "dynports": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:9.1-11.10" + }, + "parameter_default_values": { + "WIDTH": "00000000000000000000000000000000" + }, + "ports": { + "I": { + "direction": "input", + "offset": -1, + "upto": 1, + "bits": [ 2, 3 ] + }, + "O": { + "direction": "output", + "offset": -1, + "upto": 1, + "bits": [ 4, 5 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2, 3 ], + "offset": -1, + "upto": 1, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:9.47-9.48" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4, 5 ], + "offset": -1, + "upto": 1, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:9.69-9.70" + } + } + } + }, + "$__DFF_N__$abc9_flop": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000010", + "blackbox": "00000000000000000000000000000001", + "abc9_flop": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.1-20.10" + }, + "ports": { + "C": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "input", + "bits": [ 4 ] + }, + "n1": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "C": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.36-14.37" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.39-14.40" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.42-14.43" + } + }, + "n1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.52-14.54" + } + } + } + }, + "$__DFF_P__$abc9_flop": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "abc9_flop": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.1-29.10" + }, + "ports": { + "C": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "input", + "bits": [ 4 ] + }, + "n1": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "C": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.36-23.37" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.39-23.40" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.42-23.43" + } + }, + "n1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.52-23.54" + } + } + } + }, + "\\$__ABC9_LUT5": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_lut": "00000000000000000000000000000010", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.1-30.10" + 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"DONTCARE", + "D_BITCLK_FROM_ND_EN": "DONTCARE", + "D_BITCLK_LOCAL_EN": "DONTCARE", + "D_BITCLK_ND_EN": "DONTCARE", + "D_BUS8BIT_SEL": "DONTCARE", + "D_CDR_LOL_SET": "DONTCARE", + "D_CMUSETBIASI": "DONTCARE", + "D_CMUSETI4CPP": "DONTCARE", + "D_CMUSETI4CPZ": "DONTCARE", + "D_CMUSETI4VCO": "DONTCARE", + "D_CMUSETICP4P": "DONTCARE", + "D_CMUSETICP4Z": "DONTCARE", + "D_CMUSETINITVCT": "DONTCARE", + "D_CMUSETISCL4VCO": "DONTCARE", + "D_CMUSETP1GM": "DONTCARE", + "D_CMUSETP2AGM": "DONTCARE", + "D_CMUSETZGM": "DONTCARE", + "D_DCO_CALIB_TIME_SEL": "DONTCARE", + "D_HIGH_MARK": "DONTCARE", + "D_IB_PWDNB": "DONTCARE", + "D_ISETLOS": "DONTCARE", + "D_LOW_MARK": "DONTCARE", + "D_MACROPDB": "DONTCARE", + "D_PD_ISET": "DONTCARE", + "D_PLL_LOL_SET": "DONTCARE", + "D_REFCK_MODE": "DONTCARE", + "D_REQ_ISET": "DONTCARE", + "D_RG_EN": "DONTCARE", + "D_RG_SET": "DONTCARE", + "D_SETICONST_AUX": "DONTCARE", + "D_SETICONST_CH": "DONTCARE", + "D_SETIRPOLY_AUX": "DONTCARE", + "D_SETIRPOLY_CH": "DONTCARE", + "D_SETPLLRC": "DONTCARE", + "D_SYNC_LOCAL_EN": "DONTCARE", + "D_SYNC_ND_EN": "DONTCARE", + "D_TXPLL_PWDNB": "DONTCARE", + "D_TX_MAX_RATE": "DONTCARE", + "D_TX_VCO_CK_DIV": "DONTCARE", + "D_XGE_MODE": "DONTCARE" + }, + "ports": { + "CH0_HDINP": { + "direction": "input", + "bits": [ 2 ] + }, + "CH1_HDINP": { + "direction": "input", + "bits": [ 3 ] + }, + "CH0_HDINN": { + "direction": "input", + "bits": [ 4 ] + }, + "CH1_HDINN": { + "direction": "input", + "bits": [ 5 ] + }, + "D_TXBIT_CLKP_FROM_ND": { + "direction": "input", + "bits": [ 6 ] + }, + "D_TXBIT_CLKN_FROM_ND": { + "direction": "input", + "bits": [ 7 ] + }, + "D_SYNC_ND": { + "direction": "input", + "bits": [ 8 ] + }, + "D_TXPLL_LOL_FROM_ND": { + "direction": "input", + "bits": [ 9 ] + }, + "CH0_RX_REFCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "CH1_RX_REFCLK": { + "direction": "input", + "bits": [ 11 ] + }, + "CH0_FF_RXI_CLK": { + "direction": "input", + "bits": [ 12 ] + }, + "CH1_FF_RXI_CLK": { + "direction": "input", + "bits": [ 13 ] + }, + "CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 86 ] + }, + "CH1_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 87 ] + }, + "CH0_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 88 ] + }, + "CH1_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 89 ] + }, + "CH0_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 90 ] + }, + "CH1_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 91 ] + }, + "CH0_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 92 ] + }, + "CH1_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 93 ] + }, + "CH0_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 94 ] + }, + "CH1_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 95 ] + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 96 ] + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 97 ] + }, + "CH0_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 98 ] + }, + "CH1_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 99 ] + }, + "CH0_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 100 ] + }, + "CH1_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 101 ] + }, + "CH0_FFC_RRST": { + "direction": "input", + "bits": [ 102 ] + }, + "CH1_FFC_RRST": { + "direction": "input", + "bits": [ 103 ] + }, + "CH0_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 104 ] + }, + "CH1_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 105 ] + }, + "CH0_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 106 ] + }, + "CH1_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 107 ] + }, + "CH0_LDR_CORE2TX": { + "direction": "input", + "bits": [ 108 ] + }, + "CH1_LDR_CORE2TX": { + "direction": "input", + "bits": [ 109 ] + }, + "D_SCIWDATA0": { + "direction": "input", + "bits": [ 110 ] + }, + "D_SCIWDATA1": { + "direction": "input", + "bits": [ 111 ] + }, + "D_SCIWDATA2": { + "direction": "input", + "bits": [ 112 ] + }, + "D_SCIWDATA3": { + "direction": "input", + "bits": [ 113 ] + }, + "D_SCIWDATA4": { + "direction": "input", + "bits": [ 114 ] + }, + "D_SCIWDATA5": { + "direction": "input", + "bits": [ 115 ] + }, + "D_SCIWDATA6": { + "direction": "input", + "bits": [ 116 ] + }, + "D_SCIWDATA7": { + "direction": "input", + "bits": [ 117 ] + }, + "D_SCIADDR0": { + "direction": "input", + "bits": [ 118 ] + }, + "D_SCIADDR1": { + "direction": "input", + "bits": [ 119 ] + }, + "D_SCIADDR2": { + "direction": "input", + "bits": [ 120 ] + }, + "D_SCIADDR3": { + "direction": "input", + "bits": [ 121 ] + }, + "D_SCIADDR4": { + "direction": "input", + "bits": [ 122 ] + }, + "D_SCIADDR5": { + "direction": "input", + "bits": [ 123 ] + }, + "D_SCIENAUX": { + "direction": "input", + "bits": [ 124 ] + }, + "D_SCISELAUX": { + "direction": "input", + "bits": [ 125 ] + }, + "CH0_SCIEN": { + "direction": "input", + "bits": [ 126 ] + }, + "CH1_SCIEN": { + "direction": "input", + "bits": [ 127 ] + }, + "CH0_SCISEL": { + "direction": "input", + "bits": [ 128 ] + }, + "CH1_SCISEL": { + "direction": "input", + "bits": [ 129 ] + }, + "D_SCIRD": { + "direction": "input", + "bits": [ 130 ] + }, + "D_SCIWSTN": { + "direction": "input", + "bits": [ 131 ] + }, + "D_CYAWSTN": { + "direction": "input", + "bits": [ 132 ] + }, + "D_FFC_SYNC_TOGGLE": { + "direction": "input", + "bits": [ 133 ] + }, + "D_FFC_DUAL_RST": { + "direction": "input", + "bits": [ 134 ] + }, + "D_FFC_MACRO_RST": { + "direction": "input", + "bits": [ 135 ] + }, + "D_FFC_MACROPDB": { + "direction": "input", + "bits": [ 136 ] + }, + "D_FFC_TRST": { + "direction": "input", + "bits": [ 137 ] + }, + "CH0_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 138 ] + }, + "CH1_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 139 ] + }, + "D_SCAN_ENABLE": { + "direction": "input", + "bits": [ 140 ] + }, + "D_SCAN_IN_0": { + "direction": "input", + "bits": [ 141 ] + }, + "D_SCAN_IN_1": { + "direction": "input", + "bits": [ 142 ] + }, + "D_SCAN_IN_2": { + "direction": "input", + "bits": [ 143 ] + }, + "D_SCAN_IN_3": { + "direction": "input", + "bits": [ 144 ] + }, + "D_SCAN_IN_4": { + "direction": "input", + "bits": [ 145 ] + }, + "D_SCAN_IN_5": { + "direction": "input", + "bits": [ 146 ] + }, + "D_SCAN_IN_6": { + "direction": "input", + "bits": [ 147 ] + }, + "D_SCAN_IN_7": { + "direction": "input", + "bits": [ 148 ] + }, + "D_SCAN_MODE": { + "direction": "input", + "bits": [ 149 ] + }, + "D_SCAN_RESET": { + "direction": "input", + "bits": [ 150 ] + }, + "D_CIN0": { + "direction": "input", + "bits": [ 151 ] + }, + "D_CIN1": { + "direction": "input", + "bits": [ 152 ] + }, + "D_CIN2": { + "direction": "input", + "bits": [ 153 ] + }, + "D_CIN3": { + "direction": "input", + "bits": [ 154 ] + }, + "D_CIN4": { + "direction": "input", + "bits": [ 155 ] + }, + "D_CIN5": { + "direction": "input", + "bits": [ 156 ] + }, + "D_CIN6": { + "direction": "input", + "bits": [ 157 ] + }, + "D_CIN7": { + "direction": "input", + "bits": [ 158 ] + }, + "D_CIN8": { + "direction": "input", + "bits": [ 159 ] + }, + "D_CIN9": { + "direction": "input", + "bits": [ 160 ] + }, + "D_CIN10": { + "direction": "input", + "bits": [ 161 ] + }, + "D_CIN11": { + "direction": "input", + "bits": [ 162 ] + }, + "CH0_HDOUTP": { + "direction": "output", + "bits": [ 163 ] + }, + "CH1_HDOUTP": { + "direction": "output", + "bits": [ 164 ] + }, + "CH0_HDOUTN": { + "direction": "output", + "bits": [ 165 ] + }, + "CH1_HDOUTN": { + "direction": "output", + "bits": [ 166 ] + }, + "D_TXBIT_CLKP_TO_ND": { + "direction": "output", + "bits": [ 167 ] + }, + "D_TXBIT_CLKN_TO_ND": { + "direction": "output", + "bits": [ 168 ] + }, + "D_SYNC_PULSE2ND": { + "direction": "output", + "bits": [ 169 ] + }, + "D_TXPLL_LOL_TO_ND": { + "direction": "output", + "bits": [ 170 ] + }, + "CH0_FF_RX_F_CLK": { + "direction": "output", + "bits": [ 171 ] + }, + "CH1_FF_RX_F_CLK": { + "direction": "output", + "bits": [ 172 ] + }, + "CH0_FF_RX_H_CLK": { + "direction": "output", + "bits": [ 173 ] + }, + "CH1_FF_RX_H_CLK": { + "direction": "output", + "bits": [ 174 ] + }, + "CH0_FF_TX_F_CLK": { + "direction": "output", + "bits": [ 175 ] + }, + "CH1_FF_TX_F_CLK": { + "direction": "output", + "bits": [ 176 ] + }, + "CH0_FF_TX_H_CLK": { + "direction": "output", + "bits": [ 177 ] + }, + "CH1_FF_TX_H_CLK": { + "direction": "output", + "bits": [ 178 ] + }, + "CH0_FF_RX_PCLK": { + "direction": "output", + "bits": [ 179 ] + }, + "CH1_FF_RX_PCLK": { + "direction": "output", + "bits": [ 180 ] + }, + "CH0_FF_TX_PCLK": { + "direction": "output", + "bits": [ 181 ] + }, + "CH1_FF_TX_PCLK": { + "direction": "output", + "bits": [ 182 ] + }, + "CH0_FF_RX_D_0": { + "direction": "output", + "bits": [ 183 ] + }, + "CH1_FF_RX_D_0": { + "direction": "output", + "bits": [ 184 ] + }, + "CH0_FF_RX_D_1": { + "direction": "output", + "bits": [ 185 ] + }, + "CH1_FF_RX_D_1": { + "direction": "output", + "bits": [ 186 ] + }, + "CH0_FF_RX_D_2": { + "direction": "output", + "bits": [ 187 ] + }, + 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"00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOA15": { + "hide_name": 0, + "bits": [ 343, 308, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOA16": { + "hide_name": 0, + "bits": [ 344, 309, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOA17": { + "hide_name": 0, + "bits": [ 310, 345, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOA2": { + "hide_name": 0, + "bits": [ 347, 311, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOA3": { + "hide_name": 0, + "bits": [ 312, 348, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOA4": { + "hide_name": 0, + "bits": [ 313, 349, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOA5": { + "hide_name": 0, + "bits": [ 314, 350, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOA6": { + "hide_name": 0, + "bits": [ 315, 351, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOA7": { + "hide_name": 0, + "bits": [ 352, 316, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOA8": { + "hide_name": 0, + "bits": [ 317, 353, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOA9": { + "hide_name": 0, + "bits": [ 318, 354, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB0": { + "hide_name": 0, + "bits": [ 319, 355, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB1": { + "hide_name": 0, + "bits": [ 320, 356, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB17": { + "hide_name": 0, + "bits": [ 301, 302, 311, 312, 313, 314, 315, 316, 317, 318, 303, 304, 305, 306, 307, 308, 309, 310, 319, 320, 329, 330, 331, 332, 333, 334, 335, 336, 321, 322, 323, 324, 325, 326, 327, 328 ], + "attributes": { + "unused_bits": "28 29 30 31 32 33 34 35" + } + }, + "mem.0.1_DOB2": { + "hide_name": 0, + "bits": [ 329, 357, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB3": { + "hide_name": 0, + "bits": [ 330, 358, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB4": { + "hide_name": 0, + "bits": [ 331, 359, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB5": { + "hide_name": 0, + "bits": [ 332, 360, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB6": { + "hide_name": 0, + "bits": [ 361, 333, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB7": { + "hide_name": 0, + "bits": [ 334, 362, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB8": { + "hide_name": 0, + "bits": [ 363, 335, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "mem.0.1_DOB9": { + "hide_name": 0, + "bits": [ 336, 364, 237 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "rd_addr": { + "hide_name": 0, + "bits": [ 74, 75, 76, 77, 78, 79 ], + "attributes": { + "src": "hardware/v2/rtl/weight_buffer.v:33.48-33.55" + } + }, + "rd_data": { + "hide_name": 0, + "bits": [ 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143 ], + "signed": 1, + "attributes": { + "src": "hardware/v2/rtl/weight_buffer.v:34.48-34.55" + } + }, + "wr_addr": { + "hide_name": 0, + "bits": [ 4, 5, 6, 7, 8, 9 ], + "attributes": { + "src": "hardware/v2/rtl/weight_buffer.v:30.48-30.55" + } + }, + "wr_addr_TRELLIS_FF_DI_Q": { + "hide_name": 0, + "bits": [ 77, 76, 75, 149, 148, 147 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "wr_data": { + "hide_name": 0, + "bits": [ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73 ], + "signed": 1, + "attributes": { + "src": "hardware/v2/rtl/weight_buffer.v:31.48-31.55" + } + }, + "wr_en": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "hardware/v2/rtl/weight_buffer.v:29.48-29.53" + } + }, + "wr_en_TRELLIS_FF_DI_Q": { + "hide_name": 0, + "bits": [ 79, 78, 145, 150, 144 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + } + } + } + } +} diff --git a/hardware/v2/synthesis/weight_buffer_d64/yosys.log b/hardware/v2/synthesis/weight_buffer_d64/yosys.log new file mode 100644 index 0000000..61d434e --- /dev/null +++ b/hardware/v2/synthesis/weight_buffer_d64/yosys.log @@ -0,0 +1,1158 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) + +-- Running command ` + read_verilog hardware/v2/rtl/weight_buffer.v + chparam -set DEPTH 64 weight_buffer + synth_ecp5 -json hardware/v2/synthesis/weight_buffer_d64/top.json -top weight_buffer +' -- + +1. Executing Verilog-2005 frontend: hardware/v2/rtl/weight_buffer.v +Parsing Verilog input from `hardware/v2/rtl/weight_buffer.v' to AST representation. +Generating RTLIL representation for module `\weight_buffer'. +Successfully finished Verilog frontend. +Parameter \DEPTH = 64 + +2. Executing AST frontend in derive mode using pre-parsed AST for module `\weight_buffer'. +Parameter \DEPTH = 64 +Generating RTLIL representation for module `$paramod\weight_buffer\DEPTH=s32'00000000000000000000000001000000'. + +3. Executing SYNTH_LATTICE pass. + +3.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +3.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +3.3. Executing HIERARCHY pass (managing design hierarchy). + +3.3.1. Analyzing design hierarchy.. +Top module: \weight_buffer + +3.3.2. Analyzing design hierarchy.. +Top module: \weight_buffer +Removed 0 unused modules. + +3.4. Executing PROC pass (convert processes to netlists). + +3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/weight_buffer.v:39$12 in module weight_buffer. +Removed a total of 0 dead cases. + +3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 4 assignments to connections. + +3.4.4. Executing PROC_INIT pass (extract init attributes). + +3.4.5. Executing PROC_ARST pass (detect async resets in processes). + +3.4.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$12'. + 1/3: $1$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$18 + 2/3: $1$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_DATA[63:0]$17 + 3/3: $1$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_ADDR[5:0]$16 +Creating decoders for process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:44$19'. + +3.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +3.4.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\weight_buffer.$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_ADDR' using process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$12'. + created $dff cell `$procdff$255' with positive edge clock. +Creating register for signal `\weight_buffer.$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_DATA' using process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$12'. + created $dff cell `$procdff$256' with positive edge clock. +Creating register for signal `\weight_buffer.$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN' using process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$12'. + created $dff cell `$procdff$257' with positive edge clock. +Creating register for signal `\weight_buffer.\rd_data' using process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:44$19'. + created $dff cell `$procdff$258' with positive edge clock. + +3.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$12'. +Removing empty process `weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$12'. +Removing empty process `weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:44$19'. +Cleaned up 1 empty switch. + +3.4.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.5. Executing CHECK pass (checking for obvious problems). +Checking module weight_buffer... +Found and reported 0 problems. + +3.6. Executing FLATTEN pass (flatten design). + +3.7. Executing TRIBUF pass. + +3.8. Executing DEMINOUT pass (demote inout ports to input or output). + +3.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. +Removed 3 unused cells and 13 unused wires. + + +3.11. Executing CHECK pass (checking for obvious problems). +Checking module weight_buffer... +Found and reported 0 problems. + +3.12. Executing OPT pass (performing simple optimizations). + +3.12.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.12.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \weight_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \weight_buffer. + Consolidated identical input bits for $mux cell $procmux$247: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] + New connections: $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [63:1] = { $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$11_EN[63:0]$15 [0] } + Optimizing cells in module \weight_buffer. +Performed a total of 1 changes. + +3.12.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.12.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +3.12.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.12.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \weight_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \weight_buffer. +Performed a total of 0 changes. + +3.12.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.12.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +3.12.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.12.16. Finished fast OPT passes. (There is nothing left to do.) + +3.13. Executing FSM pass (extract and optimize FSM). + +3.13.1. Executing FSM_DETECT pass (finding FSMs in design). + +3.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +3.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +3.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +3.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +3.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +3.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +3.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +3.14. Executing OPT pass (performing simple optimizations). + +3.14.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.14.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \weight_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \weight_buffer. +Performed a total of 0 changes. + +3.14.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.14.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +3.14.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.14.9. Finished fast OPT passes. (There is nothing left to do.) + +3.15. Executing WREDUCE pass (reducing word size of cells). + +3.16. Executing PEEPOPT pass (run peephole optimizers). + +3.17. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +3.18. Executing SHARE pass (SAT-based resource sharing). + +3.19. Executing TECHMAP pass (map to technology primitives). + +3.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +3.19.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.20. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +3.22. Executing TECHMAP pass (map to technology primitives). + +3.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +3.22.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.23. Executing TECHMAP pass (map to technology primitives). + +3.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +3.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.24. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module weight_buffer: + created 0 $alu and 0 $macc cells. + +3.25. Executing OPT pass (performing simple optimizations). + +3.25.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.25.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \weight_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \weight_buffer. +Performed a total of 0 changes. + +3.25.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 6 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.25.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +3.25.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.25.9. Finished fast OPT passes. (There is nothing left to do.) + +3.26. Executing MEMORY pass. + +3.26.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +3.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +3.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing weight_buffer.mem write port 0. + +3.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +3.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\mem'[0] in module `\weight_buffer': merging output FF to cell. + Write port 0: non-transparent. + +3.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. +Removed 1 unused cells and 65 unused wires. + + +3.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +3.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +3.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +3.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +3.27. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +3.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). +mapping memory weight_buffer.mem via $__PDPW16KD_ + + +3.29. Executing TECHMAP pass (map to technology primitives). + +3.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +3.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +3.29.3. Continuing TECHMAP pass. +Using template $paramod$02d10cc8049219b734b94ed56325542341e7b150$__PDPW16KD_ for cells of type $__PDPW16KD_. +No more expansions possible. + + +3.30. Executing OPT pass (performing simple optimizations). + +3.30.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + + +3.30.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 10 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.30.3. Executing OPT_DFF pass (perform DFF optimizations). +Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$333 ($dffe) from module weight_buffer. + +3.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. +Removed 0 unused cells and 30 unused wires. + + +3.30.5. Rerunning OPT passes. (Removed registers in this run.) + +3.30.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.30.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 10 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.30.8. Executing OPT_DFF pass (perform DFF optimizations). + +3.30.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +3.30.10. Finished fast OPT passes. + +3.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +3.32. Executing OPT pass (performing simple optimizations). + +3.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 10 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \weight_buffer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \weight_buffer. +Performed a total of 0 changes. + +3.32.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 10 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.32.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +3.32.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.32.9. Finished fast OPT passes. (There is nothing left to do.) + +3.33. Executing TECHMAP pass (map to technology primitives). + +3.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +3.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +3.33.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $eq. +No more expansions possible. + + +3.34. Executing OPT pass (performing simple optimizations). + +3.34.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.34.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 215 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.34.3. Executing OPT_DFF pass (perform DFF optimizations). + +3.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. +Removed 0 unused cells and 1 unused wires. + + +3.34.5. Finished fast OPT passes. + +3.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. + +3.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +3.37. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\weight_buffer'. +Computing hashes of 215 cells of `\weight_buffer'. +Finding duplicate cells in `\weight_buffer'. +Removed a total of 0 cells. + +3.38. Executing TECHMAP pass (map to technology primitives). + +3.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +3.38.2. Continuing TECHMAP pass. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +No more expansions possible. + + +3.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module weight_buffer. + +3.40. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +3.41. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in weight_buffer. + +3.42. Executing ATTRMVCP pass (move or copy attributes). + +3.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \weight_buffer.. +Removed 0 unused cells and 544 unused wires. + + +3.44. Executing CHECK pass (checking for obvious problems). +Checking module weight_buffer... +Found and reported 0 problems. + +3.45. Executing TECHMAP pass (map to technology primitives). + +3.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +3.45.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.46. Executing ABC9 pass. + +3.46.1. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.2. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module weight_buffer. +Found 0 SCCs. + +3.46.4. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.5. Executing TECHMAP pass (map to technology primitives). + +3.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +3.46.5.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.46.6. Executing OPT pass (performing simple optimizations). + +3.46.6.1. Executing OPT_EXPR pass (perform const folding). + +3.46.6.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +3.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +3.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +3.46.6.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +3.46.6.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +3.46.6.8. Executing OPT_EXPR pass (perform const folding). + +3.46.6.9. Finished fast OPT passes. (There is nothing left to do.) + +3.46.7. Executing TECHMAP pass (map to technology primitives). + +3.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +3.46.7.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3.46.9. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.10. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +3.46.12. Executing AIGMAP pass (map logic to AIG). +Module weight_buffer: replaced 75 cells with 510 new cells, skipped 140 cells. + replaced 3 cell types: + 64 $_MUX_ + 5 $_OR_ + 6 $_XOR_ + not replaced 4 cell types: + 1 $_AND_ + 1 $_NOT_ + 136 TRELLIS_FF + 2 DP16KD + +3.46.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.12.2. Executing ABC9_OPS pass (helper functions for ABC9). + +3.46.12.3. Executing XAIGER backend. + +Extracted 216 AND gates and 792 wires from module `weight_buffer' to a netlist network with 278 inputs and 136 outputs. + +3.46.12.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +3.46.12.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 278/ 136 and = 216 lev = 6 (0.99) mem = 0.01 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 278/ 136 and = 433 lev = 5 (0.98) mem = 0.01 MB ch = 67 box = 0 bb = 0 +ABC: cst = 0 cls = 66 lit = 67 unused = 578 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 433. Ch = 66. Total mem = 0.14 MB. Peak cut mem = 0.01 MB. +ABC: P: Del = 1366.00. Ar = 79.0. Edge = 212. Cut = 1204. T = 0.00 sec +ABC: P: Del = 1366.00. Ar = 79.0. Edge = 212. Cut = 1198. T = 0.00 sec +ABC: P: Del = 1366.00. Ar = 79.0. Edge = 212. Cut = 1310. T = 0.00 sec +ABC: F: Del = 1359.00. Ar = 73.0. Edge = 213. Cut = 1206. T = 0.00 sec +ABC: A: Del = 1359.00. Ar = 73.0. Edge = 213. Cut = 1159. T = 0.00 sec +ABC: A: Del = 1359.00. Ar = 73.0. Edge = 213. Cut = 1159. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: Timing manager is given but there is no GIA of boxes. +ABC: Error: Abc_FrameUpdateGia(): Transformation has failed. +ABC: + &ps -l +ABC: /input : i/o = 278/ 136 and = 216 lev = 5 (0.98) mem = 0.01 MB box = 0 bb = 0 +ABC: Mapping (K=6) : lut = 69 edge = 213 lev = 2 (0.49) mem = 0.00 MB +ABC: LUT = 69 : 2=1 1.4 % 3=64 92.8 % 4=2 2.9 % 5=1 1.4 % 6=1 1.4 % Ave = 3.09 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.01 sec +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +3.46.12.6. Executing AIGER frontend. + +Removed 302 unused cells and 645 unused wires. + +3.46.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 69 +ABC RESULTS: input signals: 8 +ABC RESULTS: output signals: 5 + +Removing temp directory. + +3.46.13. Executing TECHMAP pass (map to technology primitives). + +3.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +3.46.13.2. Continuing TECHMAP pass. +No more expansions possible. + +Removed 64 unused cells and 933 unused wires. + +3.47. Executing TECHMAP pass (map to technology primitives). + +3.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +3.47.2. Continuing TECHMAP pass. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut. +Using template $paramod$bdd0743498c1b082701359850a99d6fbd624c0dd$lut for cells of type $lut. +Using template $paramod$9485b1f3e4381a5bb2f1460aeaacbe063409dde1$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. +Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. +No more expansions possible. + + +3.48. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in weight_buffer. + Optimizing lut $abc$2087$lut$aiger2086$290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$2087$lut$aiger2086$290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$2087$lut$aiger2086$296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) +Removed 0 unused cells and 84 unused wires. + +3.49. Executing AUTONAME pass. +Renamed 355 objects in module weight_buffer. + + +3.50. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `weight_buffer'. Setting top module to weight_buffer. + +3.50.1. Analyzing design hierarchy.. +Top module: \weight_buffer + +3.50.2. Analyzing design hierarchy.. +Top module: \weight_buffer +Removed 0 unused modules. + +3.51. Printing statistics. + +=== weight_buffer === + + +----------Local Count, excluding submodules. + | + 148 wires + 460 wire bits + 148 public wires + 460 public wire bits + 6 ports + 142 port bits + 2 cells + 2 DP16KD + 213 submodules + 1 L6MUX21 + 73 LUT4 + 3 PFUMX + 136 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + 2 weight_buffer + + +----------Count including submodules. + | + 148 wires + 460 wire bits + 148 public wires + 460 public wire bits + 6 ports + 142 port bits + - memories + - memory bits + - processes + 2 cells + 2 DP16KD + 213 submodules + 1 L6MUX21 + 73 LUT4 + 3 PFUMX + 136 TRELLIS_FF + +3.52. Executing CHECK pass (checking for obvious problems). +Checking module weight_buffer... +Found and reported 0 problems. + +3.53. Executing JSON backend. + +End of script. Logfile hash: e8f98d9974, time: 0.31s, user: 0.28s, system: 0.01s, MEM: 29.55 MB peak +Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) +Time spent: 54% 20x read_verilog (0 sec), 23% 11x techmap (0 sec), ...