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feat(v2): M3 activation/weight/result buffers, real BRAM mapping

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Implements M3: three parametric dual-port buffers for the §12
data-plane (Input/Weight/Result), reusing the proven BRAM-inference
idiom from the frozen hardware/v1/rtl/act_buffer.v (synchronous write,
synchronous REGISTERED read, no reset on the read register -- keeps
Yosys off the LUT-RAM path).

Verified with Verilator: 10/10 tests pass (write-then-read
correctness, extreme INT8 round-tripping, weight_buffer's full 64-bit
tile width round-tripping, undisturbed re-reads).

Real synthesis at two depths per module (6 configs total): 0 CHECK
problems, every configuration correctly infers DP16KD (never
LUT-RAM). Non-obvious real finding: weight_buffer's BRAM cost is
driven by its P_IN*DATA_WIDTH tile width, not its DEPTH -- an 8x depth
reduction (512->64) left DP16KD usage unchanged at 2, while
activation_buffer/result_buffer (byte-wide) scale as naively expected
(2->1). All default-depth configs PASS at 80MHz with large margin
(287-367 MHz) via real nextpnr-ecp5 place&route.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 14:19:11 +02:00
co-authored by Claude Sonnet 5
parent 3026dcd997
commit 5f0d7f101c
29 changed files with 178330 additions and 2 deletions
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hardware/v2/logs/development.log
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@@ -88,3 +88,25 @@ errors: ERR-0005 (artefatto di sintesi da pin-count, non un bug RTL --
decision: vedi decisions.log DEC-0005.
next_action: M3 -- activation_buffer.v / weight_buffer.v /
result_buffer.v (profondita' parametrica, valutare BRAM mapping).
[2026-09-05T15:15:00Z] commit=3026dcd session=v2-M3-buffers
module: hardware/v2/rtl/activation_buffer.v, weight_buffer.v,
result_buffer.v
action: implementato M3 -- tre buffer paramentrici (profondita'
parametrica) che inferiscono DP16KD reale, riusando l'idioma gia'
validato in hardware/v1/rtl/act_buffer.v (porta A scrittura sync,
porta B lettura sync REGISTRATA, nessun reset sulla porta di lettura
per restare fuori dal percorso LUT-RAM).
reason: roadmap M3.
result: 10/10 test PASS (Verilator). Sintesi reale a 2 profondita'
ciascuno: 0 problemi CHECK, DP16KD reale confermato in tutte le 6
configurazioni (mai LUT-RAM). Scoperta reale non assunta: il costo
BRAM di weight_buffer e' determinato dalla LARGHEZZA (P_IN*DATA_
WIDTH=64 bit), non dalla profondita' -- 512->64 di profondita' non
ha ridotto il conteggio DP16KD (resta 2). Place&route reale sui
default: tutti PASS a 80MHz con ampio margine (287-367 MHz).
errors: nessuno.
decision: vedi benchmark.log -- il dimensionamento di weight_buffer
andra' guidato da P_IN, non solo da DEPTH, quando si arrivera' a
M4/M9.
next_action: M4 -- memory_manager.v + prefetch_engine.v.