feat(v2): M5 Neural Director, first-free job scheduling

Implements M5: neural_director.v dispatches job descriptors to
whichever of N_SLOTS (memory_manager, neural_processor) pairs is
currently free (first-free scheduling per §9's initial policy), with
a parametric-depth ready-queue FIFO for jobs arriving faster than
slots can absorb them.

Scope for this milestone (see decisions.log DEC-0007): a reduced
4-state FSM (DIR_IDLE/SCAN_READY/ALLOCATE/ERROR) rather than §9's full
8-state baseline -- dependency tracking, the waiting queue, and
wake-up are §10's explicit responsibility (Dependency Manager, M6, not
yet built), and slot-completion detection runs as an always-active
per-slot tracker rather than a dedicated FSM state, for the same
reason DEC-0002 already gave for the Neural Processor's own FSM
(gating concurrent per-unit progress behind one shared state kills
throughput).

Verified with Verilator (N_SLOTS=2, each slot backed by its own
independent behavioral memory rather than sharing V1's real PSRAM --
M4 already proved that path for one slot; this milestone's own concern
is scheduling across multiple slots): 4/4 tests pass -- 3 jobs
submitted to 2 slots (first two dispatch immediately, third correctly
queues until a slot frees), and a deliberate burst that forces the
ready queue to genuinely fill and recover.

Real synthesis: 0 CHECK problems, 382 LUT4/366 FF/4 CCU2C/0 DSP. Real
place&route (via a synthesis-only timing harness, same TRELLIS_IO
pin-budget reason as M2/M4): Fmax 250.50 MHz, PASS at 80MHz.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/docs/ROADMAP.md

@@ -27,7 +27,10 @@ reali, non solo scritto).
       job PASS) con vero neural_processor + vera catena PSRAM V1.
       3 bug RTL trovati/risolti (`logs/errors.log` ERR-0006). Fmax
       165.86 MHz.
-- [ ] **M5 — Neural Director** (`neural_director.v`), scheduling first-free.
+- [x] **M5 — Neural Director** (`neural_director.v`), scheduling
+      first-free. 4/4 test PASS (dispatch + coda + backpressure reale
+      su N_SLOTS=2). FSM ridotta a 4 stati, dependency rimandata a M6
+      (`logs/decisions.log` DEC-0007). Fmax 250.50 MHz.
 - [ ] **M6 — Dependency Manager** (`dependency_manager.v`), ready/waiting
       queue, dependency counters, wake-up, producer tracking.
 - [ ] **M7 — Dataflow Core** (`dataflow_core.v`), integrazione completa.