From 2e4cedc7618ac8f2bfeeec0c6886e2694db608a7 Mon Sep 17 00:00:00 2001 From: Michele Bigi Date: Sat, 5 Sep 2026 14:46:32 +0200 Subject: [PATCH] feat(v2): M5 Neural Director, first-free job scheduling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implements M5: neural_director.v dispatches job descriptors to whichever of N_SLOTS (memory_manager, neural_processor) pairs is currently free (first-free scheduling per §9's initial policy), with a parametric-depth ready-queue FIFO for jobs arriving faster than slots can absorb them. Scope for this milestone (see decisions.log DEC-0007): a reduced 4-state FSM (DIR_IDLE/SCAN_READY/ALLOCATE/ERROR) rather than §9's full 8-state baseline -- dependency tracking, the waiting queue, and wake-up are §10's explicit responsibility (Dependency Manager, M6, not yet built), and slot-completion detection runs as an always-active per-slot tracker rather than a dedicated FSM state, for the same reason DEC-0002 already gave for the Neural Processor's own FSM (gating concurrent per-unit progress behind one shared state kills throughput). Verified with Verilator (N_SLOTS=2, each slot backed by its own independent behavioral memory rather than sharing V1's real PSRAM -- M4 already proved that path for one slot; this milestone's own concern is scheduling across multiple slots): 4/4 tests pass -- 3 jobs submitted to 2 slots (first two dispatch immediately, third correctly queues until a slot frees), and a deliberate burst that forces the ready queue to genuinely fill and recover. Real synthesis: 0 CHECK problems, 382 LUT4/366 FF/4 CCU2C/0 DSP. Real place&route (via a synthesis-only timing harness, same TRELLIS_IO pin-budget reason as M2/M4): Fmax 250.50 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v --- hardware/v2/docs/ROADMAP.md | 5 +- hardware/v2/logs/benchmark.log | 7 + hardware/v2/logs/decisions.log | 70 + hardware/v2/logs/development.log | 22 + hardware/v2/logs/experiments.log | 48 + hardware/v2/logs/simulation.log | 6 + hardware/v2/logs/synthesis.log | 3 + hardware/v2/logs/timing.log | 5 + hardware/v2/rtl/neural_director.v | 220 + hardware/v2/sim/tb_neural_director.v | 322 + .../v2/synthesis/harness_neural_director.v | 66 + .../harness_neural_director/nextpnr.log | 192 + .../harness_neural_director/top.config | 4194 ++ .../harness_neural_director/top.json | 29126 ++++++++++ .../harness_neural_director/yosys.log | 2132 + .../synthesis/neural_director_n4/nextpnr.log | 56 + .../v2/synthesis/neural_director_n4/top.json | 44359 ++++++++++++++++ .../v2/synthesis/neural_director_n4/yosys.log | 1978 + 18 files changed, 82810 insertions(+), 1 deletion(-) create mode 100644 hardware/v2/rtl/neural_director.v create mode 100644 hardware/v2/sim/tb_neural_director.v create mode 100644 hardware/v2/synthesis/harness_neural_director.v create mode 100644 hardware/v2/synthesis/harness_neural_director/nextpnr.log create mode 100644 hardware/v2/synthesis/harness_neural_director/top.config create mode 100644 hardware/v2/synthesis/harness_neural_director/top.json create mode 100644 hardware/v2/synthesis/harness_neural_director/yosys.log create mode 100644 hardware/v2/synthesis/neural_director_n4/nextpnr.log create mode 100644 hardware/v2/synthesis/neural_director_n4/top.json create mode 100644 hardware/v2/synthesis/neural_director_n4/yosys.log diff --git a/hardware/v2/docs/ROADMAP.md b/hardware/v2/docs/ROADMAP.md index f1fc0a2..e30ffb0 100644 --- a/hardware/v2/docs/ROADMAP.md +++ b/hardware/v2/docs/ROADMAP.md @@ -27,7 +27,10 @@ reali, non solo scritto). job PASS) con vero neural_processor + vera catena PSRAM V1. 3 bug RTL trovati/risolti (`logs/errors.log` ERR-0006). Fmax 165.86 MHz. -- [ ] **M5 — Neural Director** (`neural_director.v`), scheduling first-free. +- [x] **M5 — Neural Director** (`neural_director.v`), scheduling + first-free. 4/4 test PASS (dispatch + coda + backpressure reale + su N_SLOTS=2). FSM ridotta a 4 stati, dependency rimandata a M6 + (`logs/decisions.log` DEC-0007). Fmax 250.50 MHz. - [ ] **M6 — Dependency Manager** (`dependency_manager.v`), ready/waiting queue, dependency counters, wake-up, producer tracking. - [ ] **M7 — Dataflow Core** (`dataflow_core.v`), integrazione completa. diff --git a/hardware/v2/logs/benchmark.log b/hardware/v2/logs/benchmark.log index b827ebc..13d1bc3 100644 --- a/hardware/v2/logs/benchmark.log +++ b/hardware/v2/logs/benchmark.log @@ -74,3 +74,10 @@ dominated by psram_model.v's real ~70ns TAA access latency, not by memory_manager's own control overhead (its bank-swap turnaround is documented as a fixed +1 cycle/tile in decisions.log DEC-0006, a small fraction of the ~140-cycle PSRAM-dominated total). + +[2026-09-05] M5 Neural Director (standalone resource count; Fmax via +timing harness -- see errors.log ERR-0005) + +| Module | Fmax (POST-P&R) | LUT | FF | DSP | CCU2C | +|------------------|------------------|-----|-----|-----|-------| +| neural_director (N_SLOTS=4) | 250.50 MHz | 382 | 366 | 0 | 4 | diff --git a/hardware/v2/logs/decisions.log b/hardware/v2/logs/decisions.log index 2c5d0ec..950cac8 100644 --- a/hardware/v2/logs/decisions.log +++ b/hardware/v2/logs/decisions.log @@ -319,3 +319,73 @@ rather than optimized blindly now. STATUS: ACCEPTED + +--- + +DEC-0007 + +DATE: 2026-09-05 + +DECISION: +neural_director.v (M5) implements a reduced FSM (DIR_IDLE, +DIR_SCAN_READY, DIR_ALLOCATE, DIR_ERROR) instead of §9's full 8-state +baseline list (which also includes DIR_WAIT_DEPENDENCY, DIR_MONITOR, +DIR_COMPLETE, DIR_WAKEUP). Dependency tracking/waiting/wake-up are +entirely deferred to the Dependency Manager (M6, not yet built); slot +completion detection (§9's "rilevamento dei completamenti", +DIR_MONITOR's job) is handled by an always-active per-slot busy +tracker running independently of whatever state the allocate/scan +loop happens to be in, not a dedicated state the loop must visit. + +WHY: +§10 explicitly assigns dependency counters/ready-vs-waiting +tracking/wake-up/producer-tracking to the Dependency Manager, not the +Director -- building DIR_WAIT_DEPENDENCY/DIR_WAKEUP now, before M6 +exists, would mean inventing a dependency model here that M6 would +then have to either reuse or replace, backwards from the roadmap's own +milestone order. For DIR_MONITOR: gating "did any slot just finish" +detection behind a specific FSM state would force the SAME state to be +revisited every cycle for every one of N_SLOTS independently-running +jobs, which is exactly the throughput-killing pattern DEC-0002 already +rejected for the Neural Processor's own FSM -- the same reasoning +applies one level up here. + +EVIDENCE: +hardware/v2/sim/tb_neural_director.v -- 4/4 tests pass with 2 slots +running genuinely concurrent, independently-timed jobs (a 3rd job +correctly queued until whichever slot freed first, and a +deliberately-slow 2-job burst used to force real ready-queue +backpressure) -- confirms slot-completion detection and first-free +allocation both work without a dedicated FSM state gating either. + +Separately: this milestone's testbench gives each (memory_manager, +neural_processor) slot its OWN independent behavioral byte memory +(sim_byte_mem, not the real V1 PSRAM chain) rather than sharing one +PSRAM port across N_SLOTS. M4 (EXP-0005) already proved the real PSRAM +path end-to-end for ONE slot; M5's own concern is scheduling/dispatch +across MULTIPLE slots, which this isolates. Multiple slots genuinely +sharing one physical PSRAM port is a backend-arbitration problem +already explicitly deferred (DEC-0006), not solved here either. + +ALTERNATIVES: +1. Implement the literal 8-state FSM now, with DIR_WAIT_DEPENDENCY/ + DIR_WAKEUP as real states that simply never get exercised until + M6 wires something into them. Rejected: dead states with no real + behavior are not simpler or safer than documenting the deferral + explicitly, and risk baking in an ad-hoc dependency model that + conflicts with M6's actual design once built. +2. Share one real PSRAM backend across N_SLOTS now, forcing the + arbiter-design question into M5. Rejected: out of this milestone's + scope (§9 is about scheduling, not memory arbitration) and would + duplicate work once M6/M8 need a real answer to backend sharing + anyway. + +RESULT: +neural_director.v as implemented: 4-state FSM, always-active slot-busy +tracking, ready-queue backpressure via a plain parametric-depth +circular FIFO. First-free scheduling only (§9's initial policy); +round-robin/least-loaded/etc are explicitly deferred to a later, +experimentally-driven milestone per §9's own text. + +STATUS: +ACCEPTED diff --git a/hardware/v2/logs/development.log b/hardware/v2/logs/development.log index 56d4cbc..89729b4 100644 --- a/hardware/v2/logs/development.log +++ b/hardware/v2/logs/development.log @@ -137,3 +137,25 @@ errors: vedi errors.log ERR-0005 (ricorrenza), ERR-0006 (3 bug nuovi). decision: vedi decisions.log DEC-0006 (motore di prefetch singolo + registro pendente, nessun arbitro backend ancora necessario). next_action: M5 -- neural_director.v, scheduling first-free. + +[2026-09-05T17:00:00Z] commit=175f697 session=v2-M5-neural-director +module: hardware/v2/rtl/neural_director.v +action: implementato M5 -- Neural Director, scheduling first-free + (§9) su N_SLOTS coppie (memory_manager, neural_processor). FSM + ridotta a 4 stati (DIR_IDLE/SCAN_READY/ALLOCATE/ERROR) -- dependency + tracking/wake-up rimandati al Dependency Manager (M6, non ancora + costruito), rilevamento completamenti gestito da un tracker + sempre-attivo per-slot (non uno stato dedicato da rivisitare). +reason: roadmap M5. +result: 4/4 test PASS (N_SLOTS=2) -- dispatch first-free confermato, + coda pronta con backpressure reale confermata (riempimento e + recupero), 3 job su 2 slot con il terzo correttamente in coda fino + a liberazione di uno slot. 2 bug di testbench trovati e risolti + (non RTL): DEPTH di sim_byte_mem troppo piccolo per il range di + indirizzi usato, e una condizione di attesa che si fermava al primo + job completato invece che a tutti e tre. Sintesi reale: 0 problemi, + 382 LUT4/366 FF/4 CCU2C/0 DSP. Fmax reale (via harness): 250.50 MHz. +errors: nessun bug RTL, solo 2 bug di testbench (vedi experiments.log + EXP-0006). +decision: vedi decisions.log DEC-0007. +next_action: M6 -- dependency_manager.v. diff --git a/hardware/v2/logs/experiments.log b/hardware/v2/logs/experiments.log index 74f8c57..e3b864e 100644 --- a/hardware/v2/logs/experiments.log +++ b/hardware/v2/logs/experiments.log @@ -274,3 +274,51 @@ decision: see decisions.log DEC-0006 (single prefetch engine + pending next_action: M5 -- neural_director.v (first-free scheduling), wiring job dispatch to potentially multiple (memory_manager, neural_ processor) pairs instead of the single hardcoded pair tested here. + +EXP-0006 +timestamp: 2026-09-05T17:00:00Z +git_commit: 175f697 (+ uncommitted M5 work) +session: v2-M5-neural-director +module: hardware/v2/rtl/neural_director.v +configuration: N_SLOTS=2 (sim), N_SLOTS=4 (synth default), + QUEUE_DEPTH=4 (sim), ADDR_WIDTH=23 +action: M5 -- first-free job scheduler dispatching to N_SLOTS + (memory_manager, neural_processor) pairs, with a parametric-depth + ready queue. +command (sim, Verilator): verilator --binary --timing -j 0 -Wno-fatal + --top-module tb -o /tmp/vtb_dir hardware/v2/rtl/neural_processor.v + hardware/v2/rtl/prefetch_engine.v hardware/v2/rtl/memory_manager.v + hardware/v2/rtl/neural_director.v hardware/v2/sim/tb_neural_director.v + && /tmp/vtb_dir +command (synth): yosys -p "synth_ecp5 -json .../top.json -top + neural_director" hardware/v2/rtl/neural_director.v (standalone, real + resource counts); harness_neural_director.v (see errors.log + ERR-0005 pattern) for real P&R Fmax. +result: + SIMULATED (N_SLOTS=2, tb_neural_director.v): 4/4 tests PASS -- + 3 jobs submitted to 2 slots (first two dispatch immediately, + first-free; third correctly WAITS in the ready queue until a slot + frees, then auto-dispatches), each result independently verified; + a deliberate 2-long-job burst forces the ready queue to genuinely + fill (job_in_ready correctly deasserts after exactly QUEUE_DEPTH + queued jobs while both slots are kept busy) and recover once + slots/queue drain. + SYNTHESIZED (standalone, N_SLOTS=4): 0 CHECK problems, 382 LUT4, + 366 TRELLIS_FF, 4 CCU2C, 0 DSP. + POST-P&R (via harness, real Fmax): 250.50 MHz, PASS at 80MHz with + large margin. +errors: two real testbench bugs found and fixed during bring-up (not + RTL bugs): (1) sim_byte_mem's DEPTH parameter (1024) was smaller + than the test's own address range (up to 0x703=1795), an + out-of-bounds array access silently returning garbage; (2) the + initial completion-wait loop exited as soon as ANY ONE of three + jobs' result bytes changed, not all three -- fixed by counting + job_out_done pulses instead of polling result memory directly. +decision: see decisions.log DEC-0007 (reduced 4-state FSM; dependency + handling deferred to M6; per-slot independent behavioral memory + instead of shared real PSRAM, deferred to when backend arbitration + is actually needed). +next_action: M6 -- dependency_manager.v (ready/waiting queue, + dependency counters, wake-up, producer tracking) -- the first + milestone where job READINESS itself, not just free-slot dispatch, + becomes the Director's actual gating condition. diff --git a/hardware/v2/logs/simulation.log b/hardware/v2/logs/simulation.log index bb2d71b..5ea99cb 100644 --- a/hardware/v2/logs/simulation.log +++ b/hardware/v2/logs/simulation.log @@ -48,3 +48,9 @@ bit-exact result: PSRAM-read-back result byte matches hand-computed RTL under test) cycles: 446 (3 tiles), 166 (1 tile), 728 (5 tiles) -- real PSRAM latency dominates, not memory_manager's own control overhead + +[2026-09-05] EXP-0006 -- hardware/v2/sim/tb_neural_director.v +test: 4 cases (3-jobs-2-slots first-free dispatch + queueing, + backpressure fill/recover) +simulator: Verilator 5.050 (--binary --timing) +PASS/FAIL: 4/4 PASS diff --git a/hardware/v2/logs/synthesis.log b/hardware/v2/logs/synthesis.log index 9cb7d75..28af93e 100644 --- a/hardware/v2/logs/synthesis.log +++ b/hardware/v2/logs/synthesis.log @@ -40,3 +40,6 @@ CHECK: 0 problems, all 6 configs correctly infer DP16KD (no LUT-RAM [2026-09-05] EXP-0005 -- memory_manager + prefetch_engine (standalone) LUT4=851 TRELLIS_FF=789 CCU2C=108 MULT18X18D=0 (expected, no multiplication in this module). CHECK: 0 problems. + +[2026-09-05] EXP-0006 -- neural_director (N_SLOTS=4, standalone) +LUT4=382 TRELLIS_FF=366 CCU2C=4 DSP=0. CHECK: 0 problems. diff --git a/hardware/v2/logs/timing.log b/hardware/v2/logs/timing.log index 4f7717a..8c9ef60 100644 --- a/hardware/v2/logs/timing.log +++ b/hardware/v2/logs/timing.log @@ -44,3 +44,8 @@ harness_memory_manager.v, see errors.log ERR-0005 for why a harness was needed), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained Fmax: 165.86 MHz -- PASS at 80MHz (real place&route measurement) + +[2026-09-05] EXP-0006 -- neural_director (via harness_neural_director.v, +see errors.log ERR-0005 for why), real nextpnr-ecp5 --45k --package +CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained +Fmax: 250.50 MHz -- PASS at 80MHz (real place&route measurement) diff --git a/hardware/v2/rtl/neural_director.v b/hardware/v2/rtl/neural_director.v new file mode 100644 index 0000000..050dbd2 --- /dev/null +++ b/hardware/v2/rtl/neural_director.v @@ -0,0 +1,220 @@ +`timescale 1ns/1ps + +// ================================================================ +// FPGA-Neural V2 -- Neural Director (M5, docs/v2-description.md §9) +// +// Dispatches job descriptors, arriving via a simple valid/ready +// producer interface, to whichever of N_SLOTS (memory_manager, M4) +// instances is currently free -- first-free scheduling (§9's initial +// policy; round-robin/least-loaded/etc are explicitly deferred to a +// later, experimentally-driven milestone, not this one). +// +// Each "slot" is one memory_manager's own job_start/x_base/w_base/ +// n_tiles/result_addr/job_done interface (M4) -- the Director does +// not touch a Neural Processor directly, matching §34's division of +// labor ("Il Director gestisce WHAT deve essere eseguito... Il +// Memory Manager gestisce COME rendere disponibili i dati"). +// +// Scope of THIS milestone (see hardware/v2/logs/decisions.log +// DEC-0007 for the full rationale): jobs are assumed already READY +// (no unresolved dependencies) -- dependency tracking, the waiting +// queue, and wake-up are explicitly the Dependency Manager's job +// (§10, M6, not yet built). §9's baseline FSM states +// DIR_WAIT_DEPENDENCY/DIR_COMPLETE/DIR_WAKEUP are therefore not +// separate states here; DIR_MONITOR's job (detecting a slot's +// completion) is handled by an always-active per-slot busy tracker, +// not a state the main allocate/scan loop must visit -- the same +// "don't gate concurrent per-unit progress behind a single shared +// FSM state" principle already applied to the Neural Processor's own +// FSM (DEC-0002). +// ================================================================ + +module neural_director #( + parameter ADDR_WIDTH = 23, + parameter N_SLOTS = 4, + parameter QUEUE_DEPTH = 8 +)( + input wire clk, + input wire rst, + + // ---- job submission (producer interface, e.g. a host or a + // future Dependency Manager, M6) ---- + input wire job_in_valid, + output wire job_in_ready, + input wire [ADDR_WIDTH-1:0] job_in_x_base, + input wire [ADDR_WIDTH-1:0] job_in_w_base, + input wire [15:0] job_in_n_tiles, + input wire [ADDR_WIDTH-1:0] job_in_result_addr, + input wire [15:0] job_in_node_id, + + // ---- per-slot memory_manager job control (arrayed, §9) ---- + output reg [N_SLOTS-1:0] slot_job_start, + output reg [ADDR_WIDTH*N_SLOTS-1:0] slot_x_base, + output reg [ADDR_WIDTH*N_SLOTS-1:0] slot_w_base, + output reg [16*N_SLOTS-1:0] slot_n_tiles, + output reg [ADDR_WIDTH*N_SLOTS-1:0] slot_result_addr, + input wire [N_SLOTS-1:0] slot_job_done, + + // ---- completion notification (§9 "rilevamento dei completamenti") ---- + output reg job_out_done, // one-cycle pulse + output reg [$clog2(N_SLOTS)-1:0] job_out_slot, + + output reg [3:0] dir_state, + output reg dir_error +); + + localparam DIR_IDLE = 4'd0; + localparam DIR_SCAN_READY = 4'd1; + localparam DIR_ALLOCATE = 4'd2; + localparam DIR_ERROR = 4'd3; + + // ---- ready queue: a plain circular FIFO of job descriptors. + // Depth is parametric (§9 implies no fixed size); pushing and + // popping are independent of the allocate FSM below so a new job + // can be accepted the same cycle an old one is dispatched. ---- + localparam Q_ADDR_WIDTH = $clog2(QUEUE_DEPTH); + + reg [ADDR_WIDTH-1:0] q_x_base [0:QUEUE_DEPTH-1]; + reg [ADDR_WIDTH-1:0] q_w_base [0:QUEUE_DEPTH-1]; + reg [15:0] q_n_tiles [0:QUEUE_DEPTH-1]; + reg [ADDR_WIDTH-1:0] q_result_addr [0:QUEUE_DEPTH-1]; + reg [15:0] q_node_id [0:QUEUE_DEPTH-1]; + + reg [Q_ADDR_WIDTH-1:0] q_head, q_tail; + reg [Q_ADDR_WIDTH:0] q_count; // one extra bit: 0..QUEUE_DEPTH inclusive + + wire q_empty = (q_count == 0); + wire q_full = (q_count == QUEUE_DEPTH[Q_ADDR_WIDTH:0]); + + assign job_in_ready = !q_full; + + // ---- per-slot busy tracking: always-active, independent of the + // main allocate/scan FSM state (see file header). ---- + reg [N_SLOTS-1:0] slot_busy; + + wire [N_SLOTS-1:0] slot_free = ~slot_busy; + wire any_slot_free = |slot_free; + + // first-free slot index (priority encoder, lowest index wins -- + // "first-free", per §9's initial policy, not load-balanced) + reg [$clog2(N_SLOTS)-1:0] free_slot_idx; + integer fi; + always @(*) begin + free_slot_idx = {$clog2(N_SLOTS){1'b0}}; + for (fi = N_SLOTS-1; fi >= 0; fi = fi - 1) begin + if (slot_free[fi]) free_slot_idx = fi[$clog2(N_SLOTS)-1:0]; + end + end + + // Priority-encoded lowest-indexed slot reporting job_done this + // cycle (combinational, so it reflects THIS cycle's slot_job_done + // bus directly -- a register-based "already reported one" flag + // would read its own pre-edge value and not actually suppress a + // second same-cycle match, see file header/DEC-0007). + reg [$clog2(N_SLOTS)-1:0] done_slot_idx; + integer di; + always @(*) begin + done_slot_idx = {$clog2(N_SLOTS){1'b0}}; + for (di = N_SLOTS-1; di >= 0; di = di - 1) begin + if (slot_job_done[di]) done_slot_idx = di[$clog2(N_SLOTS)-1:0]; + end + end + + always @(posedge clk) begin + if (rst) begin + dir_state <= DIR_IDLE; + dir_error <= 1'b0; + q_head <= {Q_ADDR_WIDTH{1'b0}}; + q_tail <= {Q_ADDR_WIDTH{1'b0}}; + q_count <= {(Q_ADDR_WIDTH+1){1'b0}}; + slot_busy <= {N_SLOTS{1'b0}}; + slot_job_start <= {N_SLOTS{1'b0}}; + slot_x_base <= {(ADDR_WIDTH*N_SLOTS){1'b0}}; + slot_w_base <= {(ADDR_WIDTH*N_SLOTS){1'b0}}; + slot_n_tiles <= {(16*N_SLOTS){1'b0}}; + slot_result_addr <= {(ADDR_WIDTH*N_SLOTS){1'b0}}; + job_out_done <= 1'b0; + job_out_slot <= {$clog2(N_SLOTS){1'b0}}; + end else begin + slot_job_start <= {N_SLOTS{1'b0}}; + job_out_done <= 1'b0; + + // ---- Accept a new job into the ready queue (independent + // of the allocate FSM's own state -- a producer must + // never be blocked just because the FSM is mid-allocate + // this cycle). ---- + if (job_in_valid && job_in_ready) begin + q_x_base[q_tail] <= job_in_x_base; + q_w_base[q_tail] <= job_in_w_base; + q_n_tiles[q_tail] <= job_in_n_tiles; + q_result_addr[q_tail] <= job_in_result_addr; + q_node_id[q_tail] <= job_in_node_id; + q_tail <= (q_tail == QUEUE_DEPTH[Q_ADDR_WIDTH-1:0]-1'b1) ? {Q_ADDR_WIDTH{1'b0}} : q_tail + 1'b1; + end + + // ---- Free a slot the instant its job_done pulses, + // regardless of the allocate FSM's own state (DIR_MONITOR + // absorbed here -- see file header). Cleared with a single + // vectorized AND-NOT of the whole slot_job_done bus (not a + // per-bit for-loop of individual NBA writes) so that TWO + // slots completing on the SAME cycle both get freed --a + // per-bit loop would have each iteration's non-blocking + // write use the same pre-edge slot_busy, so only the LAST + // matching bit would actually clear ("last write wins"). + // job_out_done/job_out_slot still report at most one + // (the lowest-indexed) simultaneous completion per cycle + // -- a documented simplification (decisions.log DEC-0007), + // not a correctness issue for slot freeing itself. ---- + slot_busy <= slot_busy & ~slot_job_done; + if (|slot_job_done) begin + job_out_done <= 1'b1; + job_out_slot <= done_slot_idx; + end + + // ---- Main allocate/scan loop ---- + case (dir_state) + + DIR_IDLE: begin + dir_state <= DIR_SCAN_READY; + end + + DIR_SCAN_READY: begin + if (!q_empty && any_slot_free) begin + dir_state <= DIR_ALLOCATE; + end + end + + DIR_ALLOCATE: begin + // Dispatch the head of the queue to the first + // free slot found this cycle. + slot_job_start[free_slot_idx] <= 1'b1; + slot_x_base[free_slot_idx*ADDR_WIDTH +: ADDR_WIDTH] <= q_x_base[q_head]; + slot_w_base[free_slot_idx*ADDR_WIDTH +: ADDR_WIDTH] <= q_w_base[q_head]; + slot_n_tiles[free_slot_idx*16 +: 16] <= q_n_tiles[q_head]; + slot_result_addr[free_slot_idx*ADDR_WIDTH +: ADDR_WIDTH] <= q_result_addr[q_head]; + slot_busy[free_slot_idx] <= 1'b1; + q_head <= (q_head == QUEUE_DEPTH[Q_ADDR_WIDTH-1:0]-1'b1) ? {Q_ADDR_WIDTH{1'b0}} : q_head + 1'b1; + dir_state <= DIR_SCAN_READY; + end + + DIR_ERROR: begin + // Recoverable only via rst (§34: an error must not + // block the rest of the system). + end + + default: dir_state <= DIR_ERROR; + + endcase + + // q_count tracks push/pop independently of which branch + // above fired, so it stays correct even when a push and a + // pop happen the same cycle. + case ({job_in_valid && job_in_ready, (dir_state == DIR_SCAN_READY) && !q_empty && any_slot_free}) + 2'b10: q_count <= q_count + 1'b1; + 2'b01: q_count <= q_count - 1'b1; + default: q_count <= q_count; // 00: no change, 11: push+pop cancel out + endcase + end + end + +endmodule diff --git a/hardware/v2/sim/tb_neural_director.v b/hardware/v2/sim/tb_neural_director.v new file mode 100644 index 0000000..222140d --- /dev/null +++ b/hardware/v2/sim/tb_neural_director.v @@ -0,0 +1,322 @@ +`timescale 1ns/1ps + +// ============================================================ +// M5 testbench (docs/v2-description.md §9/§20): neural_director.v +// dispatching to N_SLOTS=2 (memory_manager + neural_processor) pairs. +// Verified with Verilator (decisions.log DEC-0004). +// +// Scope decision (decisions.log DEC-0007): each slot gets its OWN +// independent simple behavioral byte memory (sim_byte_mem below, +// fixed 2-cycle latency, matching int8_memory_access.v's req/wr/addr/ +// wdata -> rdata/ready contract exactly) instead of sharing V1's real +// PSRAM chain -- M4 already proved the real PSRAM path end-to-end +// with ONE slot (EXP-0005); M5's own concern is scheduling/dispatch +// across MULTIPLE slots, which is what this testbench isolates. +// Multiple slots genuinely sharing ONE physical PSRAM port is a +// backend-arbitration problem explicitly deferred (DEC-0006), not +// re-solved here. +// +// Coverage: +// - more jobs submitted (3) than slots exist (2): first two must +// dispatch immediately (first-free), the third must wait in the +// ready queue until a slot frees up, then dispatch automatically. +// - each job's result independently verified (own oracle). +// - ready-queue backpressure: fill the queue past N jobs beyond +// slot capacity and confirm job_in_ready deasserts, then confirm +// it drains and reasserts as slots complete. +// ============================================================ + +module sim_byte_mem #( + parameter ADDR_WIDTH = 23, + parameter DEPTH = 1024 +)( + input wire clk, + input wire rst, + input wire req, + input wire wr, + input wire [ADDR_WIDTH-1:0] addr, + input wire signed [7:0] wdata, + output reg signed [7:0] rdata, + output reg ready +); + reg signed [7:0] mem [0:DEPTH-1]; + reg [1:0] state; + reg [ADDR_WIDTH-1:0] addr_reg; + reg wr_reg; + localparam ST_IDLE = 0, ST_WAIT = 1; + always @(posedge clk) begin + if (rst) begin + state <= ST_IDLE; ready <= 1'b0; rdata <= 8'sd0; + end else begin + ready <= 1'b0; + case (state) + ST_IDLE: if (req) begin + addr_reg <= addr; wr_reg <= wr; + if (wr) mem[addr] <= wdata; + state <= ST_WAIT; + end + ST_WAIT: begin + rdata <= mem[addr_reg]; + ready <= 1'b1; + state <= ST_IDLE; + end + endcase + end + end +endmodule + +module tb; + + localparam ADDR_WIDTH = 23; + localparam DATA_WIDTH = 8; + localparam P_IN = 8; + localparam ACC_WIDTH = 32; + localparam N_SLOTS = 2; + localparam QUEUE_DEPTH = 4; + + reg clk, rst; + initial begin clk = 0; forever #5 clk = ~clk; end + + reg job_in_valid; + wire job_in_ready; + reg [ADDR_WIDTH-1:0] job_in_x_base, job_in_w_base, job_in_result_addr; + reg [15:0] job_in_n_tiles, job_in_node_id; + + wire [N_SLOTS-1:0] slot_job_start; + wire [ADDR_WIDTH*N_SLOTS-1:0] slot_x_base, slot_w_base, slot_result_addr; + wire [16*N_SLOTS-1:0] slot_n_tiles; + wire [N_SLOTS-1:0] slot_job_done; + + wire job_out_done; + wire [$clog2(N_SLOTS)-1:0] job_out_slot; + wire [3:0] dir_state; + wire dir_error; + + neural_director #( + .ADDR_WIDTH(ADDR_WIDTH), .N_SLOTS(N_SLOTS), .QUEUE_DEPTH(QUEUE_DEPTH) + ) u_dir ( + .clk(clk), .rst(rst), + .job_in_valid(job_in_valid), .job_in_ready(job_in_ready), + .job_in_x_base(job_in_x_base), .job_in_w_base(job_in_w_base), + .job_in_n_tiles(job_in_n_tiles), .job_in_result_addr(job_in_result_addr), + .job_in_node_id(job_in_node_id), + .slot_job_start(slot_job_start), .slot_x_base(slot_x_base), .slot_w_base(slot_w_base), + .slot_n_tiles(slot_n_tiles), .slot_result_addr(slot_result_addr), .slot_job_done(slot_job_done), + .job_out_done(job_out_done), .job_out_slot(job_out_slot), + .dir_state(dir_state), .dir_error(dir_error) + ); + + genvar g; + generate + for (g = 0; g < N_SLOTS; g = g + 1) begin : GEN_SLOT + + wire mm_operand_valid, mm_operand_ready; + wire signed [DATA_WIDTH*P_IN-1:0] mm_input_data, mm_weight_data; + wire mm_tile_last; + wire mm_result_valid, mm_result_ready; + wire signed [DATA_WIDTH-1:0] mm_result_data; + + wire mem_req, mem_wr; + wire [ADDR_WIDTH-1:0] mem_addr; + wire signed [7:0] mem_wdata, mem_rdata; + wire mem_ready; + + memory_manager #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ADDR_WIDTH(ADDR_WIDTH) + ) u_mm ( + .clk(clk), .rst(rst), + .job_start(slot_job_start[g]), + .x_base(slot_x_base[g*ADDR_WIDTH +: ADDR_WIDTH]), + .w_base(slot_w_base[g*ADDR_WIDTH +: ADDR_WIDTH]), + .n_tiles(slot_n_tiles[g*16 +: 16]), + .result_addr(slot_result_addr[g*ADDR_WIDTH +: ADDR_WIDTH]), + .job_done(slot_job_done[g]), + .operand_valid(mm_operand_valid), .operand_ready(mm_operand_ready), + .input_data(mm_input_data), .weight_data(mm_weight_data), .tile_last(mm_tile_last), + .result_valid(mm_result_valid), .result_ready(mm_result_ready), .result_data(mm_result_data), + .mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr), .mem_wdata(mem_wdata), + .mem_rdata(mem_rdata), .mem_ready(mem_ready) + ); + + reg job_valid_np; + wire job_ready_np; + wire result_valid_np; + wire signed [DATA_WIDTH-1:0] result_data_np; + wire [3:0] np_state; + wire np_error; + + neural_processor #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH) + ) u_np ( + .clk(clk), .rst(rst), + .job_valid(job_valid_np), .job_ready(job_ready_np), + .job_node_id(16'h0), .job_bias(8'sd0), .job_activation(2'd1), + .operand_valid(mm_operand_valid), .operand_ready(mm_operand_ready), + .input_data(mm_input_data), .weight_data(mm_weight_data), .tile_last(mm_tile_last), + .result_valid(result_valid_np), .result_ready(mm_result_ready), + .result_data(result_data_np), .result_node_id(), + .np_state(np_state), .np_error(np_error) + ); + assign mm_result_valid = result_valid_np; + assign mm_result_data = result_data_np; + + always @(posedge clk) begin + if (rst) job_valid_np <= 1'b0; + else if (slot_job_start[g]) job_valid_np <= 1'b1; + else if (job_valid_np && job_ready_np) job_valid_np <= 1'b0; + end + + sim_byte_mem #(.ADDR_WIDTH(ADDR_WIDTH), .DEPTH(4096)) u_mem ( + .clk(clk), .rst(rst), + .req(mem_req), .wr(mem_wr), .addr(mem_addr), .wdata(mem_wdata), + .rdata(mem_rdata), .ready(mem_ready) + ); + + end + endgenerate + + task automatic poke(input integer slot, input [ADDR_WIDTH-1:0] addr, input [7:0] val); + begin + case (slot) + 0: tb.GEN_SLOT[0].u_mem.mem[addr] = val; + 1: tb.GEN_SLOT[1].u_mem.mem[addr] = val; + default: ; + endcase + end + endtask + + function automatic signed [7:0] peek(input integer slot, input [ADDR_WIDTH-1:0] addr); + begin + case (slot) + 0: peek = tb.GEN_SLOT[0].u_mem.mem[addr]; + 1: peek = tb.GEN_SLOT[1].u_mem.mem[addr]; + default: peek = 8'sdx; + endcase + end + endfunction + + integer errors, tests; + + task automatic submit_job( + input [ADDR_WIDTH-1:0] xb, input [ADDR_WIDTH-1:0] wb, + input [15:0] nt, input [ADDR_WIDTH-1:0] resaddr, input [15:0] nid + ); + begin + @(posedge clk); + job_in_x_base = xb; job_in_w_base = wb; job_in_n_tiles = nt; + job_in_result_addr = resaddr; job_in_node_id = nid; + job_in_valid = 1'b1; + while (!job_in_ready) @(posedge clk); + @(posedge clk); + job_in_valid = 1'b0; + end + endtask + + integer i; + integer wd; + + initial begin + errors = 0; tests = 0; + rst = 1; job_in_valid = 0; job_in_x_base = 0; job_in_w_base = 0; + job_in_n_tiles = 0; job_in_result_addr = 0; job_in_node_id = 0; + repeat(4) @(posedge clk); + rst = 0; + @(posedge clk); + + // ---- prepare 3 independent jobs (2 slots, so job 2 must + // wait in the ready queue for a slot to free up) ---- + // Job 0 (slot 0 pre-loaded region 0x100/0x200): 8 inputs, x=2,w=3 -> acc=48 + for (i = 0; i < 8; i = i + 1) begin poke(0, 23'h100+i, 8'sd2); poke(0, 23'h200+i, 8'sd3); poke(1, 23'h100+i, 8'sd2); poke(1, 23'h200+i, 8'sd3); end + // Job 1 (either slot, region 0x300/0x400): 16 inputs, x=1,w=1 -> acc=16 + for (i = 0; i < 16; i = i + 1) begin poke(0, 23'h300+i, 8'sd1); poke(0, 23'h400+i, 8'sd1); poke(1, 23'h300+i, 8'sd1); poke(1, 23'h400+i, 8'sd1); end + // Job 2 (queued until a slot frees, region 0x500/0x600): 8 inputs, x=1,w=5 -> acc=40 + for (i = 0; i < 8; i = i + 1) begin poke(0, 23'h500+i, 8'sd1); poke(0, 23'h600+i, 8'sd5); poke(1, 23'h500+i, 8'sd1); poke(1, 23'h600+i, 8'sd5); end + + submit_job(23'h100, 23'h200, 16'd1, 23'h700, 16'd1); // -> dispatches to slot 0 (first-free) + submit_job(23'h300, 23'h400, 16'd2, 23'h701, 16'd2); // -> dispatches to slot 1 + submit_job(23'h500, 23'h600, 16'd1, 23'h702, 16'd3); // -> waits in queue + + // job_in_ready should have stayed high throughout (only 3 + // jobs, queue depth 4) -- confirmed implicitly: submit_job's + // own while-loop would have hung the testbench otherwise. + + tests = tests + 3; + wd = 0; + begin + integer completions; + completions = 0; + while (completions < 3 && wd < 3000) begin + @(posedge clk); + wd = wd + 1; + if (job_out_done) completions = completions + 1; + end + if (completions < 3) + $display("FAIL: only %0d/3 jobs completed within watchdog", completions); + end + // give the last-completing job's write a little extra margin + repeat(5) @(posedge clk); + + if (peek(0, 23'h700) !== 8'sd48) begin + $display("FAIL job0: result=%0d expected=48", peek(0,23'h700)); errors = errors + 1; + end else $display("PASS job0 (slot dispatched first-free): result=48"); + + if (peek(1, 23'h701) !== 8'sd16) begin + $display("FAIL job1: result=%0d expected=16", peek(1,23'h701)); errors = errors + 1; + end else $display("PASS job1 (slot dispatched first-free): result=16"); + + // Job 2 could have landed on either slot (whichever freed + // first) -- check both. + if (peek(0, 23'h702) !== 8'sd40 && peek(1, 23'h702) !== 8'sd40) begin + $display("FAIL job2 (queued): neither slot's result byte at 0x702 is 40 (got %0d / %0d)", peek(0,23'h702), peek(1,23'h702)); + errors = errors + 1; + end else $display("PASS job2 (queued until a slot freed): result=40"); + + // ---- backpressure: occupy both slots with LONG jobs (many + // tiles, so they stay busy for a while and won't drain the + // queue mid-burst), then push jobs faster than they can be + // consumed and confirm job_in_ready genuinely deasserts once + // the queue fills, then recovers once slots free up again. ---- + tests = tests + 1; + for (i = 0; i < 64; i = i + 1) begin poke(0, 23'h800+i, 8'sd1); poke(0, 23'h900+i, 8'sd1); poke(1, 23'h800+i, 8'sd1); poke(1, 23'h900+i, 8'sd1); end + submit_job(23'h800, 23'h900, 16'd64, 23'h704, 16'd10); // occupies slot 0/1 for a while + submit_job(23'h800, 23'h900, 16'd64, 23'h705, 16'd11); // occupies the other slot + + job_in_x_base = 23'h100; job_in_w_base = 23'h200; job_in_n_tiles = 16'd1; + job_in_result_addr = 23'h706; job_in_node_id = 16'd12; + i = 0; + while (job_in_ready && i < QUEUE_DEPTH + 2) begin + @(posedge clk); + job_in_valid = 1'b1; + @(posedge clk); + i = i + 1; + end + if (i > QUEUE_DEPTH) begin + $display("FAIL backpressure: job_in_ready never deasserted after %0d pushes (QUEUE_DEPTH=%0d) -- both slots busy, queue should have filled", i, QUEUE_DEPTH); + errors = errors + 1; + end else begin + $display("PASS backpressure: job_in_ready correctly deasserted after %0d queued jobs (QUEUE_DEPTH=%0d), both slots busy", i, QUEUE_DEPTH); + end + job_in_valid = 1'b0; + + // Drain: wait for everything (2 long jobs + whatever got + // queued) to finish, no watchdog failure, and confirm + // job_in_ready recovers once slots/queue free up. + wd = 0; + while (!job_in_ready && wd < 5000) begin @(posedge clk); wd = wd + 1; end + if (!job_in_ready) begin + $display("FAIL backpressure: job_in_ready never recovered within watchdog"); + errors = errors + 1; + end else begin + $display("PASS backpressure: job_in_ready recovered once slots/queue drained"); + end + + $display("========================================"); + if (errors == 0) + $display("ALL %0d TESTS PASSED (neural_director, first-free scheduling, N_SLOTS=%0d)", tests, N_SLOTS); + else + $display("FAILED: %0d/%0d test(s) had errors -- see messages above", errors, tests); + $display("========================================"); + $finish; + end + +endmodule diff --git a/hardware/v2/synthesis/harness_neural_director.v b/hardware/v2/synthesis/harness_neural_director.v new file mode 100644 index 0000000..66ea1ac --- /dev/null +++ b/hardware/v2/synthesis/harness_neural_director.v @@ -0,0 +1,66 @@ +// ================================================================ +// SYNTHESIS-ONLY TIMING HARNESS -- NOT a functional deliverable. +// Same rationale as harness_neural_processor_array.v / harness_ +// memory_manager.v (see errors.log ERR-0005): neural_director's +// per-slot arrayed ports (N_SLOTS=4 * 23-bit addresses x3) exceed the +// LFE5U-45F's TRELLIS_IO budget as a bare top-level module. +// ================================================================ + +module harness_neural_director #( + parameter ADDR_WIDTH = 23, + parameter N_SLOTS = 4, + parameter QUEUE_DEPTH = 8 +)( + input wire clk, + input wire rst, + input wire [7:0] seed, + output wire [7:0] checksum +); + + reg [31:0] lfsr; + always @(posedge clk) begin + if (rst) lfsr <= {24'h0, seed} | 32'h1; + else lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]}; + end + + wire job_in_valid = lfsr[0]; + wire [ADDR_WIDTH-1:0] job_in_x_base = lfsr[ADDR_WIDTH-1:0]; + wire [ADDR_WIDTH-1:0] job_in_w_base = {lfsr[3:0], lfsr[ADDR_WIDTH-5:0]}; + wire [15:0] job_in_n_tiles = lfsr[15:0]; + wire [ADDR_WIDTH-1:0] job_in_result_addr = {lfsr[7:0], lfsr[ADDR_WIDTH-9:0]}; + wire [15:0] job_in_node_id = lfsr[31:16]; + wire [N_SLOTS-1:0] slot_job_done = lfsr[N_SLOTS-1:0]; + + wire job_in_ready; + wire [N_SLOTS-1:0] slot_job_start; + wire [ADDR_WIDTH*N_SLOTS-1:0] slot_x_base, slot_w_base, slot_result_addr; + wire [16*N_SLOTS-1:0] slot_n_tiles; + wire job_out_done; + wire [$clog2(N_SLOTS)-1:0] job_out_slot; + wire [3:0] dir_state; + wire dir_error; + + neural_director #( + .ADDR_WIDTH(ADDR_WIDTH), .N_SLOTS(N_SLOTS), .QUEUE_DEPTH(QUEUE_DEPTH) + ) dut ( + .clk(clk), .rst(rst), + .job_in_valid(job_in_valid), .job_in_ready(job_in_ready), + .job_in_x_base(job_in_x_base), .job_in_w_base(job_in_w_base), + .job_in_n_tiles(job_in_n_tiles), .job_in_result_addr(job_in_result_addr), + .job_in_node_id(job_in_node_id), + .slot_job_start(slot_job_start), .slot_x_base(slot_x_base), .slot_w_base(slot_w_base), + .slot_n_tiles(slot_n_tiles), .slot_result_addr(slot_result_addr), .slot_job_done(slot_job_done), + .job_out_done(job_out_done), .job_out_slot(job_out_slot), + .dir_state(dir_state), .dir_error(dir_error) + ); + + reg [7:0] chk; + always @(posedge clk) begin + if (rst) chk <= 8'h0; + else chk <= chk ^ {7'h0, job_in_ready} ^ slot_job_start ^ slot_x_base[7:0] + ^ slot_w_base[7:0] ^ slot_result_addr[7:0] ^ slot_n_tiles[7:0] + ^ {7'h0, job_out_done} ^ {6'h0, job_out_slot} ^ dir_state ^ {7'h0, dir_error}; + end + assign checksum = chk; + +endmodule diff --git a/hardware/v2/synthesis/harness_neural_director/nextpnr.log b/hardware/v2/synthesis/harness_neural_director/nextpnr.log new file mode 100644 index 0000000..d8ef9d4 --- /dev/null +++ b/hardware/v2/synthesis/harness_neural_director/nextpnr.log @@ -0,0 +1,192 @@ + + +Info: Logic utilisation before packing: +Info: Total LUT4s: 163/43848 0% +Info: logic LUTs: 107/43848 0% +Info: carry LUTs: 8/43848 0% +Info: RAM LUTs: 32/ 5481 0% +Info: RAMW LUTs: 16/10962 0% + +Info: Total DFFs: 98/43848 0% + +Info: Packing IOs.. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 66 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0x77eb46c4 + +Info: Device utilisation: +Info: TRELLIS_IO: 18/ 245 7% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 108 0% +Info: MULT18X18D: 0/ 72 0% +Info: ALU54B: 0/ 36 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 160 0% +Info: SIOLOGIC: 0/ 85 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 10 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 98/ 43848 0% +Info: TRELLIS_COMB: 169/ 43848 0% +Info: TRELLIS_RAMW: 8/ 5481 0% + +Info: Placed 0 cells based on constraints. +Info: Creating initial analytic placement for 134 cells, random placement wirelen = 12480. +Info: at initial placer iter 0, wirelen = 1480 +Info: at initial placer iter 1, wirelen = 1128 +Info: at initial placer iter 2, wirelen = 1103 +Info: at initial placer iter 3, wirelen = 1100 +Info: Running main analytical placer, max placement attempts per cell = 10804. +Info: at iteration #1, type ALL: wirelen solved = 1119, spread = 1315, legal = 1359; time = 0.00s +Info: HeAP Placer Time: 0.02s +Info: of which solving equations: 0.01s +Info: of which spreading cells: 0.00s +Info: of which strict legalisation: 0.00s + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 12, wirelen = 1359 +Info: at iteration #5: temp = 0.000000, timing cost = 33, wirelen = 1072 +Info: at iteration #10: temp = 0.000000, timing cost = 31, wirelen = 1074 +Info: at iteration #12: temp = 0.000000, timing cost = 23, wirelen = 1051 +Info: SA placement time 0.05s + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 275.10 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.52 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.86 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 8865, 9019) |********************* +Info: [ 9019, 9173) |******************* +Info: [ 9173, 9327) |***************** +Info: [ 9327, 9481) |************** +Info: [ 9481, 9635) |*** +Info: [ 9635, 9789) |*** +Info: [ 9789, 9943) |** +Info: [ 9943, 10097) |**** +Info: [ 10097, 10251) |***** +Info: [ 10251, 10405) |***** +Info: [ 10405, 10559) |************** +Info: [ 10559, 10713) |******************************** +Info: [ 10713, 10867) |***************************************** +Info: [ 10867, 11021) |************************************ +Info: [ 11021, 11175) |**************************** +Info: [ 11175, 11329) |****************************** +Info: [ 11329, 11483) |**** +Info: [ 11483, 11637) |************ +Info: [ 11637, 11791) |*************** +Info: [ 11791, 11945) |*** +Info: Checksum: 0x23c4f63e +Info: Routing globals... +Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 887 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 1000 | 154 829 | 154 829 | 48| 0.08 0.08| +Info: 1047 | 154 875 | 0 46 | 0| 0.04 0.11| +Info: Routing complete. +Info: Router1 time 0.11s +Info: Checksum: 0x86bbec10 + +Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source dut.slot_busy_TRELLIS_FF_Q_2.Q +Info: routing 0.68 1.07 Net dut.dir_state_LUT4_D_Z[1] (27,37) -> (28,37) +Info: Sink dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0_B0_LUT4_Z.D +Info: Defined in: +Info: hardware/v2/rtl/neural_director.v:93.23-93.32 +Info: logic 0.18 1.25 Source dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0_B0_LUT4_Z.F +Info: routing 0.85 2.10 Net dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0_B0 (28,37) -> (30,38) +Info: Sink dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0$CCU2_COMB0.B +Info: logic 0.35 2.46 Source dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0$CCU2_COMB0.FCO +Info: routing 0.00 2.46 Net dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0$CCU2_FCI_INT (30,38) -> (30,38) +Info: Sink dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0$CCU2_COMB1.FCI +Info: logic 0.29 2.75 Source dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0$CCU2_COMB1.F +Info: routing 0.94 3.69 Net dut.dir_state_LUT4_D_Z[3] (30,38) -> (28,35) +Info: Sink dut.q_w_base.0.1_DO_LUT4_B_Z_LUT4_Z.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 3.87 Source dut.q_w_base.0.1_DO_LUT4_B_Z_LUT4_Z.F +Info: routing 0.12 3.99 Net dut.q_w_base.0.1_DO_LUT4_B_Z[2] (28,35) -> (28,35) +Info: Sink dut.slot_w_base_TRELLIS_FF_Q_2.DI +Info: setup 0.00 3.99 Source dut.slot_w_base_TRELLIS_FF_Q_2.DI +Info: 1.40 ns logic, 2.59 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': +Info: type curr total name +Info: source 0.00 0.00 Source rst$tr_io.O +Info: routing 2.75 2.75 Net rst$TRELLIS_IO_IN (29,0) -> (29,37) +Info: Sink dut.slot_job_start_TRELLIS_FF_Q_LSR_LUT4_Z.C +Info: Defined in: +Info: hardware/v2/synthesis/harness_neural_director.v:15.17-15.20 +Info: logic 0.18 2.93 Source dut.slot_job_start_TRELLIS_FF_Q_LSR_LUT4_Z.F +Info: routing 0.47 3.40 Net dut.slot_job_start_TRELLIS_FF_Q_LSR (29,37) -> (28,36) +Info: Sink dut.slot_job_start_TRELLIS_FF_Q_3.LSR +Info: setup 0.29 3.68 Source dut.slot_job_start_TRELLIS_FF_Q_3.LSR +Info: 0.47 ns logic, 3.22 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_5.Q +Info: routing 2.94 3.34 Net checksum[6]$TRELLIS_IO_OUT (32,39) -> (90,38) +Info: Sink checksum[6]$tr_io.I +Info: Defined in: +Info: hardware/v2/synthesis/harness_neural_director.v:57.15-57.18 +Info: 0.40 ns logic, 2.94 ns routing + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 250.50 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.68 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 3.34 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 8508, 8673) |** +Info: [ 8673, 8838) |******** +Info: [ 8838, 9003) |*********************** +Info: [ 9003, 9168) |****** +Info: [ 9168, 9333) |*********************** +Info: [ 9333, 9498) |**************** +Info: [ 9498, 9663) |* +Info: [ 9663, 9828) | +Info: [ 9828, 9993) |*** +Info: [ 9993, 10158) |* +Info: [ 10158, 10323) |******* +Info: [ 10323, 10488) |**** +Info: [ 10488, 10653) |********* +Info: [ 10653, 10818) |***************************** +Info: [ 10818, 10983) |*************************** +Info: [ 10983, 11148) |****************************************** +Info: [ 11148, 11313) |*************************************** +Info: [ 11313, 11478) |*********************************** +Info: [ 11478, 11643) |******************** +Info: [ 11643, 11808) |************* + +Info: Program finished normally. diff --git a/hardware/v2/synthesis/harness_neural_director/top.config b/hardware/v2/synthesis/harness_neural_director/top.config new file mode 100644 index 0000000..f8dd993 --- /dev/null +++ b/hardware/v2/synthesis/harness_neural_director/top.config @@ -0,0 +1,4194 @@ +.device LFE5U-45F + +.comment Part: LFE5U-45F-8CABGA381 + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R13C1:CIB_LR +arc: E3_H06E0303 JQ5 + +.tile CIB_R1C29:CIB +arc: S3_V06S0003 JQ0 + +.tile CIB_R1C31:CIB +arc: E1_H02E0501 V06N0303 +arc: S3_V06S0003 JQ0 + +.tile CIB_R1C32:CIB +arc: JA0 H02E0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C33:CIB +arc: S3_V06S0003 H06W0003 + +.tile CIB_R1C36:CIB +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R1C37:CIB +arc: E3_H06E0303 S3_V06N0303 + +.tile CIB_R1C41:CIB +arc: E1_H02E0501 S1_V02N0501 + +.tile CIB_R1C42:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C43:CIB +arc: E3_H06E0303 W3_H06E0303 +arc: JA0 W1_H02E0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C48:CIB +arc: JD7 E1_H01W0100 + +.tile CIB_R1C49:CIB +arc: H01W0100 W3_H06E0303 + +.tile CIB_R32C1:CIB_LR +arc: E3_H06E0303 JQ5 + +.tile CIB_R34C13:CIB_EBR +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R34C19:CIB_EBR +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R34C1:CIB_LR_S +arc: E3_H06E0303 JQ5 + +.tile CIB_R34C25:CIB_EBR +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R34C26:CIB_EBR +arc: N1_V02N0701 H06W0203 + +.tile CIB_R34C27:CIB_EBR +arc: S1_V02S0701 E1_H02W0701 + +.tile CIB_R34C29:CIB_EBR +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V06S0203 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 V06S0203 + +.tile CIB_R34C30:CIB_EBR +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0701 H02E0701 + +.tile CIB_R34C31:CIB_EBR +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0401 W1_H02E0401 +arc: S1_V02S0701 W1_H02E0701 + +.tile CIB_R34C32:CIB_EBR +arc: S1_V02S0101 N1_V01S0100 +arc: S3_V06S0303 N1_V01S0100 + +.tile CIB_R34C7:CIB_EBR +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R35C1:CIB_LR +arc: JA0 E1_H02W0501 +arc: JA3 E1_H02W0701 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R37C1:CIB_LR +arc: E3_H06E0303 JQ5 + +.tile CIB_R38C1:CIB_LR +arc: E3_H06E0303 JQ5 +arc: JA0 E1_H02W0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R38C89:CIB_LR +arc: JA3 V02N0501 +arc: W3_H06W0303 JF5 +enum: CIB.JB3MUX 0 + +.tile CIB_R39C89:CIB_LR +arc: N1_V02N0501 H06E0303 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0701 H06E0203 + +.tile CIB_R40C89:CIB_LR +arc: JA0 V02S0701 +arc: JA3 V00B0000 +arc: V00B0000 V02S0201 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C1:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C89:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C42:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C43:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C44:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C45:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C46:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C47:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C48:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C49:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C50:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C51:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C52:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C53:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C69:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C70:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C71:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C72:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C73:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C74:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C75:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C76:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C77:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C78:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C79:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile CIB_R70C80:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C87:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile MIB_R0C29:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C31:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C32:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C3:BANKREF0 +enum: BANK.VCCIO 3V3 + +.tile MIB_R0C40:TMID_0 +arc: G_TDCC0CLKI G_JTRQPCLKCIB1 + +.tile MIB_R0C42:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C43:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C87:BANKREF1 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C30:EBR_SPINE_UL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C40:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_VPFS0000 + +.tile MIB_R10C41:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_VPFS0000 + +.tile MIB_R12C0:PICL1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON + +.tile MIB_R13C0:PICL2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R17C0:PICL0_DQS2 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R18C0:PICL1_DQS3 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R1C29:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C31:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C32:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C42:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C43:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R32C0:PICL0 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R33C0:PICL1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON + +.tile MIB_R34C0:MIB_CIB_LR +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R35C0:PICL0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R36C0:PICL1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R37C0:PICL2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R38C0:PICL0 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R38C90:PICR0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R39C0:PICL1_DQS0 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R39C90:PICR1_DQS0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R40C90:PICR2_DQS1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R58C30:EBR_SPINE_LL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R58C40:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_VPFS0000 + +.tile MIB_R58C41:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_VPFS0000 + +.tile MIB_R71C1:BANKREF6 +enum: BANK.VCCIO 3V3 + +.tile MIB_R71C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile MIB_R71C89:BANKREF3 +enum: BANK.VCCIO 3V3 + +.tile R11C41:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R12C31:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R13C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R13C19:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R13C25:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R13C29:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R13C31:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: S3_V06S0003 N3_V06S0003 + +.tile R13C33:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R13C37:PLC2 +arc: N3_V06N0303 W3_H06E0303 + +.tile R13C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R17C41:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R18C31:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R19C29:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R19C31:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R19C33:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R23C41:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R24C31:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R25C29:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R25C31:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R25C33:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R29C41:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R30C31:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R31C29:PLC2 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 + +.tile R31C31:PLC2 +arc: S1_V02S0101 N3_V06S0103 + +.tile R31C33:PLC2 +arc: S1_V02S0101 N3_V06S0103 + +.tile R32C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R32C19:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R32C25:PLC2 +arc: S1_V02S0401 W3_H06E0203 + +.tile R32C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R33C25:PLC2 +arc: E1_H02E0401 V02S0401 + +.tile R33C26:PLC2 +arc: A0 V02N0701 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R33C27:PLC2 +arc: S1_V02S0501 H01E0101 + +.tile R33C29:PLC2 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 N1_V02S0101 + +.tile R33C30:PLC2 +arc: S3_V06S0103 E1_H01W0100 +arc: B0 V02N0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R33C31:PLC2 +arc: E1_H02E0401 V02N0401 +arc: S1_V02S0101 E1_H01W0100 +arc: B0 N1_V02S0101 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R33C32:PLC2 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0001 W3_H06E0003 +arc: B0 H02W0101 +arc: C0 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R33C33:PLC2 +arc: W1_H02W0101 N1_V02S0101 + +.tile R35C15:PLC2 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile R35C21:PLC2 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 + +.tile R35C26:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: A2 V01N0101 +arc: B2 S1_V02N0101 +arc: C2 S1_V02N0401 +arc: CLK0 G_HPBX0000 +arc: D2 N1_V02S0001 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F2 +arc: F2 F2_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: S1_V02S0201 Q2 +word: SLICEB.K0.INIT 1111111111111110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C27:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 H02E0001 +arc: H00L0100 H02W0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0701 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0701 V02S0701 +arc: A0 H00L0100 +arc: A1 V02N0701 +arc: A3 V00T0000 +arc: A4 H02E0701 +arc: A6 S1_V02N0301 +arc: B0 F3 +arc: B1 V02N0301 +arc: B3 V01N0001 +arc: B4 N1_V02S0501 +arc: B6 V01S0000 +arc: C0 V02N0401 +arc: C1 F6 +arc: C2 E1_H01W0000 +arc: C4 H02E0401 +arc: C6 V02N0201 +arc: CE1 H00R0100 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D2 Q2 +arc: D3 E1_H02W0001 +arc: D4 V00B0000 +arc: D6 H01W0000 +arc: E1_H01E0001 F2 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: V00T0000 Q0 +arc: V01S0000 Q4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEB.K0.INIT 0000111111110000 +word: SLICEA.K0.INIT 0110100110010110 +word: SLICEB.K1.INIT 1001100101100110 +word: SLICEA.K1.INIT 1001011001101001 +word: SLICED.K0.INIT 0110100110010110 +word: SLICEC.K0.INIT 0000000011110100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C28:PLC2 +arc: H00R0100 S1_V02N0701 +arc: V00T0000 S1_V02N0401 +arc: A6 W1_H02E0701 +arc: B1 Q1 +arc: B2 E1_H01W0100 +arc: B3 Q3 +arc: B4 F1 +arc: B5 S1_V02N0501 +arc: B6 H02W0301 +arc: C1 H00L0000 +arc: C2 V02N0601 +arc: C3 V02N0401 +arc: C4 V00T0100 +arc: C5 H01E0001 +arc: C6 V02N0001 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 Q2 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: E1_H01E0101 Q5 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 Q5 +arc: E1_H02E0601 Q4 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q6 +arc: S1_V02S0601 Q4 +arc: V00T0100 Q1 +arc: V01S0000 Q5 +arc: V01S0100 Q4 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEA.K1.INIT 0011110011001100 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 0000000000110010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R35C29:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 N1_V02S0301 +arc: H00R0100 H02E0501 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0301 V02N0301 +arc: A0 V02N0701 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: A4 V02N0101 +arc: A5 V02N0301 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 E1_H02W0301 +arc: B5 V00B0100 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0201 +arc: CLK1 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 E1_H02W0201 +arc: D5 S1_V02N0401 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F2 +arc: LSR0 V00T0000 +arc: LSR1 E1_H02W0501 +arc: M2 V00B0000 +arc: MUXCLK1 CLK1 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 Q2 +arc: S3_V06S0003 F3 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEC.MODE RAMW +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK + +.tile R35C30:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 V02N0401 +arc: H00R0100 S1_V02N0701 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 E1_H02W0201 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0701 +arc: A5 V02N0301 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C4 V00T0000 +arc: C5 S1_V02N0001 +arc: C6 V02N0001 +arc: CE3 H00R0100 +arc: CLK1 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H02W0201 +arc: D5 E1_H02W0001 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q6 +arc: LSR0 V00T0100 +arc: LSR1 V00B0100 +arc: MUXCLK3 CLK1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0301 F3 +arc: V00B0000 Q6 +arc: V01S0000 F0 +arc: V01S0100 F1 +arc: W1_H02W0201 F2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100110011110000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +enum: SLICEC.MODE RAMW +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R35C31:PLC2 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 H02W0101 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 H02W0501 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 V02N0301 +arc: A5 N1_V02S0101 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 E1_H02W0101 +arc: B5 H00L0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C5 N1_V02S0001 +arc: CLK1 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H00L0100 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F0 +arc: H01W0100 F1 +arc: LSR1 V00B0100 +arc: S1_V02S0001 F2 +arc: S3_V06S0003 F3 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEC.MODE RAMW +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK + +.tile R35C32:PLC2 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V01N0101 +arc: B0 H01W0100 +arc: C0 H00L0100 +arc: C2 H00L0100 +arc: CE0 S1_V02N0201 +arc: CE1 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 0011111111000000 +word: SLICEA.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000111111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R35C33:PLC2 +arc: W1_H02W0101 H01E0101 + +.tile R35C35:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R35C3:PLC2 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 + +.tile R35C41:PLC2 +arc: N3_V06N0203 W3_H06E0203 + +.tile R35C9:PLC2 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile R36C26:PLC2 +arc: E1_H02E0001 V06S0003 +arc: A0 V02N0701 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111010110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R36C27:PLC2 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0701 E1_H01W0100 +arc: A0 V02N0501 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 0101010100000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R36C28:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 W1_H02E0201 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0401 E1_H02W0101 +arc: A2 V01N0101 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: B2 V01N0001 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0701 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 E1_H01W0100 +arc: D5 V02N0601 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: S3_V06S0103 Q2 +arc: V01S0000 F2 +arc: V01S0100 F3 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEB.K0.INIT 0010000000000000 +word: SLICEC.K0.INIT 1001011001101001 +word: SLICEC.K1.INIT 0110100110010110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C29:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0100 V02S0101 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0000 H02W0401 +arc: V00T0000 H02W0201 +arc: W1_H02W0301 V01N0101 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0701 +arc: A5 S1_V02N0301 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 V02S0701 +arc: B5 H02E0101 +arc: B6 N1_V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C6 Q6 +arc: CE3 H00R0100 +arc: CLK1 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q6 +arc: LSR0 V00B0000 +arc: LSR1 H02W0301 +arc: MUXCLK3 CLK1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 F3 +arc: V01S0100 F0 +arc: W1_H02W0401 Q6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111111111111111 +enum: SLICEC.MODE RAMW +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R36C30:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 V02S0701 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02N0401 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: A6 S1_V02N0101 +arc: A7 N1_V01S0100 +arc: B0 S1_V02N0301 +arc: B1 Q1 +arc: B2 S1_V02N0101 +arc: B4 V02N0501 +arc: B6 H01E0101 +arc: B7 H02E0101 +arc: C0 H00L0000 +arc: C1 E1_H01W0000 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V00B0100 +arc: D2 N1_V01S0000 +arc: D3 V02N0201 +arc: D4 W1_H02E0201 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q4 +arc: H01W0100 Q7 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q6 +arc: N1_V02N0101 F3 +arc: N1_V02N0401 Q4 +arc: S1_V02S0301 F3 +arc: V00B0000 Q6 +arc: V01S0000 Q4 +arc: V01S0100 F3 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 F3 +arc: W1_H02W0601 Q4 +arc: W1_H02W0701 Q7 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1110111001000100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 1100110010101010 +word: SLICEC.K0.INIT 0011001111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R36C31:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 V02S0601 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 V02N0701 +arc: A1 E1_H02W0701 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 E1_H02W0701 +arc: A5 S1_V02N0301 +arc: A6 H02E0701 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 V02S0501 +arc: B5 H02W0301 +arc: B6 V00B0000 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 H02E0401 +arc: CLK1 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V02S0601 +arc: D5 H02W0001 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F2 +arc: LSR0 V00T0100 +arc: LSR1 H02E0301 +arc: MUXCLK3 CLK1 +arc: MUXLSR3 LSR0 +arc: N3_V06N0303 Q6 +arc: S1_V02S0101 F3 +arc: V00B0000 Q6 +arc: V01S0000 F1 +arc: W1_H02W0001 F0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 1001011001101001 +enum: SLICEC.MODE RAMW +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK + +.tile R36C32:PLC2 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 W3_H06E0003 +arc: V00B0000 H02E0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 V06S0003 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 N1_V01N0101 +arc: A5 N1_V02S0101 +arc: B0 E1_H02W0301 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0301 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: C0 E1_H02W0601 +arc: C1 E1_H02W0601 +arc: C2 E1_H02W0601 +arc: C3 E1_H02W0601 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: CLK1 G_HPBX0000 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 V00B0000 +arc: D5 W1_H02E0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: LSR1 W1_H02E0301 +arc: N1_V01N0101 F6 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F2 +arc: S3_V06S0103 F1 +arc: V01S0100 F6 +arc: W3_H06W0303 F6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +enum: SLICEC.MODE RAMW +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R36C33:PLC2 +arc: W1_H02W0701 H01E0101 + +.tile R36C34:PLC2 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 W3_H06E0303 + +.tile R37C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R37C19:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R37C23:PLC2 +arc: E1_H02E0701 E3_H06W0203 + +.tile R37C25:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 E1_H01W0000 + +.tile R37C26:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 V01N0001 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0100 H02W0101 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H06W0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02W0201 +arc: A2 E1_H02W0701 +arc: A3 V02N0701 +arc: A5 E1_H01W0000 +arc: A7 E1_H01W0000 +arc: B1 H02W0301 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: C0 H02W0601 +arc: C1 E1_H01W0000 +arc: C2 H02W0401 +arc: C3 H02W0601 +arc: C4 H02W0601 +arc: C5 V02N0201 +arc: C6 H02W0401 +arc: C7 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 V00B0100 +arc: D5 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00T0000 +arc: M1 H02W0001 +arc: M2 V00T0000 +arc: M3 H00L0100 +arc: M4 V00T0000 +arc: M5 H02W0001 +arc: M6 V00T0000 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 0011110011110000 +word: SLICEB.K0.INIT 1111000011010010 +word: SLICEB.K1.INIT 1111000001111000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0101101010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 0101101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R37C27:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0000 E1_H02W0401 +arc: A1 V02N0701 +arc: A3 V01N0101 +arc: A5 E1_H02W0501 +arc: A6 N1_V01N0101 +arc: B1 E1_H02W0301 +arc: B4 V02N0501 +arc: B5 V00B0100 +arc: B6 V00T0000 +arc: C1 E1_H02W0601 +arc: C2 F6 +arc: C3 E1_H01W0000 +arc: C4 E1_H01E0101 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0201 +arc: D2 S1_V02N0201 +arc: D3 V02N0001 +arc: D4 F2 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E1_H02E0501 Q5 +arc: E1_H02E0701 Q5 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 Q6 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M3 H02W0201 +arc: M6 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q6 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F6 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: V00B0100 Q5 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: V01S0000 F2 +arc: V01S0100 Q6 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q6 +arc: W1_H02W0601 Q6 +word: SLICEC.K1.INIT 0000110010101110 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEC.K0.INIT 0011111111000000 +word: SLICED.K0.INIT 0000000000000010 +word: SLICEB.K1.INIT 0000000000000101 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0110100110010110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R37C28:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: A0 F5 +arc: A1 F5 +arc: A2 H02E0701 +arc: A4 V00B0000 +arc: A5 H02E0501 +arc: A7 H02E0701 +arc: B0 E1_H01W0100 +arc: B1 Q1 +arc: B2 H00R0000 +arc: B4 N1_V01S0000 +arc: B5 H00L0000 +arc: B7 V00T0000 +arc: C0 N1_V01S0100 +arc: C1 W1_H02E0601 +arc: C2 H00L0000 +arc: C4 V02S0001 +arc: C5 V00T0100 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D4 E1_H01W0100 +arc: D5 V00B0000 +arc: D7 V00B0000 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 F7 +arc: LSR1 H02E0301 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: S1_V02S0501 F5 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 Q5 +arc: V01S0100 F2 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0010101000000000 +word: SLICEC.K0.INIT 1100111000001010 +word: SLICEA.K0.INIT 1111010011110000 +word: SLICEA.K1.INIT 0010111000001100 +word: SLICEC.K1.INIT 0000101010001010 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R37C29:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H06E0203 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 N3_V06S0203 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 V00T0000 +arc: A4 V00B0000 +arc: A6 F5 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0301 +arc: B3 Q3 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0601 +arc: C3 N1_V01S0100 +arc: C4 N1_V02S0001 +arc: C5 H02E0401 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0201 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 V02N0601 +arc: D6 S1_V02N0401 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0100 F5 +arc: H01W0000 Q2 +arc: H01W0100 F5 +arc: LSR1 V00T0100 +arc: M0 H02W0601 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F0 +arc: N1_V02N0501 F5 +arc: S1_V02S0501 F5 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 Q4 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICED.K0.INIT 1111111101010101 +word: SLICEA.K0.INIT 0110100110010110 +word: SLICEA.K1.INIT 1001011001101001 +word: SLICEC.K1.INIT 0000111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R37C30:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0301 N1_V02S0301 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0100 H02W0301 +arc: W1_H02W0001 V01N0001 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0701 +arc: A5 E1_H02W0501 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H02W0101 +arc: B5 H02W0301 +arc: C0 N1_V02S0601 +arc: C1 N1_V02S0601 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0601 +arc: C4 N1_V02S0201 +arc: C5 S1_V02N0201 +arc: C6 N1_V02S0001 +arc: C7 V01N0101 +arc: CE3 H00R0100 +arc: CLK1 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: D4 H00L0100 +arc: D5 V02N0401 +arc: D6 V01N0001 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0100 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M5 H00L0000 +arc: MUXCLK0 CLK1 +arc: MUXCLK1 CLK1 +arc: MUXCLK2 CLK1 +arc: MUXCLK3 CLK1 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: S1_V02S0101 F1 +arc: V00T0000 Q0 +arc: V01S0000 F2 +arc: V01S0100 F3 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q7 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE RAMW +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK + +.tile R37C31:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 V02S0501 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 V02S0501 +arc: A4 H02W0701 +arc: A5 H02W0501 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 V00B0100 +arc: B5 H00L0000 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 V02S0201 +arc: C5 S1_V02N0001 +arc: CLK1 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 N1_V02S0601 +arc: D5 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: LSR1 H02E0301 +arc: S1_V02S0301 F1 +arc: V01S0000 F3 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEC.MODE RAMW +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK + +.tile R37C32:PLC2 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: S1_V02S0001 H01E0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 W1_H02E0701 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1010101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C33:PLC2 +arc: H01W0000 W3_H06E0103 +arc: A0 V02N0501 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R37C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R38C11:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R38C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R38C17:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R38C19:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R38C23:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R38C25:PLC2 +arc: E1_H02E0701 W3_H06E0203 + +.tile R38C26:PLC2 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: A0 H02E0701 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R38C27:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 H02W0401 +arc: V00B0100 V02S0301 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: B1 E1_H01W0100 +arc: B2 V02S0101 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 N1_V01S0000 +arc: D2 V02S0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q1 +arc: E1_H02E0301 Q3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: M0 V00B0100 +arc: M1 V01S0100 +arc: M3 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F2 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0101101010010110 +word: SLICEB.K0.INIT 0000000000000001 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R38C28:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 V02S0501 +arc: H00L0000 H02E0201 +arc: H00L0100 H02E0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 V02S0401 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A3 H01E0001 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: C0 H00L0000 +arc: C2 H00L0000 +arc: C6 Q6 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0201 +arc: D2 H01E0101 +arc: D3 H02E0201 +arc: D6 H01W0000 +arc: E1_H01E0001 Q7 +arc: E1_H02E0301 Q3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q7 +arc: H01W0100 Q6 +arc: LSR1 V00T0000 +arc: M0 H02E0601 +arc: M1 H00R0100 +arc: M2 H02E0601 +arc: M3 H00L0100 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q6 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 Q7 +arc: N1_V02N0701 Q7 +arc: V01S0000 Q6 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 1100100101101100 +word: SLICEA.K1.INIT 0110011011001100 +word: SLICEB.K0.INIT 0011110011001100 +word: SLICEB.K1.INIT 0110011011001100 +word: SLICED.K0.INIT 1111111100001111 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C29:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0000 V02N0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0401 E1_H01W0000 +arc: A0 N1_V02S0701 +arc: A7 H02E0501 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q7 +arc: H00L0000 Q2 +arc: H01W0000 Q1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 V00B0100 +arc: M1 H00L0100 +arc: M2 H02W0601 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: V00B0100 Q5 +arc: V01S0000 Q6 +arc: V01S0100 Q6 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R38C30:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 H02E0501 +arc: N1_V02N0401 V01N0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0601 H01E0001 +arc: A4 V02S0301 +arc: A6 N1_V01S0100 +arc: B0 W1_H02E0101 +arc: C4 Q4 +arc: C6 Q6 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D4 H00L0100 +arc: D6 H01W0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F0 +arc: E1_H02E0101 F1 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F1 +arc: H01W0000 F1 +arc: LSR1 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F1 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F1 +arc: S1_V02S0401 Q4 +arc: S1_V02S0601 Q6 +arc: V01S0000 F1 +arc: V01S0100 F1 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F1 +arc: W3_H06W0103 F1 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICED.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R38C31:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0301 H02W0301 +arc: V00T0000 V02S0401 +arc: A4 N1_V01S0100 +arc: B0 N1_V02S0101 +arc: B1 W1_H02E0301 +arc: B2 V02S0101 +arc: B3 Q3 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 V02N0401 +arc: C3 H02E0601 +arc: C4 H01E0001 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D4 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V02N0401 Q4 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: V00B0000 Q4 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1100110011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R38C32:PLC2 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: V00B0100 H02E0701 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0301 W3_H06E0003 +arc: A3 E1_H01E0001 +arc: A4 V00B0000 +arc: B0 N1_V02S0101 +arc: B1 W1_H02E0301 +arc: B2 W1_H02E0101 +arc: B3 H02E0301 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C2 H00L0000 +arc: C4 H02E0601 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 N1_V02S0201 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: E1_H01E0001 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S1_V02S0401 Q4 +arc: V00B0000 Q4 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEB.K1.INIT 1010101011001100 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEC.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R38C33:PLC2 +arc: N1_V02N0501 E1_H02W0501 + +.tile R38C35:PLC2 +arc: W1_H02W0501 E3_H06W0303 + +.tile R38C3:PLC2 +arc: W1_H02W0501 E1_H02W0401 + +.tile R38C41:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R38C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R38C53:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R38C59:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R38C5:PLC2 +arc: W1_H02W0401 E3_H06W0203 + +.tile R38C65:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R38C71:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R38C77:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R38C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R38C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R39C26:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 E1_H01W0100 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 + +.tile R39C27:PLC2 +arc: H00L0100 H02W0301 +arc: H00R0100 H02W0501 +arc: V00B0000 H02W0401 +arc: A0 H00L0000 +arc: B0 H02E0301 +arc: C0 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: H01W0100 Q6 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M1 H00L0100 +arc: M3 H00R0100 +arc: M4 V00T0100 +arc: M6 N1_V01N0101 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +arc: V00B0100 Q7 +arc: V00T0100 Q3 +word: SLICEA.K0.INIT 0110100110010110 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C28:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 N1_V02S0401 +arc: H00R0100 W1_H02E0501 +arc: V00B0100 H02W0501 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 N1_V02S0401 +arc: C3 N1_V02S0601 +arc: CLK0 G_HPBX0000 +arc: D3 N1_V01S0000 +arc: F3 F3_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q6 +arc: H01W0000 Q3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q0 +arc: V00B0000 Q4 +arc: V00T0100 Q1 +arc: V01S0000 F3 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q5 +word: SLICEB.K1.INIT 1111000011111111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R39C29:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 H02W0201 +arc: H00L0100 H02W0101 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0401 H02E0401 +arc: V00B0000 H02E0401 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02W0301 +arc: A0 H00L0100 +arc: A1 H00L0000 +arc: B0 V00T0000 +arc: B1 E1_H01W0100 +arc: B3 Q3 +arc: C0 E1_H01W0000 +arc: C1 N1_V01S0100 +arc: C3 E1_H02W0401 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 E1_H02W0201 +arc: D3 V02S0001 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: LSR0 V00B0000 +arc: M0 V00T0100 +arc: M5 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0001 F0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q3 +arc: W1_H02W0501 Q5 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 0110100110010110 +word: SLICEA.K1.INIT 1001011001101001 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R39C30:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0003 N3_V06S0003 +arc: H00R0100 H02E0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 N3_V06S0103 +arc: V00B0100 H02E0701 +arc: A0 H00L0000 +arc: A2 V00T0000 +arc: B1 Q1 +arc: B2 H02E0301 +arc: B3 N1_V02S0101 +arc: C0 N1_V01S0100 +arc: C1 S1_V02N0601 +arc: C3 H00L0100 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D1 N1_V01S0000 +arc: D2 N1_V01S0000 +arc: D3 N1_V01S0000 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: V00T0000 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011001100 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R39C31:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 N1_V01S0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 V06S0203 +arc: A0 F5 +arc: A5 V00B0000 +arc: B2 N1_V02S0301 +arc: B5 H00L0000 +arc: C0 H02E0401 +arc: C2 N1_V01N0001 +arc: C5 H01E0001 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 H02E0001 +arc: D5 H02E0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: W1_H02W0201 Q2 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1001011001101001 +word: SLICEA.K0.INIT 0101101010100101 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C32:PLC2 +arc: H00L0100 V02S0101 +arc: N1_V02N0401 N1_V01S0000 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0201 V06S0103 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A4 V02S0101 +arc: A5 N1_V01S0100 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H00L0000 +arc: B5 H00L0000 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 V02S0201 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D2 N1_V01S0000 +arc: D3 V02S0001 +arc: D4 H02E0001 +arc: D5 H00L0100 +arc: E1_H01E0001 Q5 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 Q5 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M2 W1_H02E0601 +arc: M4 V00B0100 +arc: M5 V01S0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: V00B0000 F4 +arc: V01S0000 F2 +word: SLICEB.K0.INIT 0110100110010110 +word: SLICEB.K1.INIT 1001011001101001 +word: SLICEC.K0.INIT 0110100110010110 +word: SLICEC.K1.INIT 1001011001101001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R39C33:PLC2 +arc: N1_V02N0001 H06E0003 + +.tile R39C37:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R39C38:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 + +.tile R39C43:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R39C44:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 + +.tile R39C49:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R39C50:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 + +.tile R39C55:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R39C56:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 + +.tile R39C61:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R39C62:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 + +.tile R39C67:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R39C68:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 + +.tile R39C73:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R39C74:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 + +.tile R39C79:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R39C80:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 + +.tile R39C85:PLC2 +arc: E1_H01E0001 W3_H06E0003 + +.tile R39C86:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 W3_H06E0203 + +.tile R3C41:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R40C28:PLC2 +arc: N1_V02N0601 N1_V01S0000 + +.tile R41C30:PLC2 +arc: N1_V02N0601 N3_V06S0303 + +.tile R4C31:PLC2 +arc: N3_V06N0303 S1_V02N0501 + +.tile R6C31:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R7C29:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R7C31:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R7C33:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R7C37:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R9C41:PLC2 +arc: N3_V06N0303 S1_V02N0501 + +.tile TAP_R33C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R35C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile 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"DONTCARE", + "CH0_TX_GEAR_BYPASS": "DONTCARE", + "CH0_TX_GEAR_MODE": "DONTCARE", + "CH0_TX_POST_SIGN": "DONTCARE", + "CH0_TX_PRE_SIGN": "DONTCARE", + "CH0_UC_MODE": "DONTCARE", + "CH0_UDF_COMMA_A": "DONTCARE", + "CH0_UDF_COMMA_B": "DONTCARE", + "CH0_UDF_COMMA_MASK": "DONTCARE", + "CH0_WA_BYPASS": "DONTCARE", + "CH0_WA_MODE": "DONTCARE", + "CH1_AUTO_CALIB_EN": "DONTCARE", + "CH1_AUTO_FACQ_EN": "DONTCARE", + "CH1_BAND_THRESHOLD": "DONTCARE", + "CH1_CALIB_CK_MODE": "DONTCARE", + "CH1_CC_MATCH_1": "DONTCARE", + "CH1_CC_MATCH_2": "DONTCARE", + "CH1_CC_MATCH_3": "DONTCARE", + "CH1_CC_MATCH_4": "DONTCARE", + "CH1_CDR_CNT4SEL": "DONTCARE", + "CH1_CDR_CNT8SEL": "DONTCARE", + "CH1_CDR_MAX_RATE": "DONTCARE", + "CH1_CTC_BYPASS": "DONTCARE", + "CH1_DCOATDCFG": "DONTCARE", + "CH1_DCOATDDLY": "DONTCARE", + "CH1_DCOBYPSATD": "DONTCARE", + "CH1_DCOCALDIV": "DONTCARE", + "CH1_DCOCTLGI": "DONTCARE", + "CH1_DCODISBDAVOID": "DONTCARE", + "CH1_DCOFLTDAC": "DONTCARE", + "CH1_DCOFTNRG": "DONTCARE", + "CH1_DCOIOSTUNE": "DONTCARE", + "CH1_DCOITUNE": "DONTCARE", + "CH1_DCOITUNE4LSB": "DONTCARE", + "CH1_DCOIUPDNX2": "DONTCARE", + "CH1_DCONUOFLSB": "DONTCARE", + "CH1_DCOSCALEI": "DONTCARE", + "CH1_DCOSTARTVAL": "DONTCARE", + "CH1_DCOSTEP": "DONTCARE", + "CH1_DEC_BYPASS": "DONTCARE", + "CH1_ENABLE_CG_ALIGN": "DONTCARE", + "CH1_ENC_BYPASS": "DONTCARE", + "CH1_FF_RX_F_CLK_DIS": "DONTCARE", + "CH1_FF_RX_H_CLK_EN": "DONTCARE", + "CH1_FF_TX_F_CLK_DIS": "DONTCARE", + "CH1_FF_TX_H_CLK_EN": "DONTCARE", + "CH1_GE_AN_ENABLE": "DONTCARE", + "CH1_INVERT_RX": "DONTCARE", + "CH1_INVERT_TX": "DONTCARE", + "CH1_LDR_CORE2TX_SEL": "DONTCARE", + "CH1_LDR_RX2CORE_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_TRIM": "DONTCARE", + "CH1_LSM_DISABLE": "DONTCARE", + "CH1_MATCH_2_ENABLE": "DONTCARE", + "CH1_MATCH_4_ENABLE": "DONTCARE", + "CH1_MIN_IPG_CNT": "DONTCARE", + "CH1_PCIE_EI_EN": "DONTCARE", + "CH1_PCIE_MODE": "DONTCARE", + "CH1_PCS_DET_TIME_SEL": "DONTCARE", + "CH1_PDEN_SEL": "DONTCARE", + "CH1_PRBS_ENABLE": "DONTCARE", + "CH1_PRBS_LOCK": "DONTCARE", + "CH1_PRBS_SELECTION": "DONTCARE", + "CH1_PROTOCOL": "DONTCARE", + "CH1_RATE_MODE_RX": "DONTCARE", + "CH1_RATE_MODE_TX": "DONTCARE", + "CH1_RCV_DCC_EN": "DONTCARE", + "CH1_REG_BAND_OFFSET": "DONTCARE", + "CH1_REG_BAND_SEL": "DONTCARE", + "CH1_REG_IDAC_EN": "DONTCARE", + "CH1_REG_IDAC_SEL": "DONTCARE", + "CH1_REQ_EN": "DONTCARE", + "CH1_REQ_LVL_SET": "DONTCARE", + "CH1_RIO_MODE": "DONTCARE", + "CH1_RLOS_SEL": "DONTCARE", + "CH1_RPWDNB": "DONTCARE", + "CH1_RTERM_RX": "DONTCARE", + "CH1_RTERM_TX": "DONTCARE", + "CH1_RXIN_CM": "DONTCARE", + "CH1_RXTERM_CM": "DONTCARE", + "CH1_RX_DCO_CK_DIV": "DONTCARE", + "CH1_RX_DIV11_SEL": "DONTCARE", + "CH1_RX_GEAR_BYPASS": "DONTCARE", + "CH1_RX_GEAR_MODE": "DONTCARE", + "CH1_RX_LOS_CEQ": "DONTCARE", + "CH1_RX_LOS_EN": "DONTCARE", + "CH1_RX_LOS_HYST_EN": "DONTCARE", + "CH1_RX_LOS_LVL": "DONTCARE", + "CH1_RX_RATE_SEL": "DONTCARE", + "CH1_RX_SB_BYPASS": "DONTCARE", + "CH1_SB_BYPASS": "DONTCARE", + "CH1_SEL_SD_RX_CLK": "DONTCARE", + "CH1_TDRV_DAT_SEL": "DONTCARE", + "CH1_TDRV_POST_EN": "DONTCARE", + "CH1_TDRV_PRE_EN": "DONTCARE", + "CH1_TDRV_SLICE0_CUR": "DONTCARE", + "CH1_TDRV_SLICE0_SEL": "DONTCARE", + "CH1_TDRV_SLICE1_CUR": "DONTCARE", + "CH1_TDRV_SLICE1_SEL": "DONTCARE", + "CH1_TDRV_SLICE2_CUR": "DONTCARE", + "CH1_TDRV_SLICE2_SEL": "DONTCARE", + "CH1_TDRV_SLICE3_CUR": "DONTCARE", + "CH1_TDRV_SLICE3_SEL": "DONTCARE", + "CH1_TDRV_SLICE4_CUR": "DONTCARE", + "CH1_TDRV_SLICE4_SEL": "DONTCARE", + "CH1_TDRV_SLICE5_CUR": "DONTCARE", + "CH1_TDRV_SLICE5_SEL": "DONTCARE", + "CH1_TPWDNB": "DONTCARE", + "CH1_TXAMPLITUDE": "DONTCARE", + "CH1_TXDEPOST": "DONTCARE", + "CH1_TXDEPRE": "DONTCARE", + "CH1_TX_CM_SEL": "DONTCARE", + "CH1_TX_DIV11_SEL": "DONTCARE", + "CH1_TX_GEAR_BYPASS": "DONTCARE", + "CH1_TX_GEAR_MODE": "DONTCARE", + "CH1_TX_POST_SIGN": "DONTCARE", + "CH1_TX_PRE_SIGN": "DONTCARE", + "CH1_UC_MODE": "DONTCARE", + "CH1_UDF_COMMA_A": "DONTCARE", + "CH1_UDF_COMMA_B": "DONTCARE", + "CH1_UDF_COMMA_MASK": "DONTCARE", + "CH1_WA_BYPASS": "DONTCARE", + "CH1_WA_MODE": "DONTCARE", + "D_BITCLK_FROM_ND_EN": "DONTCARE", + "D_BITCLK_LOCAL_EN": "DONTCARE", + "D_BITCLK_ND_EN": "DONTCARE", + "D_BUS8BIT_SEL": "DONTCARE", + "D_CDR_LOL_SET": "DONTCARE", + "D_CMUSETBIASI": "DONTCARE", + "D_CMUSETI4CPP": "DONTCARE", + "D_CMUSETI4CPZ": "DONTCARE", + "D_CMUSETI4VCO": "DONTCARE", + "D_CMUSETICP4P": "DONTCARE", + "D_CMUSETICP4Z": "DONTCARE", + "D_CMUSETINITVCT": "DONTCARE", + "D_CMUSETISCL4VCO": "DONTCARE", + "D_CMUSETP1GM": "DONTCARE", + "D_CMUSETP2AGM": "DONTCARE", + "D_CMUSETZGM": "DONTCARE", + "D_DCO_CALIB_TIME_SEL": "DONTCARE", + "D_HIGH_MARK": "DONTCARE", + "D_IB_PWDNB": "DONTCARE", + "D_ISETLOS": "DONTCARE", + "D_LOW_MARK": "DONTCARE", + "D_MACROPDB": "DONTCARE", + "D_PD_ISET": "DONTCARE", + "D_PLL_LOL_SET": "DONTCARE", + "D_REFCK_MODE": "DONTCARE", + "D_REQ_ISET": "DONTCARE", + "D_RG_EN": "DONTCARE", + "D_RG_SET": "DONTCARE", + "D_SETICONST_AUX": "DONTCARE", + "D_SETICONST_CH": "DONTCARE", + "D_SETIRPOLY_AUX": "DONTCARE", + "D_SETIRPOLY_CH": "DONTCARE", + "D_SETPLLRC": "DONTCARE", + "D_SYNC_LOCAL_EN": "DONTCARE", + "D_SYNC_ND_EN": "DONTCARE", + "D_TXPLL_PWDNB": "DONTCARE", + "D_TX_MAX_RATE": "DONTCARE", + "D_TX_VCO_CK_DIV": "DONTCARE", + "D_XGE_MODE": "DONTCARE" + }, + "ports": { + "CH0_HDINP": { + "direction": "input", + "bits": [ 2 ] + }, + "CH1_HDINP": { + "direction": "input", + "bits": [ 3 ] + }, + "CH0_HDINN": { + "direction": "input", + "bits": [ 4 ] + }, + "CH1_HDINN": { + "direction": "input", + "bits": [ 5 ] + }, + "D_TXBIT_CLKP_FROM_ND": { + "direction": "input", + "bits": [ 6 ] + }, + "D_TXBIT_CLKN_FROM_ND": { + "direction": "input", + "bits": [ 7 ] + }, + "D_SYNC_ND": { + "direction": "input", + "bits": [ 8 ] + }, + "D_TXPLL_LOL_FROM_ND": { + "direction": "input", + "bits": [ 9 ] + }, + "CH0_RX_REFCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "CH1_RX_REFCLK": { + "direction": "input", + "bits": [ 11 ] + }, + "CH0_FF_RXI_CLK": { + "direction": "input", + "bits": [ 12 ] + }, + "CH1_FF_RXI_CLK": { + "direction": "input", + "bits": [ 13 ] + }, + "CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 86 ] + }, + "CH1_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 87 ] + }, + "CH0_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 88 ] + }, + "CH1_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 89 ] + }, + "CH0_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 90 ] + }, + "CH1_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 91 ] + }, + "CH0_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 92 ] + }, + "CH1_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 93 ] + }, + "CH0_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 94 ] + }, + "CH1_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 95 ] + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 96 ] + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 97 ] + }, + "CH0_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 98 ] + }, + "CH1_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 99 ] + }, + "CH0_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 100 ] + }, + "CH1_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 101 ] + }, + "CH0_FFC_RRST": { + "direction": "input", + "bits": [ 102 ] + }, + "CH1_FFC_RRST": { + "direction": "input", + "bits": [ 103 ] + }, + "CH0_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 104 ] + }, + "CH1_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 105 ] + }, + "CH0_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 106 ] + }, + "CH1_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 107 ] + }, + "CH0_LDR_CORE2TX": { + "direction": "input", + "bits": [ 108 ] + }, + "CH1_LDR_CORE2TX": { + "direction": "input", + "bits": [ 109 ] + }, + "D_SCIWDATA0": { + "direction": "input", + "bits": [ 110 ] + }, + "D_SCIWDATA1": { + "direction": "input", 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}, + "CH1_SCIEN": { + "direction": "input", + "bits": [ 127 ] + }, + "CH0_SCISEL": { + "direction": "input", + "bits": [ 128 ] + }, + "CH1_SCISEL": { + "direction": "input", + "bits": [ 129 ] + }, + "D_SCIRD": { + "direction": "input", + "bits": [ 130 ] + }, + "D_SCIWSTN": { + "direction": "input", + "bits": [ 131 ] + }, + "D_CYAWSTN": { + "direction": "input", + "bits": [ 132 ] + }, + "D_FFC_SYNC_TOGGLE": { + "direction": "input", + "bits": [ 133 ] + }, + "D_FFC_DUAL_RST": { + "direction": "input", + "bits": [ 134 ] + }, + "D_FFC_MACRO_RST": { + "direction": "input", + "bits": [ 135 ] + }, + "D_FFC_MACROPDB": { + "direction": "input", + "bits": [ 136 ] + }, + "D_FFC_TRST": { + "direction": "input", + "bits": [ 137 ] + }, + "CH0_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 138 ] + }, + "CH1_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 139 ] + }, + "D_SCAN_ENABLE": { + "direction": "input", + "bits": [ 140 ] + }, + "D_SCAN_IN_0": { + "direction": "input", + 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"x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], + "attributes": { + "src": "hardware/v2/synthesis/harness_neural_director.v:36.61-36.77" + } + }, + "slot_w_base": { + "hide_name": 0, + "bits": [ 44, 72, 179, 189, 186, 177, 184, 181, "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], + "attributes": { + "src": "hardware/v2/synthesis/harness_neural_director.v:36.48-36.59" + } + }, + "slot_x_base": { + "hide_name": 0, + "bits": [ 50, 71, 201, 209, 199, 203, 205, 211, "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], + "attributes": { + "src": "hardware/v2/synthesis/harness_neural_director.v:36.35-36.46" + } + } + } + } + } +} diff --git a/hardware/v2/synthesis/harness_neural_director/yosys.log b/hardware/v2/synthesis/harness_neural_director/yosys.log new file mode 100644 index 0000000..59243c2 --- /dev/null +++ b/hardware/v2/synthesis/harness_neural_director/yosys.log @@ -0,0 +1,2132 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) + +-- Parsing `hardware/v2/rtl/neural_director.v' using frontend ` -vlog2k' -- + +1. Executing Verilog-2005 frontend: hardware/v2/rtl/neural_director.v +Parsing Verilog input from `hardware/v2/rtl/neural_director.v' to AST representation. +Storing AST representation for module `$abstract\neural_director'. +Successfully finished Verilog frontend. + +-- Parsing `hardware/v2/synthesis/harness_neural_director.v' using frontend ` -vlog2k' -- + +2. Executing Verilog-2005 frontend: hardware/v2/synthesis/harness_neural_director.v +Parsing Verilog input from `hardware/v2/synthesis/harness_neural_director.v' to AST representation. +Storing AST representation for module `$abstract\harness_neural_director'. +Successfully finished Verilog frontend. + +-- Running command `synth_ecp5 -json hardware/v2/synthesis/harness_neural_director/top.json -top harness_neural_director' -- + +3. Executing SYNTH_LATTICE pass. + +3.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +3.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +3.3. Executing HIERARCHY pass (managing design hierarchy). + +3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_neural_director'. +Generating RTLIL representation for module `\harness_neural_director'. + +3.4.1. Analyzing design hierarchy.. +Top module: \harness_neural_director +Parameter \ADDR_WIDTH = 23 +Parameter \N_SLOTS = 4 +Parameter \QUEUE_DEPTH = 8 + +3.4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\neural_director'. +Parameter \ADDR_WIDTH = 23 +Parameter \N_SLOTS = 4 +Parameter \QUEUE_DEPTH = 8 +Generating RTLIL representation for module `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director'. + +3.4.3. Analyzing design hierarchy.. +Top module: \harness_neural_director +Used module: $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director + +3.4.4. Analyzing design hierarchy.. +Top module: \harness_neural_director +Used module: $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director +Removing unused module `$abstract\harness_neural_director'. +Removing unused module `$abstract\neural_director'. +Removed 2 unused modules. + +3.5. Executing PROC pass (convert processes to netlists). + +3.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:123$268 in module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director. +Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:116$261 in module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director. +Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:102$260 in module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director. +Marked 1 switch rules as full_case in process $proc$hardware/v2/synthesis/harness_neural_director.v:58$233 in module harness_neural_director. +Marked 1 switch rules as full_case in process $proc$hardware/v2/synthesis/harness_neural_director.v:21$228 in module harness_neural_director. +Removed a total of 0 dead cases. + +3.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 4 redundant assignments. +Promoted 37 assignments to connections. + +3.5.4. Executing PROC_INIT pass (extract init attributes). + +3.5.5. Executing PROC_ARST pass (detect async resets in processes). + +3.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + 1/61: $2$lookahead\slot_busy$267[3:0]$356 + 2/61: $2$lookahead\slot_result_addr$266[91:0]$355 + 3/61: $2$lookahead\slot_n_tiles$265[63:0]$354 + 4/61: $2$lookahead\slot_w_base$264[91:0]$353 + 5/61: $2$lookahead\slot_x_base$263[91:0]$352 + 6/61: $2$lookahead\slot_job_start$262[3:0]$351 + 7/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:195$249[1:0]$350 + 8/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:194$248[31:0]$349 + 9/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:193$247[31:0]$348 + 10/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:192$246[31:0]$347 + 11/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:191$245[31:0]$346 + 12/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:190$244[1:0]$345 + 13/61: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_EN[15:0]$338 + 14/61: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_DATA[15:0]$337 + 15/61: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_ADDR[2:0]$336 + 16/61: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$335 + 17/61: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_DATA[22:0]$334 + 18/61: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_ADDR[2:0]$333 + 19/61: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$332 + 20/61: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_DATA[15:0]$331 + 21/61: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_ADDR[2:0]$330 + 22/61: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$329 + 23/61: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_DATA[22:0]$328 + 24/61: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_ADDR[2:0]$327 + 25/61: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$326 + 26/61: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_DATA[22:0]$325 + 27/61: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_ADDR[2:0]$324 + 28/61: $0\job_out_done[0:0] + 29/61: $1$lookahead\slot_result_addr$266[91:0]$321 + 30/61: $1$lookahead\slot_n_tiles$265[63:0]$320 + 31/61: $1$lookahead\slot_w_base$264[91:0]$319 + 32/61: $1$lookahead\slot_x_base$263[91:0]$318 + 33/61: $1$lookahead\slot_job_start$262[3:0]$317 + 34/61: $1$lookahead\slot_busy$267[3:0]$322 + 35/61: $0\q_count[3:0] + 36/61: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_EN[15:0]$316 + 37/61: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_DATA[15:0]$315 + 38/61: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_ADDR[2:0]$314 + 39/61: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$313 + 40/61: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_DATA[22:0]$312 + 41/61: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_ADDR[2:0]$311 + 42/61: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$310 + 43/61: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_DATA[15:0]$309 + 44/61: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_ADDR[2:0]$308 + 45/61: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$307 + 46/61: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_DATA[22:0]$306 + 47/61: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_ADDR[2:0]$305 + 48/61: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$304 + 49/61: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_DATA[22:0]$303 + 50/61: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_ADDR[2:0]$302 + 51/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:195$249[1:0]$301 + 52/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:194$248[31:0]$300 + 53/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:193$247[31:0]$299 + 54/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:192$246[31:0]$298 + 55/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:191$245[31:0]$297 + 56/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:190$244[1:0]$296 + 57/61: $0\q_tail[2:0] + 58/61: $0\q_head[2:0] + 59/61: $0\dir_error[0:0] + 60/61: $0\dir_state[3:0] + 61/61: $0\job_out_slot[1:0] +Creating decoders for process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$261'. + 1/4: $4\done_slot_idx[1:0] + 2/4: $3\done_slot_idx[1:0] + 3/4: $2\done_slot_idx[1:0] + 4/4: $1\done_slot_idx[1:0] +Creating decoders for process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$260'. + 1/4: $4\free_slot_idx[1:0] + 2/4: $3\free_slot_idx[1:0] + 3/4: $2\free_slot_idx[1:0] + 4/4: $1\free_slot_idx[1:0] +Creating decoders for process `\harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:58$233'. + 1/1: $0\chk[7:0] +Creating decoders for process `\harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:21$228'. + 1/1: $0\lfsr[31:0] + +3.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\done_slot_idx' from process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$261'. +No latch inferred for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\di' from process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$261'. +No latch inferred for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\free_slot_idx' from process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$260'. +No latch inferred for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\fi' from process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$260'. + +3.5.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_job_start' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$752' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_x_base' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$753' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_w_base' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$754' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_result_addr' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$755' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_n_tiles' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$756' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\job_out_done' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$757' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\job_out_slot' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$758' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\dir_state' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$759' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\dir_error' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$760' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\q_head' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$761' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\q_tail' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$762' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\q_count' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$763' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_busy' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$764' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:190$244' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$765' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:191$245' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$766' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:192$246' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$767' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:193$247' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$768' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:194$248' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$769' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:195$249' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$770' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$771' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$772' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$773' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$774' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$775' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$776' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$777' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$778' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$779' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$780' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$781' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$782' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$783' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$784' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$785' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_job_start$262' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$786' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_x_base$263' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$787' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_w_base$264' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$788' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_n_tiles$265' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$789' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_result_addr$266' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$790' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_busy$267' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. + created $dff cell `$procdff$791' with positive edge clock. +Creating register for signal `\harness_neural_director.\chk' using process `\harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:58$233'. + created $dff cell `$procdff$792' with positive edge clock. +Creating register for signal `\harness_neural_director.\lfsr' using process `\harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:21$228'. + created $dff cell `$procdff$793' with positive edge clock. + +3.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 6 empty switches in `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. +Removing empty process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'. +Found and cleaned up 4 empty switches in `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$261'. +Removing empty process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$261'. +Found and cleaned up 4 empty switches in `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$260'. +Removing empty process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$260'. +Found and cleaned up 1 empty switch in `\harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:58$233'. +Removing empty process `harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:58$233'. +Found and cleaned up 1 empty switch in `\harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:21$228'. +Removing empty process `harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:21$228'. +Cleaned up 16 empty switches. + +3.5.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director. + +Optimizing module harness_neural_director. + + +3.6. Executing CHECK pass (checking for obvious problems). +Checking module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director... +Checking module harness_neural_director... +Found and reported 0 problems. + +3.7. Executing FLATTEN pass (flatten design). +Deleting now unused module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director. + + +3.8. Executing TRIBUF pass. + +3.9. Executing DEMINOUT pass (demote inout ports to input or output). + +3.10. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + + +3.11. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. +Removed 64 unused cells and 276 unused wires. + + +3.12. Executing CHECK pass (checking for obvious problems). +Checking module harness_neural_director... +Found and reported 0 problems. + +3.13. Executing OPT pass (performing simple optimizations). + +3.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 192 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 174 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 170 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 168 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 166 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. + +Removed a total of 26 cells. + +3.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\dut.$procmux$463. + dead port 1/2 on $mux $flatten\dut.$procmux$529. + dead port 1/2 on $mux $flatten\dut.$procmux$535. + dead port 1/2 on $mux $flatten\dut.$procmux$541. + dead port 1/2 on $mux $flatten\dut.$procmux$547. + dead port 1/2 on $mux $flatten\dut.$procmux$553. + dead port 1/2 on $mux $flatten\dut.$procmux$559. + dead port 1/2 on $mux $flatten\dut.$procmux$565. + dead port 1/2 on $mux $flatten\dut.$procmux$571. + dead port 1/2 on $mux $flatten\dut.$procmux$577. + dead port 1/2 on $mux $flatten\dut.$procmux$583. + dead port 1/2 on $mux $flatten\dut.$procmux$589. + dead port 1/2 on $mux $flatten\dut.$procmux$595. + dead port 1/2 on $mux $flatten\dut.$procmux$428. + dead port 1/2 on $mux $flatten\dut.$procmux$456. + dead port 1/2 on $mux $flatten\dut.$procmux$449. + dead port 1/2 on $mux $flatten\dut.$procmux$435. + dead port 1/2 on $mux $flatten\dut.$procmux$442. +Removed 18 multiplexer ports. + + +3.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$526: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\dut.$procmux$526_Y + New ports: A=1'0, B=1'1, Y=$flatten\dut.$procmux$526_Y [0] + New connections: $flatten\dut.$procmux$526_Y [22:1] = { $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] } + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$544: + Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$flatten\dut.$procmux$544_Y + New ports: A=1'0, B=1'1, Y=$flatten\dut.$procmux$544_Y [0] + New connections: $flatten\dut.$procmux$544_Y [15:1] = { $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] } + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$562: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\dut.$procmux$562_Y + New ports: A=1'0, B=1'1, Y=$flatten\dut.$procmux$562_Y [0] + New connections: $flatten\dut.$procmux$562_Y [22:1] = { $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] } + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$580: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\dut.$procmux$580_Y + New ports: A=1'0, B=1'1, Y=$flatten\dut.$procmux$580_Y [0] + New connections: $flatten\dut.$procmux$580_Y [22:1] = { $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] } + New ctrl vector for $pmux cell $flatten\dut.$procmux$707: { $flatten\dut.$procmux$708_CMP $auto$opt_reduce.cc:137:opt_pmux$801 $flatten\dut.$eq$hardware/v2/rtl/neural_director.v:212$416_Y } + Optimizing cells in module \harness_neural_director. + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$637: + Old ports: A=$flatten\dut.$2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$335, B=23'00000000000000000000000, Y=$flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 + New ports: A=$flatten\dut.$procmux$526_Y [0], B=1'0, Y=$flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] + New connections: $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [22:1] = { $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] } + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$646: + Old ports: A=$flatten\dut.$2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$332, B=16'0000000000000000, Y=$flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 + New ports: A=$flatten\dut.$procmux$544_Y [0], B=1'0, Y=$flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] + New connections: $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [15:1] = { $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] } + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$655: + Old ports: A=$flatten\dut.$2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$329, B=23'00000000000000000000000, Y=$flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 + New ports: A=$flatten\dut.$procmux$562_Y [0], B=1'0, Y=$flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] + New connections: $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [22:1] = { $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] } + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$664: + Old ports: A=$flatten\dut.$2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$326, B=23'00000000000000000000000, Y=$flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 + New ports: A=$flatten\dut.$procmux$580_Y [0], B=1'0, Y=$flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] + New connections: $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [22:1] = { $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] } + Optimizing cells in module \harness_neural_director. +Performed a total of 9 changes. + +3.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 149 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 143 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 137 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. + +Removed a total of 12 cells. + +3.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. +Removed 0 unused cells and 56 unused wires. + + +3.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. +Performed a total of 0 changes. + +3.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 137 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.13.16. Finished fast OPT passes. (There is nothing left to do.) + +3.14. Executing FSM pass (extract and optimize FSM). + +3.14.1. Executing FSM_DETECT pass (finding FSMs in design). +Not marking harness_neural_director.dut.dir_state as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking harness_neural_director.dut.job_out_slot as FSM state register: + Users of register don't seem to benefit from recoding. + +3.14.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +3.14.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +3.14.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.14.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +3.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +3.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +3.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +3.15. Executing OPT pass (performing simple optimizations). + +3.15.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.15.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 137 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. +Performed a total of 0 changes. + +3.15.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 137 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.15.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $procdff$793 ($dff) from module harness_neural_director (D = { \lfsr [30:7] $xor$hardware/v2/synthesis/harness_neural_director.v:23$232_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001). +Adding SRST signal on $procdff$792 ($dff) from module harness_neural_director (D = $xor$hardware/v2/synthesis/harness_neural_director.v:60$243_Y, Q = \chk, rval = 8'00000000). +Adding SRST signal on $flatten\dut.$procdff$764 ($dff) from module harness_neural_director (D = $flatten\dut.$2$lookahead\slot_busy$267[3:0]$356, Q = \dut.slot_busy, rval = 4'0000). +Adding SRST signal on $flatten\dut.$procdff$763 ($dff) from module harness_neural_director (D = $flatten\dut.$procmux$621_Y, Q = \dut.q_count, rval = 4'0000). +Adding EN signal on $auto$ff.cc:337:slice$806 ($sdff) from module harness_neural_director (D = $flatten\dut.$procmux$621_Y, Q = \dut.q_count). +Adding SRST signal on $flatten\dut.$procdff$762 ($dff) from module harness_neural_director (D = $flatten\dut.$procmux$691_Y, Q = \dut.q_tail, rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$810 ($sdff) from module harness_neural_director (D = $flatten\dut.$ternary$hardware/v2/rtl/neural_director.v:152$341_Y, Q = \dut.q_tail). +Adding SRST signal on $flatten\dut.$procdff$761 ($dff) from module harness_neural_director (D = $flatten\dut.$procmux$698_Y, Q = \dut.q_head, rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$812 ($sdff) from module harness_neural_director (D = $flatten\dut.$ternary$hardware/v2/rtl/neural_director.v:196$415_Y, Q = \dut.q_head). +Adding EN signal on $flatten\dut.$procdff$760 ($dff) from module harness_neural_director (D = 1'0, Q = \dut.dir_error). +Adding SRST signal on $flatten\dut.$procdff$759 ($dff) from module harness_neural_director (D = $flatten\dut.$procmux$707_Y, Q = \dut.dir_state, rval = 4'0000). +Adding EN signal on $auto$ff.cc:337:slice$815 ($sdff) from module harness_neural_director (D = $flatten\dut.$procmux$707_Y, Q = \dut.dir_state). +Adding SRST signal on $flatten\dut.$procdff$758 ($dff) from module harness_neural_director (D = $flatten\dut.$procmux$717_Y, Q = \dut.job_out_slot, rval = 2'00). +Adding EN signal on $auto$ff.cc:337:slice$823 ($sdff) from module harness_neural_director (D = \dut.done_slot_idx, Q = \dut.job_out_slot). +Adding SRST signal on $flatten\dut.$procdff$757 ($dff) from module harness_neural_director (D = $flatten\dut.$procmux$597_Y, Q = \dut.job_out_done, rval = 1'0). +Adding SRST signal on $flatten\dut.$procdff$756 ($dff) from module harness_neural_director (D = $flatten\dut.$2$lookahead\slot_n_tiles$265[63:0]$354, Q = \dut.slot_n_tiles, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$826 ($sdff) from module harness_neural_director (D = $flatten\dut.$or$hardware/v2/rtl/neural_director.v:193$395_Y, Q = \dut.slot_n_tiles). +Adding SRST signal on $flatten\dut.$procdff$755 ($dff) from module harness_neural_director (D = $flatten\dut.$2$lookahead\slot_result_addr$266[91:0]$355, Q = \dut.slot_result_addr, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$828 ($sdff) from module harness_neural_director (D = $flatten\dut.$or$hardware/v2/rtl/neural_director.v:194$405_Y, Q = \dut.slot_result_addr). +Adding SRST signal on $flatten\dut.$procdff$754 ($dff) from module harness_neural_director (D = $flatten\dut.$2$lookahead\slot_w_base$264[91:0]$353, Q = \dut.slot_w_base, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$830 ($sdff) from module harness_neural_director (D = $flatten\dut.$or$hardware/v2/rtl/neural_director.v:192$385_Y, Q = \dut.slot_w_base). +Adding SRST signal on $flatten\dut.$procdff$753 ($dff) from module harness_neural_director (D = $flatten\dut.$2$lookahead\slot_x_base$263[91:0]$352, Q = \dut.slot_x_base, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$832 ($sdff) from module harness_neural_director (D = $flatten\dut.$or$hardware/v2/rtl/neural_director.v:191$375_Y, Q = \dut.slot_x_base). +Adding SRST signal on $flatten\dut.$procdff$752 ($dff) from module harness_neural_director (D = $flatten\dut.$or$hardware/v2/rtl/neural_director.v:190$365_Y, Q = \dut.slot_job_start, rval = 4'0000). +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$814 ($dffe) from module harness_neural_director. + +3.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. +Removed 22 unused cells and 22 unused wires. + + +3.15.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + + +3.15.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. +Performed a total of 0 changes. + +3.15.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 120 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.15.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. +Removed 0 unused cells and 1 unused wires. + + +3.15.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.15.16. Rerunning OPT passes. (Maybe there is more to do..) + +3.15.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.15.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. +Performed a total of 0 changes. + +3.15.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 120 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.15.20. Executing OPT_DFF pass (perform DFF optimizations). + +3.15.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.15.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.15.23. Finished fast OPT passes. (There is nothing left to do.) + +3.16. Executing WREDUCE pass (reducing word size of cells). +Removed top 1 bits (of 2) from port B of cell harness_neural_director.$auto$opt_dff.cc:320:make_patterns_logic$820 ($ne). +Removed top 7 bits (of 8) from port B of cell harness_neural_director.$xor$hardware/v2/synthesis/harness_neural_director.v:60$234 ($xor). +Removed top 7 bits (of 8) from port B of cell harness_neural_director.$xor$hardware/v2/synthesis/harness_neural_director.v:60$240 ($xor). +Removed top 6 bits (of 8) from port B of cell harness_neural_director.$xor$hardware/v2/synthesis/harness_neural_director.v:60$241 ($xor). +Removed top 24 bits (of 32) from mux cell harness_neural_director.$procmux$750 ($mux). +Removed top 2 bits (of 4) from port B of cell harness_neural_director.$flatten\dut.$procmux$708_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell harness_neural_director.$flatten\dut.$procmux$622_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell harness_neural_director.$flatten\dut.$procmux$426_CMP0 ($eq). +Removed top 3 bits (of 4) from port B of cell harness_neural_director.$flatten\dut.$eq$hardware/v2/rtl/neural_director.v:212$416 ($eq). +Converting cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:195$406 ($neg) from signed to unsigned. +Removed top 1 bits (of 3) from port A of cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:195$406 ($neg). +Converting cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:194$403 ($neg) from signed to unsigned. +Removed top 1 bits (of 33) from port A of cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:194$403 ($neg). +Removed top 27 bits (of 32) from port B of cell harness_neural_director.$flatten\dut.$mul$hardware/v2/rtl/neural_director.v:194$396 ($mul). +Removed top 25 bits (of 32) from port Y of cell harness_neural_director.$flatten\dut.$mul$hardware/v2/rtl/neural_director.v:194$396 ($mul). +Removed top 26 bits (of 33) from port A of cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:193$393 ($neg). +Converting cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:193$393 ($neg) from signed to unsigned. +Removed top 1 bits (of 7) from port A of cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:193$393 ($neg). +Removed top 25 bits (of 32) from wire harness_neural_director.$flatten\dut.$add$hardware/v2/rtl/neural_director.v:191$367_Y. +Removed top 24 bits (of 32) from wire harness_neural_director.$0\lfsr[31:0]. + +3.17. Executing PEEPOPT pass (run peephole optimizers). +left shiftmul pattern in harness_neural_director: shift=$flatten\dut.$shift$hardware/v2/rtl/neural_director.v:194$399, mul=$flatten\dut.$mul$hardware/v2/rtl/neural_director.v:194$396 +left shiftmul pattern in harness_neural_director: shift=$flatten\dut.$shift$hardware/v2/rtl/neural_director.v:194$404, mul=$flatten\dut.$mul$hardware/v2/rtl/neural_director.v:194$396 +left shiftmul pattern in harness_neural_director: shift=$flatten\dut.$shift$hardware/v2/rtl/neural_director.v:192$384, mul=$flatten\dut.$mul$hardware/v2/rtl/neural_director.v:194$396 +left shiftmul pattern in harness_neural_director: shift=$flatten\dut.$shift$hardware/v2/rtl/neural_director.v:191$374, mul=$flatten\dut.$mul$hardware/v2/rtl/neural_director.v:194$396 + +3.18. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. +Removed 2 unused cells and 4 unused wires. + + +3.19. Executing SHARE pass (SAT-based resource sharing). + +3.20. Executing TECHMAP pass (map to technology primitives). + +3.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +3.20.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.21. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.22. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.23. Executing TECHMAP pass (map to technology primitives). + +3.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +3.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.24. Executing TECHMAP pass (map to technology primitives). + +3.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +3.24.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.25. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module harness_neural_director: + creating $macc model for $auto$peepopt_pm.h:1040:block_9$846 ($neg). + creating $macc model for $auto$peepopt_pm.h:1040:block_9$843 ($neg). + creating $macc model for $auto$peepopt_pm.h:1040:block_9$852 ($neg). + creating $macc model for $flatten\dut.$neg$hardware/v2/rtl/neural_director.v:195$406 ($neg). + creating $macc model for $flatten\dut.$add$hardware/v2/rtl/neural_director.v:213$421 ($add). + creating $macc model for $flatten\dut.$sub$hardware/v2/rtl/neural_director.v:214$422 ($sub). + creating $macc model for $auto$peepopt_pm.h:1040:block_9$849 ($neg). + creating $macc model for $flatten\dut.$add$hardware/v2/rtl/neural_director.v:196$414 ($add). + creating $macc model for $flatten\dut.$add$hardware/v2/rtl/neural_director.v:152$340 ($add). + creating $macc model for $flatten\dut.$neg$hardware/v2/rtl/neural_director.v:193$393 ($neg). + creating $alu model for $macc $flatten\dut.$neg$hardware/v2/rtl/neural_director.v:193$393. + creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/neural_director.v:152$340. + creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/neural_director.v:196$414. + creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$849. + creating $alu model for $macc $flatten\dut.$sub$hardware/v2/rtl/neural_director.v:214$422. + creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/neural_director.v:213$421. + creating $alu model for $macc $flatten\dut.$neg$hardware/v2/rtl/neural_director.v:195$406. + creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$852. + creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$843. + creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$846. + creating $alu cell for $flatten\dut.$neg$hardware/v2/rtl/neural_director.v:195$406: $auto$alumacc.cc:548:replace_alu$854 + creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/neural_director.v:213$421: $auto$alumacc.cc:548:replace_alu$857 + creating $alu cell for $flatten\dut.$sub$hardware/v2/rtl/neural_director.v:214$422: $auto$alumacc.cc:548:replace_alu$860 + creating $alu cell for $auto$peepopt_pm.h:1040:block_9$846: $auto$alumacc.cc:548:replace_alu$863 + creating $alu cell for $auto$peepopt_pm.h:1040:block_9$843: $auto$alumacc.cc:548:replace_alu$866 + creating $alu cell for $auto$peepopt_pm.h:1040:block_9$852: $auto$alumacc.cc:548:replace_alu$869 + creating $alu cell for $auto$peepopt_pm.h:1040:block_9$849: $auto$alumacc.cc:548:replace_alu$872 + creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/neural_director.v:196$414: $auto$alumacc.cc:548:replace_alu$875 + creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/neural_director.v:152$340: $auto$alumacc.cc:548:replace_alu$878 + creating $alu cell for $flatten\dut.$neg$hardware/v2/rtl/neural_director.v:193$393: $auto$alumacc.cc:548:replace_alu$881 + created 10 $alu and 0 $macc cells. + +3.26. Executing OPT pass (performing simple optimizations). + +3.26.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.26.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 122 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 119 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. + +Removed a total of 3 cells. + +3.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. +Performed a total of 0 changes. + +3.26.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 119 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.26.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.26.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. +Removed 0 unused cells and 9 unused wires. + + +3.26.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.26.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.26.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.26.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. +Performed a total of 0 changes. + +3.26.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 119 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.26.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.26.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.26.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.26.16. Finished fast OPT passes. (There is nothing left to do.) + +3.27. Executing MEMORY pass. + +3.27.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +3.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +3.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing harness_neural_director.dut.q_w_base write port 0. + Analyzing harness_neural_director.dut.q_n_tiles write port 0. + Analyzing harness_neural_director.dut.q_result_addr write port 0. + Analyzing harness_neural_director.dut.q_x_base write port 0. + +3.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +3.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\dut.q_w_base'[0] in module `\harness_neural_director': no output FF found. +Checking read port `\dut.q_n_tiles'[0] in module `\harness_neural_director': no output FF found. +Checking read port `\dut.q_result_addr'[0] in module `\harness_neural_director': no output FF found. +Checking read port `\dut.q_x_base'[0] in module `\harness_neural_director': no output FF found. +Checking read port address `\dut.q_w_base'[0] in module `\harness_neural_director': merged address FF to cell. +Checking read port address `\dut.q_n_tiles'[0] in module `\harness_neural_director': merged address FF to cell. +Checking read port address `\dut.q_result_addr'[0] in module `\harness_neural_director': merged address FF to cell. +Checking read port address `\dut.q_x_base'[0] in module `\harness_neural_director': merged address FF to cell. + +3.27.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +3.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +3.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.27.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +3.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.29. Executing MEMORY_LIBMAP pass (mapping memories to cells). +mapping memory harness_neural_director.dut.q_n_tiles via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of harness_neural_director.dut.q_n_tiles: $\dut.q_n_tiles$rdreg[0] +mapping memory harness_neural_director.dut.q_w_base via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of harness_neural_director.dut.q_w_base: $\dut.q_w_base$rdreg[0] +mapping memory harness_neural_director.dut.q_x_base via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of harness_neural_director.dut.q_x_base: $\dut.q_x_base$rdreg[0] +mapping memory harness_neural_director.dut.q_result_addr via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of harness_neural_director.dut.q_result_addr: $\dut.q_result_addr$rdreg[0] + + +3.30. Executing TECHMAP pass (map to technology primitives). + +3.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +3.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +3.30.3. Continuing TECHMAP pass. +Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. +No more expansions possible. + + +3.31. Executing OPT pass (performing simple optimizations). + +3.31.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + + +3.31.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 132 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 129 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 126 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 123 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. + +Removed a total of 9 cells. + +3.31.3. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $\dut.q_n_tiles$rdreg[0] ($dff) from module harness_neural_director (D = $auto$rtlil.cc:3402:Mux$895, Q = $\dut.q_n_tiles$rdreg[0]$q, rval = 3'000). + +3.31.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. +Removed 1 unused cells and 168 unused wires. + + +3.31.5. Rerunning OPT passes. (Removed registers in this run.) + +3.31.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.31.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 122 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.31.8. Executing OPT_DFF pass (perform DFF optimizations). + +3.31.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.31.10. Finished fast OPT passes. + +3.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +3.33. Executing OPT pass (performing simple optimizations). + +3.33.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.33.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 122 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. + Consolidated identical input bits for $pmux cell $flatten\dut.$procmux$707: + Old ports: A=4'0011, B=8'00010010, Y=$flatten\dut.$procmux$707_Y + New ports: A=2'11, B=4'0110, Y=$flatten\dut.$procmux$707_Y [1:0] + New connections: $flatten\dut.$procmux$707_Y [3:2] = 2'00 + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$732: + Old ports: A=2'00, B=2'11, Y=$flatten\dut.$1\done_slot_idx[1:0] + New ports: A=1'0, B=1'1, Y=$flatten\dut.$1\done_slot_idx[1:0] [0] + New connections: $flatten\dut.$1\done_slot_idx[1:0] [1] = $flatten\dut.$1\done_slot_idx[1:0] [0] + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$744: + Old ports: A=2'00, B=2'11, Y=$flatten\dut.$1\free_slot_idx[1:0] + New ports: A=1'0, B=1'1, Y=$flatten\dut.$1\free_slot_idx[1:0] [0] + New connections: $flatten\dut.$1\free_slot_idx[1:0] [1] = $flatten\dut.$1\free_slot_idx[1:0] [0] + Optimizing cells in module \harness_neural_director. +Performed a total of 3 changes. + +3.33.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 122 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.33.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.33.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + + +3.33.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.33.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.33.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. +Performed a total of 0 changes. + +3.33.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 120 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.33.13. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$816 ($sdffe) from module harness_neural_director. +Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$816 ($sdffe) from module harness_neural_director. + +3.33.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. +Removed 0 unused cells and 2 unused wires. + + +3.33.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + + +3.33.16. Rerunning OPT passes. (Maybe there is more to do..) + +3.33.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.33.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. +Performed a total of 0 changes. + +3.33.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 120 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.33.20. Executing OPT_DFF pass (perform DFF optimizations). + +3.33.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. +Removed 0 unused cells and 2 unused wires. + + +3.33.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.33.23. Rerunning OPT passes. (Maybe there is more to do..) + +3.33.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.33.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. +Performed a total of 0 changes. + +3.33.26. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 120 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.33.27. Executing OPT_DFF pass (perform DFF optimizations). + +3.33.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.33.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.33.30. Finished fast OPT passes. (There is nothing left to do.) + +3.34. Executing TECHMAP pass (map to technology primitives). + +3.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +3.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +3.34.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $sdffe. +Using extmapper simplemap for cells of type $sdff. +Using extmapper simplemap for cells of type $mux. +Using template $paramod$3ef274a4ad1e446c08416d1cf6cb5ab03146d407\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. +Using template $paramod$c9d98d2d0793a6d8797b9c088dbedb26a7be7121\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_90_alu for cells of type $alu. +Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. +Using template $paramod$ef8fb1849064cca7dc908988762d3374786d9fdb\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $reduce_or. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $reduce_and. +Using extmapper simplemap for cells of type $ne. +Using extmapper simplemap for cells of type $reduce_bool. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $pmux. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $logic_and. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $and. +Using template $paramod$constmap:d6fff7a1d5912e7277ff55b9a478b5115760128b$paramod$64b19f47ed5f126636dbd98d727ec46a7ec08d71\_90_shift_shiftx for cells of type $shift. +Using template $paramod$constmap:f30e016643cdb78b03bc6146a268597b7789262d$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'1 + Constant input on bit 2 of port A: 1'1 + Constant input on bit 3 of port A: 1'1 + Constant input on bit 4 of port A: 1'1 + Constant input on bit 5 of port A: 1'1 + Constant input on bit 6 of port A: 1'1 + Constant input on bit 7 of port A: 1'1 + Constant input on bit 8 of port A: 1'1 + Constant input on bit 9 of port A: 1'1 + Constant input on bit 10 of port A: 1'1 + Constant input on bit 11 of port A: 1'1 + Constant input on bit 12 of port A: 1'1 + Constant input on bit 13 of port A: 1'1 + Constant input on bit 14 of port A: 1'1 + Constant input on bit 15 of port A: 1'1 + Constant input on bit 16 of port A: 1'1 + Constant input on bit 17 of port A: 1'1 + Constant input on bit 18 of port A: 1'1 + Constant input on bit 19 of port A: 1'1 + Constant input on bit 20 of port A: 1'1 + Constant input on bit 21 of port A: 1'1 + Constant input on bit 22 of port A: 1'1 +Creating constmapped module `$paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx'. + +3.34.30. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$2056. + dead port 2/2 on $mux $procmux$2062. + dead port 2/2 on $mux $procmux$2068. + dead port 2/2 on $mux $procmux$2074. + dead port 2/2 on $mux $procmux$2080. + dead port 2/2 on $mux $procmux$2086. + dead port 2/2 on $mux $procmux$2092. +Removed 7 multiplexer ports. + + +3.34.31. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx. + +Removed 0 unused cells and 12 unused wires. +Using template $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx for cells of type $shift. +Using template $paramod$constmap:5a4bd879cde68fe23882c6a271f9c4bb8714bccb$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'1 + Constant input on bit 2 of port A: 1'1 + Constant input on bit 3 of port A: 1'1 + Constant input on bit 4 of port A: 1'1 + Constant input on bit 5 of port A: 1'1 + Constant input on bit 6 of port A: 1'1 + Constant input on bit 7 of port A: 1'1 + Constant input on bit 8 of port A: 1'1 + Constant input on bit 9 of port A: 1'1 + Constant input on bit 10 of port A: 1'1 + Constant input on bit 11 of port A: 1'1 + Constant input on bit 12 of port A: 1'1 + Constant input on bit 13 of port A: 1'1 + Constant input on bit 14 of port A: 1'1 + Constant input on bit 15 of port A: 1'1 +Creating constmapped module `$paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx'. + +3.34.37. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$2380. + dead port 2/2 on $mux $procmux$2386. + dead port 2/2 on $mux $procmux$2392. + dead port 2/2 on $mux $procmux$2398. + dead port 2/2 on $mux $procmux$2404. + dead port 2/2 on $mux $procmux$2410. + dead port 2/2 on $mux $procmux$2416. +Removed 7 multiplexer ports. + + +3.34.38. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx. + +Removed 0 unused cells and 12 unused wires. +Using template $paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $logic_or. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. +No more expansions possible. + + +3.35. Executing OPT pass (performing simple optimizations). + +3.35.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + + +3.35.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 4902 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4819 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4767 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4719 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4679 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4655 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4654 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4653 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4652 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4651 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4650 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4649 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4648 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4647 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4646 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4645 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4644 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4643 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4642 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4641 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4640 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4639 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4638 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4637 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4636 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 4635 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. + +Removed a total of 267 cells. + +3.35.3. Executing OPT_DFF pass (perform DFF optimizations). + +3.35.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. +Removed 3313 unused cells and 556 unused wires. + + +3.35.5. Finished fast OPT passes. + +3.36. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +3.38. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 1322 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.39. Executing TECHMAP pass (map to technology primitives). + +3.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +3.39.2. Continuing TECHMAP pass. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. +Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_. +Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. +No more expansions possible. + + +3.40. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + + +3.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +3.42. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in harness_neural_director. + +3.43. Executing ATTRMVCP pass (move or copy attributes). + +3.44. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. +Removed 0 unused cells and 530 unused wires. + + +3.45. Executing CHECK pass (checking for obvious problems). +Checking module harness_neural_director... +Found and reported 0 problems. + +3.46. Executing TECHMAP pass (map to technology primitives). + +3.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +3.46.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.47. Executing ABC9 pass. + +3.47.1. Executing ABC9_OPS pass (helper functions for ABC9). + +3.47.2. Executing ABC9_OPS pass (helper functions for ABC9). + +3.47.3. Executing PROC pass (convert processes to netlists). + +3.47.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15620'. +Cleaned up 1 empty switch. + +3.47.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. +Removed a total of 0 dead cases. + +3.47.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 22 assignments to connections. + +3.47.3.4. Executing PROC_INIT pass (extract init attributes). + +3.47.3.5. Executing PROC_ARST pass (detect async resets in processes). + +3.47.3.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.47.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621'. + 1/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15619_EN[3:0]$15627 + 2/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15619_DATA[3:0]$15626 + 3/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15619_ADDR[3:0]$15625 +Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15620'. + +3.47.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15603_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15604_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15605_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15606_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15607_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15608_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15609_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15610_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15611_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15612_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15613_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15614_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15615_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15616_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15617_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15618_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15620'. + +3.47.3.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15619_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621'. + created $dff cell `$procdff$15671' with positive edge clock. +Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15619_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621'. + created $dff cell `$procdff$15672' with positive edge clock. +Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15619_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621'. + created $dff cell `$procdff$15673' with positive edge clock. + +3.47.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.47.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'. +Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621'. +Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621'. +Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15620'. +Cleaned up 1 empty switch. + +3.47.4. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module harness_neural_director. +Found 0 SCCs. + +3.47.5. Executing ABC9_OPS pass (helper functions for ABC9). + +3.47.6. Executing TECHMAP pass (map to technology primitives). + +3.47.6.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +3.47.6.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.47.7. Executing OPT pass (performing simple optimizations). + +3.47.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. + +3.47.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Removed a total of 0 cells. + +3.47.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +3.47.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. +Performed a total of 0 changes. + +3.47.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Removed a total of 0 cells. + +3.47.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.47.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. + +3.47.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. + +3.47.7.9. Finished fast OPT passes. (There is nothing left to do.) + +3.47.8. Executing TECHMAP pass (map to technology primitives). + +3.47.8.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +3.47.8.2. Continuing TECHMAP pass. +Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. +No more expansions possible. + + +3.47.9. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3.47.10. Executing ABC9_OPS pass (helper functions for ABC9). + + +3.47.11. Executing ABC9_OPS pass (helper functions for ABC9). + +3.47.12. Executing ABC9_OPS pass (helper functions for ABC9). + + +3.47.13. Executing TECHMAP pass (map to technology primitives). + +3.47.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +3.47.13.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $xor. +Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. +Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +3.47.14. Executing OPT pass (performing simple optimizations). + +3.47.14.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + + +3.47.14.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 59 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Computing hashes of 57 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. + +Removed a total of 2 cells. + +3.47.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +3.47.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. +Performed a total of 0 changes. + +3.47.14.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 57 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.47.14.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.47.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. +Removed 0 unused cells and 55 unused wires. + + +3.47.14.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.47.14.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.47.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_neural_director.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +3.47.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_neural_director. +Performed a total of 0 changes. + +3.47.14.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_neural_director'. +Computing hashes of 57 cells of `\harness_neural_director'. +Finding duplicate cells in `\harness_neural_director'. +Removed a total of 0 cells. + +3.47.14.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.47.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_neural_director.. + +3.47.14.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_neural_director. + +3.47.14.16. Finished fast OPT passes. (There is nothing left to do.) + +3.47.15. Executing AIGMAP pass (map logic to AIG). +Module harness_neural_director: replaced 18 cells with 120 new cells, skipped 39 cells. + replaced 3 cell types: + 14 $_MUX_ + 2 $_OR_ + 2 $_XOR_ + not replaced 3 cell types: + 4 $_AND_ + 4 $_NOT_ + 31 $specify2 + +3.47.16. Executing AIGMAP pass (map logic to AIG). +Module harness_neural_director: replaced 1065 cells with 7191 new cells, skipped 268 cells. + replaced 3 cell types: + 896 $_MUX_ + 88 $_OR_ + 81 $_XOR_ + not replaced 7 cell types: + 52 $_AND_ + 52 $_NOT_ + 1 $scopeinfo + 98 TRELLIS_FF + 21 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C + 22 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 + 22 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp + +3.47.16.1. Executing ABC9_OPS pass (helper functions for ABC9). + +3.47.16.2. Executing ABC9_OPS pass (helper functions for ABC9). + +3.47.16.3. Executing XAIGER backend. + +Extracted 3071 AND gates and 7719 wires from module `harness_neural_director' to a netlist network with 196 inputs and 125 outputs. + +3.47.16.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +3.47.16.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 196/ 125 and = 2092 lev = 41 (1.99) mem = 0.04 MB box = 43 bb = 22 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 196/ 125 and = 622 lev = 12 (1.14) mem = 0.02 MB ch = 83 box = 12 bb = 8 +ABC: cst = 0 cls = 80 lit = 83 unused = 699 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 622. Ch = 80. Total mem = 0.18 MB. Peak cut mem = 0.01 MB. +ABC: P: Del = 1909.00. Ar = 150.0. Edge = 319. Cut = 5224. T = 0.00 sec +ABC: P: Del = 1909.00. Ar = 145.0. Edge = 313. Cut = 5116. T = 0.00 sec +ABC: P: Del = 1909.00. Ar = 104.0. Edge = 302. Cut = 6433. T = 0.00 sec +ABC: F: Del = 1909.00. Ar = 104.0. Edge = 295. Cut = 5867. T = 0.00 sec +ABC: A: Del = 1909.00. Ar = 104.0. Edge = 289. Cut = 5947. T = 0.00 sec +ABC: A: Del = 1909.00. Ar = 104.0. Edge = 289. Cut = 5928. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: + &ps -l +ABC: /input : i/o = 196/ 125 and = 513 lev = 12 (1.13) mem = 0.01 MB box = 12 bb = 8 +ABC: Mapping (K=7) : lut = 87 edge = 288 lev = 3 (0.47) levB = 5 mem = 0.01 MB +ABC: LUT = 87 : 2=12 13.8 % 3=47 54.0 % 4=20 23.0 % 5=6 6.9 % 6=1 1.1 % 7=1 1.1 % Ave = 3.31 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.01 sec +ABC: + time +ABC: elapse: 0.03 seconds, total: 0.03 seconds + +3.47.16.6. Executing AIGER frontend. + +Removed 937 unused cells and 1357 unused wires. + +3.47.16.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 91 +ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 4 +ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 8 +ABC RESULTS: input signals: 36 +ABC RESULTS: output signals: 29 + +Removing temp directory. + +3.47.17. Executing TECHMAP pass (map to technology primitives). + +3.47.17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +3.47.17.2. Continuing TECHMAP pass. +Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. +No more expansions possible. + +Removed 34 unused cells and 8174 unused wires. + +3.48. Executing TECHMAP pass (map to technology primitives). + +3.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +3.48.2. Continuing TECHMAP pass. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. +Using template $paramod$d5841602ab17202e972b290147d14b63f75b0ad1$lut for cells of type $lut. +Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. +Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut. +Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. +Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. +Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f$lut for cells of type $lut. +Using template $paramod$b51fee016110db8338dd45ff659d0ba2666c78b1$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. +Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$d9e869de4ea8677851dc452d380224cee441f821$lut for cells of type $lut. +Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c$lut for cells of type $lut. +Using template $paramod$a982cf8779b70ec0ac96f44f3dab0c5228c954b0$lut for cells of type $lut. +Using template $paramod$766866f5aa0715f9d5b453950f9c60b7c05612b0$lut for cells of type $lut. +Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. +Using template $paramod$59848369e5f408d15e0c8c710ff689c98ce02999$lut for cells of type $lut. +Using template $paramod$f5c97e291c8b48d9f1b4239d871ab7639e5a24ac$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$21a9cf1c7cffed4ea7970972274e8bcced7c7005$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. +Using template $paramod$cd6c4b4da6d8737b72fd2dc8f5d83d8967445809$lut for cells of type $lut. +Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut. +Using template $paramod$5fd0af7ac35c6c117464e59fb19cf691eb70ce85$lut for cells of type $lut. +Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. +No more expansions possible. + + +3.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in harness_neural_director. + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$30523$lut$aiger$o129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) +Removed 0 unused cells and 182 unused wires. + +3.50. Executing AUTONAME pass. +Renamed 337 objects in module harness_neural_director. + + +3.51. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `harness_neural_director'. Setting top module to harness_neural_director. + +3.51.1. Analyzing design hierarchy.. +Top module: \harness_neural_director + +3.51.2. Analyzing design hierarchy.. +Top module: \harness_neural_director +Removed 0 unused modules. + +3.52. Printing statistics. + +=== harness_neural_director === + + +----------Local Count, excluding submodules. + | + 159 wires + 1328 wire bits + 159 public wires + 1328 public wire bits + 4 ports + 18 port bits + 1 cells + 1 $scopeinfo + 233 submodules + 4 CCU2C + 4 L6MUX21 + 107 LUT4 + 12 PFUMX + 8 TRELLIS_DPR16X4 + 98 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + 1 harness_neural_director + + +----------Count including submodules. + | + 159 wires + 1328 wire bits + 159 public wires + 1328 public wire bits + 4 ports + 18 port bits + - memories + - memory bits + - processes + 1 cells + 1 $scopeinfo + 233 submodules + 4 CCU2C + 4 L6MUX21 + 107 LUT4 + 12 PFUMX + 8 TRELLIS_DPR16X4 + 98 TRELLIS_FF + +3.53. Executing CHECK pass (checking for obvious problems). +Checking module harness_neural_director... +Found and reported 0 problems. + +3.54. Executing JSON backend. + +End of script. Logfile hash: f4bf1597d9, time: 0.54s, user: 0.53s, system: 0.02s, MEM: 66.97 MB peak +Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) +Time spent: 31% 23x read_verilog (0 sec), 10% 39x opt_expr (0 sec), ... diff --git a/hardware/v2/synthesis/neural_director_n4/nextpnr.log b/hardware/v2/synthesis/neural_director_n4/nextpnr.log new file mode 100644 index 0000000..c5bec93 --- /dev/null +++ b/hardware/v2/synthesis/neural_director_n4/nextpnr.log @@ -0,0 +1,56 @@ + + +Info: Logic utilisation before packing: +Info: Total LUT4s: 522/43848 1% +Info: logic LUTs: 382/43848 0% +Info: carry LUTs: 8/43848 0% +Info: RAM LUTs: 88/ 5481 1% +Info: RAMW LUTs: 44/10962 0% + +Info: Total DFFs: 366/43848 0% + +Info: Packing IOs.. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 362 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0xb47c9b6c + +Info: Device utilisation: +Info: TRELLIS_IO: 461/ 245 188% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 108 0% +Info: MULT18X18D: 0/ 72 0% +Info: ALU54B: 0/ 36 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 160 0% +Info: SIOLOGIC: 0/ 85 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 10 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 366/ 43848 0% +Info: TRELLIS_COMB: 528/ 43848 1% +Info: TRELLIS_RAMW: 22/ 5481 0% + +Info: Placed 0 cells based on constraints. +ERROR: Unable to place cell 'job_in_n_tiles[9]$tr_io', no BELs remaining to implement cell type 'TRELLIS_IO' +0 warnings, 1 error diff --git a/hardware/v2/synthesis/neural_director_n4/top.json b/hardware/v2/synthesis/neural_director_n4/top.json new file mode 100644 index 0000000..c6126ef --- /dev/null +++ b/hardware/v2/synthesis/neural_director_n4/top.json @@ -0,0 +1,44359 @@ +{ + "creator": "Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)", + "modules": { + "$__ABC9_DELAY": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000011", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.1-7.10" + }, + "parameter_default_values": { + "DELAY": "00000000000000000000000000000000" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + "$specify$15881": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000000000000", + "T_FALL_MIN": "00000000000000000000000000000000", + "T_FALL_TYP": "00000000000000000000000000000000", + "T_RISE_MAX": "00000000000000000000000000000000", + "T_RISE_MIN": "00000000000000000000000000000000", + "T_RISE_TYP": "00000000000000000000000000000000" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:5.5-5.22" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 3 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + } + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.29-2.30" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + 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"DONTCARE", + "CH0_PCS_DET_TIME_SEL": "DONTCARE", + "CH0_PDEN_SEL": "DONTCARE", + "CH0_PRBS_ENABLE": "DONTCARE", + "CH0_PRBS_LOCK": "DONTCARE", + "CH0_PRBS_SELECTION": "DONTCARE", + "CH0_PROTOCOL": "DONTCARE", + "CH0_RATE_MODE_RX": "DONTCARE", + "CH0_RATE_MODE_TX": "DONTCARE", + "CH0_RCV_DCC_EN": "DONTCARE", + "CH0_REG_BAND_OFFSET": "DONTCARE", + "CH0_REG_BAND_SEL": "DONTCARE", + "CH0_REG_IDAC_EN": "DONTCARE", + "CH0_REG_IDAC_SEL": "DONTCARE", + "CH0_REQ_EN": "DONTCARE", + "CH0_REQ_LVL_SET": "DONTCARE", + "CH0_RIO_MODE": "DONTCARE", + "CH0_RLOS_SEL": "DONTCARE", + "CH0_RPWDNB": "DONTCARE", + "CH0_RTERM_RX": "DONTCARE", + "CH0_RTERM_TX": "DONTCARE", + "CH0_RXIN_CM": "DONTCARE", + "CH0_RXTERM_CM": "DONTCARE", + "CH0_RX_DCO_CK_DIV": "DONTCARE", + "CH0_RX_DIV11_SEL": "DONTCARE", + "CH0_RX_GEAR_BYPASS": "DONTCARE", + "CH0_RX_GEAR_MODE": "DONTCARE", + "CH0_RX_LOS_CEQ": "DONTCARE", + "CH0_RX_LOS_EN": "DONTCARE", + "CH0_RX_LOS_HYST_EN": "DONTCARE", + "CH0_RX_LOS_LVL": "DONTCARE", + "CH0_RX_RATE_SEL": "DONTCARE", + "CH0_RX_SB_BYPASS": "DONTCARE", + "CH0_SB_BYPASS": "DONTCARE", + "CH0_SEL_SD_RX_CLK": "DONTCARE", + "CH0_TDRV_DAT_SEL": "DONTCARE", + "CH0_TDRV_POST_EN": "DONTCARE", + "CH0_TDRV_PRE_EN": "DONTCARE", + "CH0_TDRV_SLICE0_CUR": "DONTCARE", + "CH0_TDRV_SLICE0_SEL": "DONTCARE", + "CH0_TDRV_SLICE1_CUR": "DONTCARE", + "CH0_TDRV_SLICE1_SEL": "DONTCARE", + "CH0_TDRV_SLICE2_CUR": "DONTCARE", + "CH0_TDRV_SLICE2_SEL": "DONTCARE", + "CH0_TDRV_SLICE3_CUR": "DONTCARE", + "CH0_TDRV_SLICE3_SEL": "DONTCARE", + "CH0_TDRV_SLICE4_CUR": "DONTCARE", + "CH0_TDRV_SLICE4_SEL": "DONTCARE", + "CH0_TDRV_SLICE5_CUR": "DONTCARE", + "CH0_TDRV_SLICE5_SEL": "DONTCARE", + "CH0_TPWDNB": "DONTCARE", + "CH0_TXAMPLITUDE": "DONTCARE", + "CH0_TXDEPOST": "DONTCARE", + "CH0_TXDEPRE": "DONTCARE", + "CH0_TX_CM_SEL": "DONTCARE", + "CH0_TX_DIV11_SEL": "DONTCARE", + "CH0_TX_GEAR_BYPASS": "DONTCARE", + "CH0_TX_GEAR_MODE": "DONTCARE", + "CH0_TX_POST_SIGN": "DONTCARE", + "CH0_TX_PRE_SIGN": "DONTCARE", + "CH0_UC_MODE": "DONTCARE", + "CH0_UDF_COMMA_A": "DONTCARE", + "CH0_UDF_COMMA_B": "DONTCARE", + "CH0_UDF_COMMA_MASK": "DONTCARE", + "CH0_WA_BYPASS": "DONTCARE", + "CH0_WA_MODE": "DONTCARE", + "CH1_AUTO_CALIB_EN": "DONTCARE", + "CH1_AUTO_FACQ_EN": "DONTCARE", + "CH1_BAND_THRESHOLD": "DONTCARE", + "CH1_CALIB_CK_MODE": "DONTCARE", + "CH1_CC_MATCH_1": "DONTCARE", + "CH1_CC_MATCH_2": "DONTCARE", + "CH1_CC_MATCH_3": "DONTCARE", + "CH1_CC_MATCH_4": "DONTCARE", + "CH1_CDR_CNT4SEL": "DONTCARE", + "CH1_CDR_CNT8SEL": "DONTCARE", + "CH1_CDR_MAX_RATE": "DONTCARE", + "CH1_CTC_BYPASS": "DONTCARE", + "CH1_DCOATDCFG": "DONTCARE", + "CH1_DCOATDDLY": "DONTCARE", + "CH1_DCOBYPSATD": "DONTCARE", + "CH1_DCOCALDIV": "DONTCARE", + "CH1_DCOCTLGI": "DONTCARE", + "CH1_DCODISBDAVOID": "DONTCARE", + "CH1_DCOFLTDAC": "DONTCARE", + "CH1_DCOFTNRG": "DONTCARE", + "CH1_DCOIOSTUNE": "DONTCARE", + "CH1_DCOITUNE": "DONTCARE", + "CH1_DCOITUNE4LSB": "DONTCARE", + "CH1_DCOIUPDNX2": "DONTCARE", + "CH1_DCONUOFLSB": "DONTCARE", + "CH1_DCOSCALEI": "DONTCARE", + "CH1_DCOSTARTVAL": "DONTCARE", + "CH1_DCOSTEP": "DONTCARE", + "CH1_DEC_BYPASS": "DONTCARE", + "CH1_ENABLE_CG_ALIGN": "DONTCARE", + "CH1_ENC_BYPASS": "DONTCARE", + "CH1_FF_RX_F_CLK_DIS": "DONTCARE", + "CH1_FF_RX_H_CLK_EN": "DONTCARE", + "CH1_FF_TX_F_CLK_DIS": "DONTCARE", + "CH1_FF_TX_H_CLK_EN": "DONTCARE", + "CH1_GE_AN_ENABLE": "DONTCARE", + "CH1_INVERT_RX": "DONTCARE", + "CH1_INVERT_TX": "DONTCARE", + "CH1_LDR_CORE2TX_SEL": "DONTCARE", + "CH1_LDR_RX2CORE_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_TRIM": "DONTCARE", + "CH1_LSM_DISABLE": "DONTCARE", + "CH1_MATCH_2_ENABLE": "DONTCARE", + "CH1_MATCH_4_ENABLE": "DONTCARE", + "CH1_MIN_IPG_CNT": "DONTCARE", + "CH1_PCIE_EI_EN": "DONTCARE", + "CH1_PCIE_MODE": "DONTCARE", + "CH1_PCS_DET_TIME_SEL": "DONTCARE", + "CH1_PDEN_SEL": "DONTCARE", + "CH1_PRBS_ENABLE": "DONTCARE", + "CH1_PRBS_LOCK": "DONTCARE", + "CH1_PRBS_SELECTION": "DONTCARE", + "CH1_PROTOCOL": "DONTCARE", + "CH1_RATE_MODE_RX": "DONTCARE", + "CH1_RATE_MODE_TX": "DONTCARE", + "CH1_RCV_DCC_EN": "DONTCARE", + "CH1_REG_BAND_OFFSET": "DONTCARE", + "CH1_REG_BAND_SEL": "DONTCARE", + "CH1_REG_IDAC_EN": "DONTCARE", + "CH1_REG_IDAC_SEL": "DONTCARE", + "CH1_REQ_EN": "DONTCARE", + "CH1_REQ_LVL_SET": "DONTCARE", + "CH1_RIO_MODE": "DONTCARE", + "CH1_RLOS_SEL": "DONTCARE", + "CH1_RPWDNB": "DONTCARE", + "CH1_RTERM_RX": "DONTCARE", + "CH1_RTERM_TX": "DONTCARE", + "CH1_RXIN_CM": "DONTCARE", + "CH1_RXTERM_CM": "DONTCARE", + "CH1_RX_DCO_CK_DIV": "DONTCARE", + "CH1_RX_DIV11_SEL": "DONTCARE", + "CH1_RX_GEAR_BYPASS": "DONTCARE", + "CH1_RX_GEAR_MODE": "DONTCARE", + "CH1_RX_LOS_CEQ": "DONTCARE", + "CH1_RX_LOS_EN": "DONTCARE", + "CH1_RX_LOS_HYST_EN": "DONTCARE", + "CH1_RX_LOS_LVL": "DONTCARE", + "CH1_RX_RATE_SEL": "DONTCARE", + "CH1_RX_SB_BYPASS": "DONTCARE", + "CH1_SB_BYPASS": "DONTCARE", + "CH1_SEL_SD_RX_CLK": "DONTCARE", + "CH1_TDRV_DAT_SEL": "DONTCARE", + "CH1_TDRV_POST_EN": "DONTCARE", + "CH1_TDRV_PRE_EN": "DONTCARE", + "CH1_TDRV_SLICE0_CUR": "DONTCARE", + "CH1_TDRV_SLICE0_SEL": "DONTCARE", + "CH1_TDRV_SLICE1_CUR": "DONTCARE", + "CH1_TDRV_SLICE1_SEL": "DONTCARE", + "CH1_TDRV_SLICE2_CUR": "DONTCARE", + "CH1_TDRV_SLICE2_SEL": "DONTCARE", + "CH1_TDRV_SLICE3_CUR": "DONTCARE", + "CH1_TDRV_SLICE3_SEL": "DONTCARE", + "CH1_TDRV_SLICE4_CUR": "DONTCARE", + "CH1_TDRV_SLICE4_SEL": "DONTCARE", + "CH1_TDRV_SLICE5_CUR": "DONTCARE", + "CH1_TDRV_SLICE5_SEL": "DONTCARE", + "CH1_TPWDNB": "DONTCARE", + "CH1_TXAMPLITUDE": "DONTCARE", + "CH1_TXDEPOST": "DONTCARE", + "CH1_TXDEPRE": "DONTCARE", + "CH1_TX_CM_SEL": "DONTCARE", + "CH1_TX_DIV11_SEL": "DONTCARE", + "CH1_TX_GEAR_BYPASS": "DONTCARE", + "CH1_TX_GEAR_MODE": "DONTCARE", + "CH1_TX_POST_SIGN": "DONTCARE", + "CH1_TX_PRE_SIGN": "DONTCARE", + "CH1_UC_MODE": "DONTCARE", + "CH1_UDF_COMMA_A": "DONTCARE", + "CH1_UDF_COMMA_B": "DONTCARE", + "CH1_UDF_COMMA_MASK": "DONTCARE", + "CH1_WA_BYPASS": "DONTCARE", + "CH1_WA_MODE": "DONTCARE", + "D_BITCLK_FROM_ND_EN": "DONTCARE", + "D_BITCLK_LOCAL_EN": "DONTCARE", + "D_BITCLK_ND_EN": "DONTCARE", + "D_BUS8BIT_SEL": "DONTCARE", + "D_CDR_LOL_SET": "DONTCARE", + "D_CMUSETBIASI": "DONTCARE", + "D_CMUSETI4CPP": "DONTCARE", + "D_CMUSETI4CPZ": "DONTCARE", + "D_CMUSETI4VCO": "DONTCARE", + "D_CMUSETICP4P": "DONTCARE", + "D_CMUSETICP4Z": "DONTCARE", + "D_CMUSETINITVCT": "DONTCARE", + "D_CMUSETISCL4VCO": "DONTCARE", + "D_CMUSETP1GM": "DONTCARE", + "D_CMUSETP2AGM": "DONTCARE", + "D_CMUSETZGM": "DONTCARE", + "D_DCO_CALIB_TIME_SEL": "DONTCARE", + "D_HIGH_MARK": "DONTCARE", + "D_IB_PWDNB": "DONTCARE", + "D_ISETLOS": "DONTCARE", + "D_LOW_MARK": "DONTCARE", + "D_MACROPDB": "DONTCARE", + "D_PD_ISET": "DONTCARE", + "D_PLL_LOL_SET": "DONTCARE", + "D_REFCK_MODE": "DONTCARE", + "D_REQ_ISET": "DONTCARE", + "D_RG_EN": "DONTCARE", + "D_RG_SET": "DONTCARE", + "D_SETICONST_AUX": "DONTCARE", + "D_SETICONST_CH": "DONTCARE", + "D_SETIRPOLY_AUX": "DONTCARE", + "D_SETIRPOLY_CH": "DONTCARE", + "D_SETPLLRC": "DONTCARE", + "D_SYNC_LOCAL_EN": "DONTCARE", + "D_SYNC_ND_EN": "DONTCARE", + "D_TXPLL_PWDNB": "DONTCARE", + "D_TX_MAX_RATE": "DONTCARE", + "D_TX_VCO_CK_DIV": "DONTCARE", + "D_XGE_MODE": "DONTCARE" + }, + "ports": { + "CH0_HDINP": { + "direction": "input", + "bits": [ 2 ] + }, + "CH1_HDINP": { + "direction": "input", + "bits": [ 3 ] + }, + "CH0_HDINN": { + "direction": "input", + "bits": [ 4 ] + }, + "CH1_HDINN": { + "direction": "input", + "bits": [ 5 ] + }, + "D_TXBIT_CLKP_FROM_ND": { + "direction": "input", + "bits": [ 6 ] + }, + "D_TXBIT_CLKN_FROM_ND": { + "direction": "input", + "bits": [ 7 ] + }, + "D_SYNC_ND": { + "direction": "input", + "bits": [ 8 ] + }, + "D_TXPLL_LOL_FROM_ND": { + "direction": "input", + "bits": [ 9 ] + }, + "CH0_RX_REFCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "CH1_RX_REFCLK": { + "direction": "input", + "bits": [ 11 ] + }, + "CH0_FF_RXI_CLK": { + "direction": "input", + "bits": [ 12 ] + }, + "CH1_FF_RXI_CLK": { + "direction": "input", + "bits": [ 13 ] + }, + "CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + 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b/hardware/v2/synthesis/neural_director_n4/yosys.log @@ -0,0 +1,1978 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) + +-- Parsing `hardware/v2/rtl/neural_director.v' using frontend ` -vlog2k' -- + +1. Executing Verilog-2005 frontend: hardware/v2/rtl/neural_director.v +Parsing Verilog input from `hardware/v2/rtl/neural_director.v' to AST representation. +Storing AST representation for module `$abstract\neural_director'. +Successfully finished Verilog frontend. + +-- Running command `synth_ecp5 -json hardware/v2/synthesis/neural_director_n4/top.json -top neural_director' -- + +2. Executing SYNTH_LATTICE pass. + +2.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +2.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +2.3. Executing HIERARCHY pass (managing design hierarchy). + +2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\neural_director'. +Generating RTLIL representation for module `\neural_director'. + +2.4.1. Analyzing design hierarchy.. +Top module: \neural_director + +2.4.2. Analyzing design hierarchy.. +Top module: \neural_director +Removing unused module `$abstract\neural_director'. +Removed 1 unused modules. + +2.5. Executing PROC pass (convert processes to netlists). + +2.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +2.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:123$252 in module neural_director. +Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:116$245 in module neural_director. +Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:102$244 in module neural_director. +Removed a total of 0 dead cases. + +2.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 2 redundant assignments. +Promoted 37 assignments to connections. + +2.5.4. Executing PROC_INIT pass (extract init attributes). + +2.5.5. Executing PROC_ARST pass (detect async resets in processes). + +2.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +2.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + 1/61: $2$lookahead\slot_busy$251[3:0]$340 + 2/61: $2$lookahead\slot_result_addr$250[91:0]$339 + 3/61: $2$lookahead\slot_n_tiles$249[63:0]$338 + 4/61: $2$lookahead\slot_w_base$248[91:0]$337 + 5/61: $2$lookahead\slot_x_base$247[91:0]$336 + 6/61: $2$lookahead\slot_job_start$246[3:0]$335 + 7/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:195$233[1:0]$334 + 8/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:194$232[31:0]$333 + 9/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:193$231[31:0]$332 + 10/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:192$230[31:0]$331 + 11/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:191$229[31:0]$330 + 12/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:190$228[1:0]$329 + 13/61: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_EN[15:0]$322 + 14/61: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_DATA[15:0]$321 + 15/61: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_ADDR[2:0]$320 + 16/61: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$319 + 17/61: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_DATA[22:0]$318 + 18/61: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_ADDR[2:0]$317 + 19/61: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$316 + 20/61: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_DATA[15:0]$315 + 21/61: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_ADDR[2:0]$314 + 22/61: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$313 + 23/61: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_DATA[22:0]$312 + 24/61: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_ADDR[2:0]$311 + 25/61: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$310 + 26/61: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_DATA[22:0]$309 + 27/61: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_ADDR[2:0]$308 + 28/61: $0\job_out_done[0:0] + 29/61: $1$lookahead\slot_result_addr$250[91:0]$305 + 30/61: $1$lookahead\slot_n_tiles$249[63:0]$304 + 31/61: $1$lookahead\slot_w_base$248[91:0]$303 + 32/61: $1$lookahead\slot_x_base$247[91:0]$302 + 33/61: $1$lookahead\slot_job_start$246[3:0]$301 + 34/61: $1$lookahead\slot_busy$251[3:0]$306 + 35/61: $0\q_count[3:0] + 36/61: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_EN[15:0]$300 + 37/61: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_DATA[15:0]$299 + 38/61: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_ADDR[2:0]$298 + 39/61: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$297 + 40/61: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_DATA[22:0]$296 + 41/61: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_ADDR[2:0]$295 + 42/61: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$294 + 43/61: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_DATA[15:0]$293 + 44/61: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_ADDR[2:0]$292 + 45/61: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$291 + 46/61: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_DATA[22:0]$290 + 47/61: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_ADDR[2:0]$289 + 48/61: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$288 + 49/61: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_DATA[22:0]$287 + 50/61: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_ADDR[2:0]$286 + 51/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:195$233[1:0]$285 + 52/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:194$232[31:0]$284 + 53/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:193$231[31:0]$283 + 54/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:192$230[31:0]$282 + 55/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:191$229[31:0]$281 + 56/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:190$228[1:0]$280 + 57/61: $0\q_tail[2:0] + 58/61: $0\q_head[2:0] + 59/61: $0\dir_error[0:0] + 60/61: $0\dir_state[3:0] + 61/61: $0\job_out_slot[1:0] +Creating decoders for process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$245'. + 1/4: $4\done_slot_idx[1:0] + 2/4: $3\done_slot_idx[1:0] + 3/4: $2\done_slot_idx[1:0] + 4/4: $1\done_slot_idx[1:0] +Creating decoders for process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$244'. + 1/4: $4\free_slot_idx[1:0] + 2/4: $3\free_slot_idx[1:0] + 3/4: $2\free_slot_idx[1:0] + 4/4: $1\free_slot_idx[1:0] + +2.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\neural_director.\done_slot_idx' from process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$245'. +No latch inferred for signal `\neural_director.\di' from process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$245'. +No latch inferred for signal `\neural_director.\free_slot_idx' from process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$244'. +No latch inferred for signal `\neural_director.\fi' from process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$244'. + +2.5.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\neural_director.\slot_job_start' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$730' with positive edge clock. +Creating register for signal `\neural_director.\slot_x_base' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$731' with positive edge clock. +Creating register for signal `\neural_director.\slot_w_base' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$732' with positive edge clock. +Creating register for signal `\neural_director.\slot_n_tiles' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$733' with positive edge clock. +Creating register for signal `\neural_director.\slot_result_addr' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$734' with positive edge clock. +Creating register for signal `\neural_director.\job_out_done' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$735' with positive edge clock. +Creating register for signal `\neural_director.\job_out_slot' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$736' with positive edge clock. +Creating register for signal `\neural_director.\dir_state' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$737' with positive edge clock. +Creating register for signal `\neural_director.\dir_error' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$738' with positive edge clock. +Creating register for signal `\neural_director.\q_head' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$739' with positive edge clock. +Creating register for signal `\neural_director.\q_tail' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$740' with positive edge clock. +Creating register for signal `\neural_director.\q_count' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$741' with positive edge clock. +Creating register for signal `\neural_director.\slot_busy' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$742' with positive edge clock. +Creating register for signal `\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:190$228' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$743' with positive edge clock. +Creating register for signal `\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:191$229' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$744' with positive edge clock. +Creating register for signal `\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:192$230' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$745' with positive edge clock. +Creating register for signal `\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:193$231' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$746' with positive edge clock. +Creating register for signal `\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:194$232' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$747' with positive edge clock. +Creating register for signal `\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:195$233' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$748' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_ADDR' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$749' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_DATA' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$750' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$751' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_ADDR' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$752' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_DATA' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$753' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$754' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_ADDR' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$755' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_DATA' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$756' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$757' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_ADDR' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$758' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_DATA' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$759' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$760' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_ADDR' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$761' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_DATA' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$762' with positive edge clock. +Creating register for signal `\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_EN' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$763' with positive edge clock. +Creating register for signal `\neural_director.$lookahead\slot_job_start$246' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$764' with positive edge clock. +Creating register for signal `\neural_director.$lookahead\slot_x_base$247' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$765' with positive edge clock. +Creating register for signal `\neural_director.$lookahead\slot_w_base$248' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$766' with positive edge clock. +Creating register for signal `\neural_director.$lookahead\slot_n_tiles$249' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$767' with positive edge clock. +Creating register for signal `\neural_director.$lookahead\slot_result_addr$250' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$768' with positive edge clock. +Creating register for signal `\neural_director.$lookahead\slot_busy$251' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. + created $dff cell `$procdff$769' with positive edge clock. + +2.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +2.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 6 empty switches in `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. +Removing empty process `neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'. +Found and cleaned up 4 empty switches in `\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$245'. +Removing empty process `neural_director.$proc$hardware/v2/rtl/neural_director.v:116$245'. +Found and cleaned up 4 empty switches in `\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$244'. +Removing empty process `neural_director.$proc$hardware/v2/rtl/neural_director.v:102$244'. +Cleaned up 14 empty switches. + +2.5.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + + +2.6. Executing CHECK pass (checking for obvious problems). +Checking module neural_director... +Found and reported 0 problems. + +2.7. Executing FLATTEN pass (flatten design). + +2.8. Executing TRIBUF pass. + +2.9. Executing DEMINOUT pass (demote inout ports to input or output). + +2.10. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + + +2.11. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. +Removed 64 unused cells and 271 unused wires. + + +2.12. Executing CHECK pass (checking for obvious problems). +Checking module neural_director... +Found and reported 0 problems. + +2.13. Executing OPT pass (performing simple optimizations). + +2.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 174 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 156 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 152 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 150 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 148 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. + +Removed a total of 26 cells. + +2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $procmux$579. + dead port 1/2 on $mux $procmux$573. + dead port 1/2 on $mux $procmux$567. + dead port 1/2 on $mux $procmux$561. + dead port 1/2 on $mux $procmux$555. + dead port 1/2 on $mux $procmux$549. + dead port 1/2 on $mux $procmux$543. + dead port 1/2 on $mux $procmux$537. + dead port 1/2 on $mux $procmux$531. + dead port 1/2 on $mux $procmux$525. + dead port 1/2 on $mux $procmux$519. + dead port 1/2 on $mux $procmux$513. + dead port 1/2 on $mux $procmux$447. + dead port 1/2 on $mux $procmux$440. + dead port 1/2 on $mux $procmux$433. + dead port 1/2 on $mux $procmux$426. + dead port 1/2 on $mux $procmux$419. + dead port 1/2 on $mux $procmux$412. +Removed 18 multiplexer ports. + + +2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \neural_director. + Consolidated identical input bits for $mux cell $procmux$528: + Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$procmux$528_Y + New ports: A=1'0, B=1'1, Y=$procmux$528_Y [0] + New connections: $procmux$528_Y [15:1] = { $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] } + Consolidated identical input bits for $mux cell $procmux$564: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$procmux$564_Y + New ports: A=1'0, B=1'1, Y=$procmux$564_Y [0] + New connections: $procmux$564_Y [22:1] = { $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] } + Consolidated identical input bits for $mux cell $procmux$510: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$procmux$510_Y + New ports: A=1'0, B=1'1, Y=$procmux$510_Y [0] + New connections: $procmux$510_Y [22:1] = { $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] } + New ctrl vector for $pmux cell $procmux$691: { $procmux$692_CMP $auto$opt_reduce.cc:137:opt_pmux$776 $procmux$696_CMP } + Consolidated identical input bits for $mux cell $procmux$546: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$procmux$546_Y + New ports: A=1'0, B=1'1, Y=$procmux$546_Y [0] + New connections: $procmux$546_Y [22:1] = { $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] } + Optimizing cells in module \neural_director. + Consolidated identical input bits for $mux cell $procmux$648: + Old ports: A=$2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$310, B=23'00000000000000000000000, Y=$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 + New ports: A=$procmux$564_Y [0], B=1'0, Y=$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] + New connections: $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [22:1] = { $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] } + Consolidated identical input bits for $mux cell $procmux$639: + Old ports: A=$2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$313, B=23'00000000000000000000000, Y=$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 + New ports: A=$procmux$546_Y [0], B=1'0, Y=$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] + New connections: $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [22:1] = { $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] } + Consolidated identical input bits for $mux cell $procmux$630: + Old ports: A=$2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$316, B=16'0000000000000000, Y=$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 + New ports: A=$procmux$528_Y [0], B=1'0, Y=$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] + New connections: $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [15:1] = { $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] } + Consolidated identical input bits for $mux cell $procmux$621: + Old ports: A=$2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$319, B=23'00000000000000000000000, Y=$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 + New ports: A=$procmux$510_Y [0], B=1'0, Y=$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] + New connections: $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [22:1] = { $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] } + Optimizing cells in module \neural_director. +Performed a total of 9 changes. + +2.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 131 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 125 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 119 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. + +Removed a total of 12 cells. + +2.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. +Removed 0 unused cells and 56 unused wires. + + +2.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \neural_director. +Performed a total of 0 changes. + +2.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 119 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. + +2.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.13.16. Finished fast OPT passes. (There is nothing left to do.) + +2.14. Executing FSM pass (extract and optimize FSM). + +2.14.1. Executing FSM_DETECT pass (finding FSMs in design). +Not marking neural_director.dir_state as FSM state register: + Register is connected to module port. + Users of register don't seem to benefit from recoding. +Not marking neural_director.job_out_slot as FSM state register: + Register is connected to module port. + Users of register don't seem to benefit from recoding. + +2.14.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +2.14.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +2.14.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. + +2.14.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +2.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +2.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +2.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +2.15. Executing OPT pass (performing simple optimizations). + +2.15.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.15.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 119 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \neural_director. +Performed a total of 0 changes. + +2.15.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 119 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.15.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $procdff$739 ($dff) from module neural_director (D = $procmux$682_Y, Q = \q_head, rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$777 ($sdff) from module neural_director (D = $ternary$hardware/v2/rtl/neural_director.v:196$399_Y, Q = \q_head). +Adding EN signal on $procdff$738 ($dff) from module neural_director (D = 1'0, Q = \dir_error). +Adding SRST signal on $procdff$737 ($dff) from module neural_director (D = $procmux$691_Y, Q = \dir_state, rval = 4'0000). +Adding EN signal on $auto$ff.cc:337:slice$780 ($sdff) from module neural_director (D = $procmux$691_Y, Q = \dir_state). +Adding SRST signal on $procdff$731 ($dff) from module neural_director (D = $2$lookahead\slot_x_base$247[91:0]$336, Q = \slot_x_base, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$788 ($sdff) from module neural_director (D = $or$hardware/v2/rtl/neural_director.v:191$359_Y, Q = \slot_x_base). +Adding SRST signal on $procdff$740 ($dff) from module neural_director (D = $procmux$675_Y, Q = \q_tail, rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$790 ($sdff) from module neural_director (D = $ternary$hardware/v2/rtl/neural_director.v:152$325_Y, Q = \q_tail). +Adding SRST signal on $procdff$732 ($dff) from module neural_director (D = $2$lookahead\slot_w_base$248[91:0]$337, Q = \slot_w_base, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$792 ($sdff) from module neural_director (D = $or$hardware/v2/rtl/neural_director.v:192$369_Y, Q = \slot_w_base). +Adding SRST signal on $procdff$733 ($dff) from module neural_director (D = $2$lookahead\slot_n_tiles$249[63:0]$338, Q = \slot_n_tiles, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$794 ($sdff) from module neural_director (D = $or$hardware/v2/rtl/neural_director.v:193$379_Y, Q = \slot_n_tiles). +Adding SRST signal on $procdff$736 ($dff) from module neural_director (D = $procmux$701_Y, Q = \job_out_slot, rval = 2'00). +Adding EN signal on $auto$ff.cc:337:slice$796 ($sdff) from module neural_director (D = \done_slot_idx, Q = \job_out_slot). +Adding SRST signal on $procdff$735 ($dff) from module neural_director (D = $procmux$581_Y, Q = \job_out_done, rval = 1'0). +Adding SRST signal on $procdff$734 ($dff) from module neural_director (D = $2$lookahead\slot_result_addr$250[91:0]$339, Q = \slot_result_addr, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$799 ($sdff) from module neural_director (D = $or$hardware/v2/rtl/neural_director.v:194$389_Y, Q = \slot_result_addr). +Adding SRST signal on $procdff$730 ($dff) from module neural_director (D = $or$hardware/v2/rtl/neural_director.v:190$349_Y, Q = \slot_job_start, rval = 4'0000). +Adding SRST signal on $procdff$742 ($dff) from module neural_director (D = $2$lookahead\slot_busy$251[3:0]$340, Q = \slot_busy, rval = 4'0000). +Adding SRST signal on $procdff$741 ($dff) from module neural_director (D = $procmux$605_Y, Q = \q_count, rval = 4'0000). +Adding EN signal on $auto$ff.cc:337:slice$807 ($sdff) from module neural_director (D = $procmux$605_Y, Q = \q_count). +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$779 ($dffe) from module neural_director. + +2.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. +Removed 21 unused cells and 21 unused wires. + + +2.15.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + + +2.15.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \neural_director. +Performed a total of 0 changes. + +2.15.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 103 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.15.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. + +2.15.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.15.16. Finished fast OPT passes. (There is nothing left to do.) + +2.16. Executing WREDUCE pass (reducing word size of cells). +Removed top 26 bits (of 33) from port A of cell neural_director.$neg$hardware/v2/rtl/neural_director.v:193$377 ($neg). +Converting cell neural_director.$neg$hardware/v2/rtl/neural_director.v:193$377 ($neg) from signed to unsigned. +Removed top 1 bits (of 7) from port A of cell neural_director.$neg$hardware/v2/rtl/neural_director.v:193$377 ($neg). +Removed top 27 bits (of 32) from port B of cell neural_director.$mul$hardware/v2/rtl/neural_director.v:194$380 ($mul). +Removed top 25 bits (of 32) from port Y of cell neural_director.$mul$hardware/v2/rtl/neural_director.v:194$380 ($mul). +Removed top 25 bits (of 33) from port A of cell neural_director.$neg$hardware/v2/rtl/neural_director.v:194$387 ($neg). +Converting cell neural_director.$neg$hardware/v2/rtl/neural_director.v:194$387 ($neg) from signed to unsigned. +Removed top 1 bits (of 8) from port A of cell neural_director.$neg$hardware/v2/rtl/neural_director.v:194$387 ($neg). +Converting cell neural_director.$neg$hardware/v2/rtl/neural_director.v:195$394 ($neg) from signed to unsigned. +Removed top 1 bits (of 3) from port A of cell neural_director.$neg$hardware/v2/rtl/neural_director.v:195$394 ($neg). +Removed top 1 bits (of 2) from port B of cell neural_director.$procmux$606_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell neural_director.$procmux$692_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell neural_director.$procmux$693_CMP0 ($eq). +Removed top 3 bits (of 4) from port B of cell neural_director.$procmux$696_CMP0 ($eq). +Removed top 25 bits (of 32) from wire neural_director.$add$hardware/v2/rtl/neural_director.v:191$351_Y. + +2.17. Executing PEEPOPT pass (run peephole optimizers). +left shiftmul pattern in neural_director: shift=$shift$hardware/v2/rtl/neural_director.v:194$388, mul=$mul$hardware/v2/rtl/neural_director.v:194$380 +left shiftmul pattern in neural_director: shift=$shift$hardware/v2/rtl/neural_director.v:194$383, mul=$mul$hardware/v2/rtl/neural_director.v:194$380 +left shiftmul pattern in neural_director: shift=$shift$hardware/v2/rtl/neural_director.v:192$368, mul=$mul$hardware/v2/rtl/neural_director.v:194$380 +left shiftmul pattern in neural_director: shift=$shift$hardware/v2/rtl/neural_director.v:191$358, mul=$mul$hardware/v2/rtl/neural_director.v:194$380 + +2.18. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. +Removed 2 unused cells and 3 unused wires. + + +2.19. Executing SHARE pass (SAT-based resource sharing). + +2.20. Executing TECHMAP pass (map to technology primitives). + +2.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +2.20.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.21. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.22. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. + +2.23. Executing TECHMAP pass (map to technology primitives). + +2.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +2.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.24. Executing TECHMAP pass (map to technology primitives). + +2.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +2.24.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.25. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module neural_director: + creating $macc model for $auto$peepopt_pm.h:1040:block_9$817 ($neg). + creating $macc model for $auto$peepopt_pm.h:1040:block_9$814 ($neg). + creating $macc model for $sub$hardware/v2/rtl/neural_director.v:214$406 ($sub). + creating $macc model for $add$hardware/v2/rtl/neural_director.v:213$405 ($add). + creating $macc model for $add$hardware/v2/rtl/neural_director.v:196$398 ($add). + creating $macc model for $neg$hardware/v2/rtl/neural_director.v:195$394 ($neg). + creating $macc model for $auto$peepopt_pm.h:1040:block_9$820 ($neg). + creating $macc model for $auto$peepopt_pm.h:1040:block_9$823 ($neg). + creating $macc model for $neg$hardware/v2/rtl/neural_director.v:193$377 ($neg). + creating $macc model for $add$hardware/v2/rtl/neural_director.v:152$324 ($add). + creating $alu model for $macc $add$hardware/v2/rtl/neural_director.v:152$324. + creating $alu model for $macc $neg$hardware/v2/rtl/neural_director.v:193$377. + creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$823. + creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$820. + creating $alu model for $macc $neg$hardware/v2/rtl/neural_director.v:195$394. + creating $alu model for $macc $add$hardware/v2/rtl/neural_director.v:196$398. + creating $alu model for $macc $add$hardware/v2/rtl/neural_director.v:213$405. + creating $alu model for $macc $sub$hardware/v2/rtl/neural_director.v:214$406. + creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$814. + creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$817. + creating $alu cell for $sub$hardware/v2/rtl/neural_director.v:214$406: $auto$alumacc.cc:548:replace_alu$825 + creating $alu cell for $add$hardware/v2/rtl/neural_director.v:213$405: $auto$alumacc.cc:548:replace_alu$828 + creating $alu cell for $add$hardware/v2/rtl/neural_director.v:196$398: $auto$alumacc.cc:548:replace_alu$831 + creating $alu cell for $neg$hardware/v2/rtl/neural_director.v:195$394: $auto$alumacc.cc:548:replace_alu$834 + creating $alu cell for $auto$peepopt_pm.h:1040:block_9$817: $auto$alumacc.cc:548:replace_alu$837 + creating $alu cell for $auto$peepopt_pm.h:1040:block_9$814: $auto$alumacc.cc:548:replace_alu$840 + creating $alu cell for $auto$peepopt_pm.h:1040:block_9$820: $auto$alumacc.cc:548:replace_alu$843 + creating $alu cell for $auto$peepopt_pm.h:1040:block_9$823: $auto$alumacc.cc:548:replace_alu$846 + creating $alu cell for $neg$hardware/v2/rtl/neural_director.v:193$377: $auto$alumacc.cc:548:replace_alu$849 + creating $alu cell for $add$hardware/v2/rtl/neural_director.v:152$324: $auto$alumacc.cc:548:replace_alu$852 + created 10 $alu and 0 $macc cells. + +2.26. Executing OPT pass (performing simple optimizations). + +2.26.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.26.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 105 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 102 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. + +Removed a total of 3 cells. + +2.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \neural_director. +Performed a total of 0 changes. + +2.26.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 102 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.26.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.26.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. +Removed 0 unused cells and 9 unused wires. + + +2.26.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.26.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.26.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.26.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \neural_director. +Performed a total of 0 changes. + +2.26.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 102 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.26.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.26.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. + +2.26.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.26.16. Finished fast OPT passes. (There is nothing left to do.) + +2.27. Executing MEMORY pass. + +2.27.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +2.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +2.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing neural_director.q_result_addr write port 0. + Analyzing neural_director.q_n_tiles write port 0. + Analyzing neural_director.q_w_base write port 0. + Analyzing neural_director.q_x_base write port 0. + +2.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +2.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\q_result_addr'[0] in module `\neural_director': no output FF found. +Checking read port `\q_n_tiles'[0] in module `\neural_director': no output FF found. +Checking read port `\q_w_base'[0] in module `\neural_director': no output FF found. +Checking read port `\q_x_base'[0] in module `\neural_director': no output FF found. +Checking read port address `\q_result_addr'[0] in module `\neural_director': merged address FF to cell. +Checking read port address `\q_n_tiles'[0] in module `\neural_director': merged address FF to cell. +Checking read port address `\q_w_base'[0] in module `\neural_director': merged address FF to cell. +Checking read port address `\q_x_base'[0] in module `\neural_director': merged address FF to cell. + +2.27.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. + +2.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +2.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +2.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. + +2.27.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +2.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. + +2.29. Executing MEMORY_LIBMAP pass (mapping memories to cells). +mapping memory neural_director.q_result_addr via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of neural_director.q_result_addr: $\q_result_addr$rdreg[0] +mapping memory neural_director.q_n_tiles via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of neural_director.q_n_tiles: $\q_n_tiles$rdreg[0] +mapping memory neural_director.q_w_base via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of neural_director.q_w_base: $\q_w_base$rdreg[0] +mapping memory neural_director.q_x_base via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of neural_director.q_x_base: $\q_x_base$rdreg[0] + + +2.30. Executing TECHMAP pass (map to technology primitives). + +2.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +2.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +2.30.3. Continuing TECHMAP pass. +Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. +No more expansions possible. + + +2.31. Executing OPT pass (performing simple optimizations). + +2.31.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + + +2.31.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 115 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 112 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 109 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 106 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. + +Removed a total of 9 cells. + +2.31.3. Executing OPT_DFF pass (perform DFF optimizations). + +2.31.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. +Removed 0 unused cells and 158 unused wires. + + +2.31.5. Finished fast OPT passes. + +2.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +2.33. Executing OPT pass (performing simple optimizations). + +2.33.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.33.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 106 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \neural_director. + Consolidated identical input bits for $pmux cell $procmux$691: + Old ports: A=4'0011, B=8'00010010, Y=$procmux$691_Y + New ports: A=2'11, B=4'0110, Y=$procmux$691_Y [1:0] + New connections: $procmux$691_Y [3:2] = 2'00 + Consolidated identical input bits for $mux cell $procmux$716: + Old ports: A=2'00, B=2'11, Y=$1\done_slot_idx[1:0] + New ports: A=1'0, B=1'1, Y=$1\done_slot_idx[1:0] [0] + New connections: $1\done_slot_idx[1:0] [1] = $1\done_slot_idx[1:0] [0] + Consolidated identical input bits for $mux cell $procmux$728: + Old ports: A=2'00, B=2'11, Y=$1\free_slot_idx[1:0] + New ports: A=1'0, B=1'1, Y=$1\free_slot_idx[1:0] [0] + New connections: $1\free_slot_idx[1:0] [1] = $1\free_slot_idx[1:0] [0] + Optimizing cells in module \neural_director. +Performed a total of 3 changes. + +2.33.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 106 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.33.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $\q_result_addr$rdreg[0] ($dff) from module neural_director (D = $auto$rtlil.cc:3402:Mux$861, Q = $\q_n_tiles$rdreg[0]$q, rval = 3'000). + +2.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. +Removed 1 unused cells and 1 unused wires. + + +2.33.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + + +2.33.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.33.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.33.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \neural_director. +Performed a total of 0 changes. + +2.33.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 103 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.33.13. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$781 ($sdffe) from module neural_director. +Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$781 ($sdffe) from module neural_director. + +2.33.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. +Removed 0 unused cells and 2 unused wires. + + +2.33.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + + +2.33.16. Rerunning OPT passes. (Maybe there is more to do..) + +2.33.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \neural_director.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.33.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \neural_director. +Performed a total of 0 changes. + +2.33.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 103 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.33.20. Executing OPT_DFF pass (perform DFF optimizations). + +2.33.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. + +2.33.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.33.23. Finished fast OPT passes. (There is nothing left to do.) + +2.34. Executing TECHMAP pass (map to technology primitives). + +2.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +2.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +2.34.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $sdffe. +Using extmapper simplemap for cells of type $sdff. +Using extmapper simplemap for cells of type $mux. +Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. +Using template $paramod$3ef274a4ad1e446c08416d1cf6cb5ab03146d407\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$c9d98d2d0793a6d8797b9c088dbedb26a7be7121\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$ef8fb1849064cca7dc908988762d3374786d9fdb\_90_alu for cells of type $alu. +Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. +Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $reduce_bool. +Using extmapper simplemap for cells of type $reduce_or. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $reduce_and. +Using extmapper simplemap for cells of type $ne. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $logic_and. +Using template $paramod$constmap:f30e016643cdb78b03bc6146a268597b7789262d$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $or. +Using template $paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: +Creating constmapped module `$paramod$constmap:5a4bd879cde68fe23882c6a271f9c4bb8714bccb$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx'. + +2.34.30. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:5a4bd879cde68fe23882c6a271f9c4bb8714bccb$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$2186. + dead port 2/2 on $mux $procmux$2192. + dead port 2/2 on $mux $procmux$2198. + dead port 2/2 on $mux $procmux$2204. + dead port 2/2 on $mux $procmux$2210. + dead port 2/2 on $mux $procmux$2216. + dead port 2/2 on $mux $procmux$2222. +Removed 7 multiplexer ports. + + +2.34.31. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:5a4bd879cde68fe23882c6a271f9c4bb8714bccb$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx. + +Removed 0 unused cells and 12 unused wires. +Using template $paramod$constmap:5a4bd879cde68fe23882c6a271f9c4bb8714bccb$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'1 + Constant input on bit 2 of port A: 1'1 + Constant input on bit 3 of port A: 1'1 + Constant input on bit 4 of port A: 1'1 + Constant input on bit 5 of port A: 1'1 + Constant input on bit 6 of port A: 1'1 + Constant input on bit 7 of port A: 1'1 + Constant input on bit 8 of port A: 1'1 + Constant input on bit 9 of port A: 1'1 + Constant input on bit 10 of port A: 1'1 + Constant input on bit 11 of port A: 1'1 + Constant input on bit 12 of port A: 1'1 + Constant input on bit 13 of port A: 1'1 + Constant input on bit 14 of port A: 1'1 + Constant input on bit 15 of port A: 1'1 + Constant input on bit 16 of port A: 1'1 + Constant input on bit 17 of port A: 1'1 + Constant input on bit 18 of port A: 1'1 + Constant input on bit 19 of port A: 1'1 + Constant input on bit 20 of port A: 1'1 + Constant input on bit 21 of port A: 1'1 + Constant input on bit 22 of port A: 1'1 +Creating constmapped module `$paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx'. + +2.34.32. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$1836. + dead port 2/2 on $mux $procmux$1842. + dead port 2/2 on $mux $procmux$1848. + dead port 2/2 on $mux $procmux$1854. + dead port 2/2 on $mux $procmux$1860. + dead port 2/2 on $mux $procmux$1866. + dead port 2/2 on $mux $procmux$1872. +Removed 7 multiplexer ports. + + +2.34.33. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx. + +Removed 0 unused cells and 12 unused wires. +Using template $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx for cells of type $shift. +Using template $paramod$constmap:d6fff7a1d5912e7277ff55b9a478b5115760128b$paramod$64b19f47ed5f126636dbd98d727ec46a7ec08d71\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $pmux. +Using extmapper simplemap for cells of type $xor. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. +Using extmapper simplemap for cells of type $pos. +Using extmapper simplemap for cells of type $logic_or. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. +No more expansions possible. + + +2.35. Executing OPT pass (performing simple optimizations). + +2.35.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + + +2.35.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 4808 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4725 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4673 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4625 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4585 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4561 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4560 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4559 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4558 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4557 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4556 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4555 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4554 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4553 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4552 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4551 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4550 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4549 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4548 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4547 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4546 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4545 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4544 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4543 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4542 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 4541 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. + +Removed a total of 267 cells. + +2.35.3. Executing OPT_DFF pass (perform DFF optimizations). + +2.35.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. +Removed 553 unused cells and 557 unused wires. + + +2.35.5. Finished fast OPT passes. + +2.36. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. + +2.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +2.38. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 3988 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.39. Executing TECHMAP pass (map to technology primitives). + +2.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +2.39.2. Continuing TECHMAP pass. +Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. +Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. +No more expansions possible. + + +2.40. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + + +2.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +2.42. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in neural_director. + +2.43. Executing ATTRMVCP pass (move or copy attributes). + +2.44. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. +Removed 0 unused cells and 2185 unused wires. + + +2.45. Executing CHECK pass (checking for obvious problems). +Checking module neural_director... +Found and reported 0 problems. + +2.46. Executing TECHMAP pass (map to technology primitives). + +2.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +2.46.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.47. Executing ABC9 pass. + +2.47.1. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.2. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.3. Executing PROC pass (convert processes to netlists). + +2.47.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15730'. +Cleaned up 1 empty switch. + +2.47.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. +Removed a total of 0 dead cases. + +2.47.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 22 assignments to connections. + +2.47.3.4. Executing PROC_INIT pass (extract init attributes). + +2.47.3.5. Executing PROC_ARST pass (detect async resets in processes). + +2.47.3.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +2.47.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731'. + 1/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15729_EN[3:0]$15737 + 2/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15729_DATA[3:0]$15736 + 3/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15729_ADDR[3:0]$15735 +Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15730'. + +2.47.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15713_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15714_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15715_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15716_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15717_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15718_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15719_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15720_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15721_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15722_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15723_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15724_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15725_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15726_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15727_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15728_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15730'. + +2.47.3.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15729_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731'. + created $dff cell `$procdff$15781' with positive edge clock. +Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15729_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731'. + created $dff cell `$procdff$15782' with positive edge clock. +Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15729_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731'. + created $dff cell `$procdff$15783' with positive edge clock. + +2.47.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +2.47.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'. +Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731'. +Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731'. +Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15730'. +Cleaned up 1 empty switch. + +2.47.4. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module neural_director. +Found 0 SCCs. + +2.47.5. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.6. Executing TECHMAP pass (map to technology primitives). + +2.47.6.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +2.47.6.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.47.7. Executing OPT pass (performing simple optimizations). + +2.47.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. + +2.47.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Removed a total of 0 cells. + +2.47.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +2.47.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. +Performed a total of 0 changes. + +2.47.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Removed a total of 0 cells. + +2.47.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.47.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. + +2.47.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. + +2.47.7.9. Finished fast OPT passes. (There is nothing left to do.) + +2.47.8. Executing TECHMAP pass (map to technology primitives). + +2.47.8.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +2.47.8.2. Continuing TECHMAP pass. +Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. +No more expansions possible. + + +2.47.9. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +2.47.10. Executing ABC9_OPS pass (helper functions for ABC9). + + +2.47.11. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.12. Executing ABC9_OPS pass (helper functions for ABC9). + + +2.47.13. Executing TECHMAP pass (map to technology primitives). + +2.47.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +2.47.13.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $xor. +Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. +Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +2.47.14. Executing OPT pass (performing simple optimizations). + +2.47.14.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + + +2.47.14.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 59 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Computing hashes of 57 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. + +Removed a total of 2 cells. + +2.47.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \neural_director.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +2.47.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \neural_director. +Performed a total of 0 changes. + +2.47.14.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 57 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.47.14.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.47.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. +Removed 0 unused cells and 55 unused wires. + + +2.47.14.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.47.14.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.47.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \neural_director.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +2.47.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \neural_director. +Performed a total of 0 changes. + +2.47.14.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\neural_director'. +Computing hashes of 57 cells of `\neural_director'. +Finding duplicate cells in `\neural_director'. +Removed a total of 0 cells. + +2.47.14.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.47.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \neural_director.. + +2.47.14.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module neural_director. + +2.47.14.16. Finished fast OPT passes. (There is nothing left to do.) + +2.47.15. Executing AIGMAP pass (map logic to AIG). +Module neural_director: replaced 18 cells with 120 new cells, skipped 39 cells. + replaced 3 cell types: + 14 $_MUX_ + 2 $_OR_ + 2 $_XOR_ + not replaced 3 cell types: + 4 $_AND_ + 4 $_NOT_ + 31 $specify2 + +2.47.16. Executing AIGMAP pass (map logic to AIG). +Module neural_director: replaced 3014 cells with 19910 new cells, skipped 983 cells. + replaced 3 cell types: + 2582 $_MUX_ + 396 $_OR_ + 36 $_XOR_ + not replaced 6 cell types: + 360 $_AND_ + 192 $_NOT_ + 366 TRELLIS_FF + 21 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C + 22 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 + 22 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp + +2.47.16.1. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.16.2. Executing ABC9_OPS pass (helper functions for ABC9). + +2.47.16.3. Executing XAIGER backend. + +Extracted 8610 AND gates and 21546 wires from module `neural_director' to a netlist network with 562 inputs and 731 outputs. + +2.47.16.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +2.47.16.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 562/ 731 and = 5580 lev = 41 (6.22) mem = 0.09 MB box = 43 bb = 22 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 562/ 731 and = 1730 lev = 11 (1.93) mem = 0.05 MB ch = 181 box = 26 bb = 22 +ABC: cst = 0 cls = 180 lit = 181 unused = 2031 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 1730. Ch = 180. Total mem = 0.55 MB. Peak cut mem = 0.07 MB. +ABC: P: Del = 1991.00. Ar = 751.0. Edge = 2007. Cut = 18688. T = 0.00 sec +ABC: P: Del = 1991.00. Ar = 749.0. Edge = 2005. Cut = 18688. T = 0.00 sec +ABC: P: Del = 1991.00. Ar = 637.0. Edge = 1735. Cut = 21114. T = 0.00 sec +ABC: F: Del = 1991.00. Ar = 634.0. Edge = 1728. Cut = 10809. T = 0.00 sec +ABC: A: Del = 1991.00. Ar = 634.0. Edge = 1723. Cut = 10810. T = 0.00 sec +ABC: A: Del = 1991.00. Ar = 634.0. Edge = 1723. Cut = 10810. T = 0.00 sec +ABC: Total time = 0.01 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: + &ps -l +ABC: /input : i/o = 562/ 731 and = 1663 lev = 10 (1.92) mem = 0.04 MB box = 26 bb = 22 +ABC: Mapping (K=6) : lut = 373 edge = 1382 lev = 3 (0.69) levB = 5 mem = 0.02 MB +ABC: LUT = 373 : 2=12 3.2 % 3=90 24.1 % 4=268 71.8 % 5=2 0.5 % 6=1 0.3 % Ave = 3.71 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.02 sec +ABC: + time +ABC: elapse: 0.08 seconds, total: 0.08 seconds + +2.47.16.6. Executing AIGER frontend. + +Removed 2657 unused cells and 3904 unused wires. + +2.47.16.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 377 +ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 4 +ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 22 +ABC RESULTS: input signals: 34 +ABC RESULTS: output signals: 32 + +Removing temp directory. + +2.47.17. Executing TECHMAP pass (map to technology primitives). + +2.47.17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +2.47.17.2. Continuing TECHMAP pass. +Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. +No more expansions possible. + +Removed 100 unused cells and 22029 unused wires. + +2.48. Executing TECHMAP pass (map to technology primitives). + +2.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +2.48.2. Continuing TECHMAP pass. +Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f$lut for cells of type $lut. +Using template $paramod$aff3a645bb9f572421a4f0f49cf8987ceb4bcdc5$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. +Using template $paramod$d5841602ab17202e972b290147d14b63f75b0ad1$lut for cells of type $lut. +Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut. +Using template $paramod$849d013d096d73269ca4beb768f8e399745d37f2$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. +Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. +Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. +Using template $paramod$351521e8b01efeb144a39a20c4d973eb0b1643fa$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. +Using template $paramod$2aa2400b636d1f2542340d9a48d35a61ec4f2ceb$lut for cells of type $lut. +Using template $paramod$00e6eb1056d6deeea8a8d38a65ef2ad861705f32$lut for cells of type $lut. +Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. +Using template $paramod$cc08dba3aac8677e797984bdf18a09dd37547dd3$lut for cells of type $lut. +Using template $paramod$2b82ba3dc458afbd78c9b79c233a51eb64b085d6$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$fccccf8bb2add7667329c686feec7546eb9a3ae3$lut for cells of type $lut. +Using template $paramod$d6fad69df4b6793100fda03bb83504fe9b335c70$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. +Using template $paramod$cd6c4b4da6d8737b72fd2dc8f5d83d8967445809$lut for cells of type $lut. +Using template $paramod$f70269f202d4dce0365aebaed07094a4216142a8$lut for cells of type $lut. +Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6$lut for cells of type $lut. +Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. +No more expansions possible. + + +2.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in neural_director. + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$56074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$56074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$56076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$56077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) +Removed 0 unused cells and 756 unused wires. + +2.50. Executing AUTONAME pass. +Renamed 890 objects in module neural_director. + + +2.51. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `neural_director'. Setting top module to neural_director. + +2.51.1. Analyzing design hierarchy.. +Top module: \neural_director + +2.51.2. Analyzing design hierarchy.. +Top module: \neural_director +Removed 0 unused modules. + +2.52. Printing statistics. + +=== neural_director === + + +----------Local Count, excluding submodules. + | + 159 wires + 1318 wire bits + 159 public wires + 1318 public wire bits + 19 ports + 461 port bits + 779 submodules + 4 CCU2C + 1 L6MUX21 + 382 LUT4 + 4 PFUMX + 22 TRELLIS_DPR16X4 + 366 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + - neural_director + + +----------Count including submodules. + | + 159 wires + 1318 wire bits + 159 public wires + 1318 public wire bits + 19 ports + 461 port bits + - memories + - memory bits + - processes + - cells + 779 submodules + 4 CCU2C + 1 L6MUX21 + 382 LUT4 + 4 PFUMX + 22 TRELLIS_DPR16X4 + 366 TRELLIS_FF + +2.53. Executing CHECK pass (checking for obvious problems). +Checking module neural_director... +Found and reported 0 problems. + +2.54. Executing JSON backend. + +End of script. Logfile hash: b9afbe9818, time: 0.66s, user: 0.58s, system: 0.03s, MEM: 75.19 MB peak +Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) +Time spent: 25% 21x read_verilog (0 sec), 13% 1x abc9_exe (0 sec), ...