micheleandClaude Sonnet 5
2e4cedc761
Implements M5: neural_director.v dispatches job descriptors to whichever of N_SLOTS (memory_manager, neural_processor) pairs is currently free (first-free scheduling per §9's initial policy), with a parametric-depth ready-queue FIFO for jobs arriving faster than slots can absorb them. Scope for this milestone (see decisions.log DEC-0007): a reduced 4-state FSM (DIR_IDLE/SCAN_READY/ALLOCATE/ERROR) rather than §9's full 8-state baseline -- dependency tracking, the waiting queue, and wake-up are §10's explicit responsibility (Dependency Manager, M6, not yet built), and slot-completion detection runs as an always-active per-slot tracker rather than a dedicated FSM state, for the same reason DEC-0002 already gave for the Neural Processor's own FSM (gating concurrent per-unit progress behind one shared state kills throughput). Verified with Verilator (N_SLOTS=2, each slot backed by its own independent behavioral memory rather than sharing V1's real PSRAM -- M4 already proved that path for one slot; this milestone's own concern is scheduling across multiple slots): 4/4 tests pass -- 3 jobs submitted to 2 slots (first two dispatch immediately, third correctly queues until a slot frees), and a deliberate burst that forces the ready queue to genuinely fill and recover. Real synthesis: 0 CHECK problems, 382 LUT4/366 FF/4 CCU2C/0 DSP. Real place&route (via a synthesis-only timing harness, same TRELLIS_IO pin-budget reason as M2/M4): Fmax 250.50 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2.9 KiB
2.9 KiB
FPGA-Neural V2 — stato roadmap
Fonte del mandato: docs/v2-description.md (root del repository). Baseline
funzionale/numerica/bit-exact: hardware/v1/ (frozen, sola lettura — vedi
hardware/v1/README.md).
Legenda: [ ] non iniziato · [~] in corso · [x] completo (sim+synth+timing
reali, non solo scritto).
- M1 — Neural Processor (
hardware/v2/rtl/neural_processor.v, P8). Bit-exact vs V1 (7/7 test, Verilator), pipeline a 8 stadi funzionante, throughput reale (1 tile/ciclo). Sintesi reale: 0 problemi CHECK, Fmax 183.12 MHz (ACC_WIDTH=32) — vedilogs/experiments.logEXP-0001/EXP-0002,logs/errors.logper 3 bug reali trovati e risolti (2 del toolchain Icarus, 1 RTL). - M2 — Processor Array (
neural_processor_array.v). 1/2/4/8 processor testati (sim concorrenza reale + sintesi/P&R reali). Fmax sempre PASS a 80MHz (159.11→134.70 MHz). Scoperta: il DSP (MULT18X18D), non LUT/FF, satura per primo (88% a N=8) — vedilogs/decisions.logDEC-0005. - M3 — Buffers (
activation_buffer.v,weight_buffer.v,result_buffer.v). Tutti inferiscono DP16KD reale (10/10 test, 6/6 config sintetizzate 0 problemi). Scoperta: il costo BRAM di weight_buffer e' guidato da P_IN (larghezza), non da DEPTH. - M4 — Memory Manager (
memory_manager.v,prefetch_engine.v), backend PSRAM V1 riusato SENZA MODIFICHE. End-to-end reale (3/3 job PASS) con vero neural_processor + vera catena PSRAM V1. 3 bug RTL trovati/risolti (logs/errors.logERR-0006). Fmax 165.86 MHz. - M5 — Neural Director (
neural_director.v), scheduling first-free. 4/4 test PASS (dispatch + coda + backpressure reale su N_SLOTS=2). FSM ridotta a 4 stati, dependency rimandata a M6 (logs/decisions.logDEC-0007). Fmax 250.50 MHz. - M6 — Dependency Manager (
dependency_manager.v), ready/waiting queue, dependency counters, wake-up, producer tracking. - M7 — Dataflow Core (
dataflow_core.v), integrazione completa. - M8 — PSRAM integration, controller V1 non modificato, misura reale.
- M9 — Full benchmark, tabella V1 vs V2 (§32 del mandato).
- M10 — Optimization, solo sulla base dei dati raccolti in M1-M9.
Log
Vedi hardware/v2/logs/ (development.log per la cronologia di sessione,
decisions.log per le decisioni architetturali con motivazione,
experiments.log per ogni EXP-XXXX end-to-end).
Regole non negoziabili attive (§34 del mandato, per riferimento rapido)
- V1 (
hardware/v1/) rimane intatta — mai modificata. - V2 vive esclusivamente sotto
hardware/v2/. - Nessun risultato inventato: THEORETICAL vs SIMULATED vs SYNTHESIZED vs POST-P&R sempre etichettati esplicitamente.
- Ogni modifica/esperimento/decisione registrata nei log, mai persa.
- Ogni esperimento ha un ID univoco, mai riutilizzato — anche i FAIL restano.