exp: N=16 timing closure fixed (EXP-0056), weight-reuse gives real 7.16x memory speedup without DDR3 (EXP-0057)

EXP-0056: N_SLOTS=16 failed timing on LFE5U-85F (23-24MHz vs 64MHz
target). First hypothesis (dependency_manager.v's serial ready-scan)
was wrong but real -- built and verified priority_encoder_lsb.v (a
generic recursive tree encoder) and dependency_manager_fast.v, bit-
exact equivalent to the original, but integrated it made no real
difference (24.26MHz). The real cause, found from nextpnr's own
critical-path report: nms_activation_fill_ctrl_v3.v's balanced max-
tree was only ever extended to N_SLOTS in {1,2,4,8}, silently falling
back to the original slow scan for 16. Added the missing case
(nms_activation_fill_ctrl_v3_n16.v), verified isolated (10017/10017)
and functionally (D-Stress N=16 still 256/256 bit-exact). Real result:
71.01MHz, PASS at 64MHz (single seed so far).

EXP-0057: built layer_weight_buffer.v, a double-buffered per-layer
weight scratchpad (fill one buffer in the background from SDRAM while
compute reads many times from the other -- weight-stationary reuse,
as opposed to D-Stress's own deliberately zero-reuse pattern). Wired
to the real sdram_controller_openrow.v + sdram_model.v, no new
hardware. For the same 32768 bytes of useful data: zero-reuse costs
27048 real cycles, reuse costs 3777 -- 7.16x real measured speedup on
the SAME SDR SDRAM, no DDR3, no clock change. This is the answer to
whether DDR3 is necessary for a workload class that actually has
reuse (e.g. conv-style face recognition, unlike D-Stress) -- it isn't,
at least not for this reason.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
2026-09-16 12:01:11 +02:00
co-authored by Claude Sonnet 5
parent fce8ff2d66
commit 1ce78dff6e
25 changed files with 25848 additions and 0 deletions
@@ -0,0 +1,15 @@
device: "LFE5U-85F-8BG381C"
cpu: "None"
memtype: "DDR3"
sdram_phy: "ECP5DDRPHY"
sdram_module: "MT41K256M16"
sdram_module_nb: 2
sdram_rank_nb: 1
input_clk_freq: 16e6
sys_clk_freq: 75e6
init_clk_freq: 25e6
cmd_latency: 0
speedgrade: -8
user_ports:
native_0:
type: "native"
@@ -0,0 +1,279 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (9ad3ecf74) on 2026-09-16 08:16:18
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
// CSR Includes.
//--------------------------------------------------------------------------------
#include <generated/soc.h>
#ifndef __GENERATED_CSR_H
#define __GENERATED_CSR_H
#include <stdint.h>
#include <system.h>
#ifndef CSR_ACCESSORS_DEFINED
#include <hw/common.h>
#endif /* ! CSR_ACCESSORS_DEFINED */
#ifndef CSR_BASE
#define CSR_BASE 0x0L
#endif /* ! CSR_BASE */
//--------------------------------------------------------------------------------
// CSR Registers/Fields Definition.
//--------------------------------------------------------------------------------
/* DDRCTRL Registers */
#define CSR_DDRCTRL_BASE (CSR_BASE + 0x0L)
#define CSR_DDRCTRL_INIT_DONE_ADDR (CSR_BASE + 0x0L)
#define CSR_DDRCTRL_INIT_DONE_SIZE 1
#define CSR_DDRCTRL_INIT_ERROR_ADDR (CSR_BASE + 0x4L)
#define CSR_DDRCTRL_INIT_ERROR_SIZE 1
/* DDRCTRL Fields */
/* DDRPHY Registers */
#define CSR_DDRPHY_BASE (CSR_BASE + 0x800L)
#define CSR_DDRPHY_DLY_SEL_ADDR (CSR_BASE + 0x800L)
#define CSR_DDRPHY_DLY_SEL_SIZE 1
#define CSR_DDRPHY_RDLY_DQ_RST_ADDR (CSR_BASE + 0x804L)
#define CSR_DDRPHY_RDLY_DQ_RST_SIZE 1
#define CSR_DDRPHY_RDLY_DQ_INC_ADDR (CSR_BASE + 0x808L)
#define CSR_DDRPHY_RDLY_DQ_INC_SIZE 1
#define CSR_DDRPHY_RDLY_DQ_BITSLIP_RST_ADDR (CSR_BASE + 0x80cL)
#define CSR_DDRPHY_RDLY_DQ_BITSLIP_RST_SIZE 1
#define CSR_DDRPHY_RDLY_DQ_BITSLIP_ADDR (CSR_BASE + 0x810L)
#define CSR_DDRPHY_RDLY_DQ_BITSLIP_SIZE 1
#define CSR_DDRPHY_BURSTDET_CLR_ADDR (CSR_BASE + 0x814L)
#define CSR_DDRPHY_BURSTDET_CLR_SIZE 1
#define CSR_DDRPHY_BURSTDET_SEEN_ADDR (CSR_BASE + 0x818L)
#define CSR_DDRPHY_BURSTDET_SEEN_SIZE 1
/* DDRPHY Fields */
/* SDRAM Registers */
#define CSR_SDRAM_BASE (CSR_BASE + 0x1000L)
#define CSR_SDRAM_DFII_CONTROL_ADDR (CSR_BASE + 0x1000L)
#define CSR_SDRAM_DFII_CONTROL_SIZE 1
#define CSR_SDRAM_DFII_PI0_COMMAND_ADDR (CSR_BASE + 0x1004L)
#define CSR_SDRAM_DFII_PI0_COMMAND_SIZE 1
#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_ADDR (CSR_BASE + 0x1008L)
#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_SIZE 1
#define CSR_SDRAM_DFII_PI0_ADDRESS_ADDR (CSR_BASE + 0x100cL)
#define CSR_SDRAM_DFII_PI0_ADDRESS_SIZE 1
#define CSR_SDRAM_DFII_PI0_BADDRESS_ADDR (CSR_BASE + 0x1010L)
#define CSR_SDRAM_DFII_PI0_BADDRESS_SIZE 1
#define CSR_SDRAM_DFII_PI0_WRDATA_ADDR (CSR_BASE + 0x1014L)
#define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 2
#define CSR_SDRAM_DFII_PI0_RDDATA_ADDR (CSR_BASE + 0x101cL)
#define CSR_SDRAM_DFII_PI0_RDDATA_SIZE 2
#define CSR_SDRAM_DFII_PI1_COMMAND_ADDR (CSR_BASE + 0x1024L)
#define CSR_SDRAM_DFII_PI1_COMMAND_SIZE 1
#define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_ADDR (CSR_BASE + 0x1028L)
#define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_SIZE 1
#define CSR_SDRAM_DFII_PI1_ADDRESS_ADDR (CSR_BASE + 0x102cL)
#define CSR_SDRAM_DFII_PI1_ADDRESS_SIZE 1
#define CSR_SDRAM_DFII_PI1_BADDRESS_ADDR (CSR_BASE + 0x1030L)
#define CSR_SDRAM_DFII_PI1_BADDRESS_SIZE 1
#define CSR_SDRAM_DFII_PI1_WRDATA_ADDR (CSR_BASE + 0x1034L)
#define CSR_SDRAM_DFII_PI1_WRDATA_SIZE 2
#define CSR_SDRAM_DFII_PI1_RDDATA_ADDR (CSR_BASE + 0x103cL)
#define CSR_SDRAM_DFII_PI1_RDDATA_SIZE 2
/* SDRAM Fields */
#define CSR_SDRAM_DFII_CONTROL_SEL_OFFSET 0
#define CSR_SDRAM_DFII_CONTROL_SEL_SIZE 1
#define CSR_SDRAM_DFII_CONTROL_CKE_OFFSET 1
#define CSR_SDRAM_DFII_CONTROL_CKE_SIZE 1
#define CSR_SDRAM_DFII_CONTROL_ODT_OFFSET 2
#define CSR_SDRAM_DFII_CONTROL_ODT_SIZE 1
#define CSR_SDRAM_DFII_CONTROL_RESET_N_OFFSET 3
#define CSR_SDRAM_DFII_CONTROL_RESET_N_SIZE 1
#define CSR_SDRAM_DFII_PI0_COMMAND_CS_OFFSET 0
#define CSR_SDRAM_DFII_PI0_COMMAND_CS_SIZE 1
#define CSR_SDRAM_DFII_PI0_COMMAND_WE_OFFSET 1
#define CSR_SDRAM_DFII_PI0_COMMAND_WE_SIZE 1
#define CSR_SDRAM_DFII_PI0_COMMAND_CAS_OFFSET 2
#define CSR_SDRAM_DFII_PI0_COMMAND_CAS_SIZE 1
#define CSR_SDRAM_DFII_PI0_COMMAND_RAS_OFFSET 3
#define CSR_SDRAM_DFII_PI0_COMMAND_RAS_SIZE 1
#define CSR_SDRAM_DFII_PI0_COMMAND_WREN_OFFSET 4
#define CSR_SDRAM_DFII_PI0_COMMAND_WREN_SIZE 1
#define CSR_SDRAM_DFII_PI0_COMMAND_RDEN_OFFSET 5
#define CSR_SDRAM_DFII_PI0_COMMAND_RDEN_SIZE 1
#define CSR_SDRAM_DFII_PI0_COMMAND_CS_TOP_OFFSET 6
#define CSR_SDRAM_DFII_PI0_COMMAND_CS_TOP_SIZE 1
#define CSR_SDRAM_DFII_PI0_COMMAND_CS_BOTTOM_OFFSET 7
#define CSR_SDRAM_DFII_PI0_COMMAND_CS_BOTTOM_SIZE 1
#define CSR_SDRAM_DFII_PI1_COMMAND_CS_OFFSET 0
#define CSR_SDRAM_DFII_PI1_COMMAND_CS_SIZE 1
#define CSR_SDRAM_DFII_PI1_COMMAND_WE_OFFSET 1
#define CSR_SDRAM_DFII_PI1_COMMAND_WE_SIZE 1
#define CSR_SDRAM_DFII_PI1_COMMAND_CAS_OFFSET 2
#define CSR_SDRAM_DFII_PI1_COMMAND_CAS_SIZE 1
#define CSR_SDRAM_DFII_PI1_COMMAND_RAS_OFFSET 3
#define CSR_SDRAM_DFII_PI1_COMMAND_RAS_SIZE 1
#define CSR_SDRAM_DFII_PI1_COMMAND_WREN_OFFSET 4
#define CSR_SDRAM_DFII_PI1_COMMAND_WREN_SIZE 1
#define CSR_SDRAM_DFII_PI1_COMMAND_RDEN_OFFSET 5
#define CSR_SDRAM_DFII_PI1_COMMAND_RDEN_SIZE 1
#define CSR_SDRAM_DFII_PI1_COMMAND_CS_TOP_OFFSET 6
#define CSR_SDRAM_DFII_PI1_COMMAND_CS_TOP_SIZE 1
#define CSR_SDRAM_DFII_PI1_COMMAND_CS_BOTTOM_OFFSET 7
#define CSR_SDRAM_DFII_PI1_COMMAND_CS_BOTTOM_SIZE 1
//--------------------------------------------------------------------------------
// CSR Registers Access Functions.
//--------------------------------------------------------------------------------
#ifndef LITEX_CSR_ACCESS_FUNCTIONS
#define LITEX_CSR_ACCESS_FUNCTIONS 1
#endif
#if LITEX_CSR_ACCESS_FUNCTIONS
/* DDRCTRL Access Functions */
static inline uint32_t ddrctrl_init_done_read(void) {
return csr_read_simple((CSR_BASE + 0x0L));
}
static inline void ddrctrl_init_done_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x0L));
}
static inline uint32_t ddrctrl_init_error_read(void) {
return csr_read_simple((CSR_BASE + 0x4L));
}
static inline void ddrctrl_init_error_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x4L));
}
/* DDRPHY Access Functions */
static inline uint32_t ddrphy_dly_sel_read(void) {
return csr_read_simple((CSR_BASE + 0x800L));
}
static inline void ddrphy_dly_sel_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x800L));
}
static inline uint32_t ddrphy_rdly_dq_rst_read(void) {
return csr_read_simple((CSR_BASE + 0x804L));
}
static inline void ddrphy_rdly_dq_rst_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x804L));
}
static inline uint32_t ddrphy_rdly_dq_inc_read(void) {
return csr_read_simple((CSR_BASE + 0x808L));
}
static inline void ddrphy_rdly_dq_inc_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x808L));
}
static inline uint32_t ddrphy_rdly_dq_bitslip_rst_read(void) {
return csr_read_simple((CSR_BASE + 0x80cL));
}
static inline void ddrphy_rdly_dq_bitslip_rst_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x80cL));
}
static inline uint32_t ddrphy_rdly_dq_bitslip_read(void) {
return csr_read_simple((CSR_BASE + 0x810L));
}
static inline void ddrphy_rdly_dq_bitslip_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x810L));
}
static inline uint32_t ddrphy_burstdet_clr_read(void) {
return csr_read_simple((CSR_BASE + 0x814L));
}
static inline void ddrphy_burstdet_clr_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x814L));
}
static inline uint32_t ddrphy_burstdet_seen_read(void) {
return csr_read_simple((CSR_BASE + 0x818L));
}
/* SDRAM Access Functions */
static inline uint32_t sdram_dfii_control_read(void) {
return csr_read_simple((CSR_BASE + 0x1000L));
}
static inline void sdram_dfii_control_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x1000L));
}
static inline uint32_t sdram_dfii_pi0_command_read(void) {
return csr_read_simple((CSR_BASE + 0x1004L));
}
static inline void sdram_dfii_pi0_command_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x1004L));
}
static inline uint32_t sdram_dfii_pi0_command_issue_read(void) {
return csr_read_simple((CSR_BASE + 0x1008L));
}
static inline void sdram_dfii_pi0_command_issue_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x1008L));
}
static inline uint32_t sdram_dfii_pi0_address_read(void) {
return csr_read_simple((CSR_BASE + 0x100cL));
}
static inline void sdram_dfii_pi0_address_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x100cL));
}
static inline uint32_t sdram_dfii_pi0_baddress_read(void) {
return csr_read_simple((CSR_BASE + 0x1010L));
}
static inline void sdram_dfii_pi0_baddress_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x1010L));
}
static inline uint64_t sdram_dfii_pi0_wrdata_read(void) {
uint64_t r = csr_read_simple((CSR_BASE + 0x1014L));
r <<= 32;
r |= csr_read_simple((CSR_BASE + 0x1018L));
return r;
}
static inline void sdram_dfii_pi0_wrdata_write(uint64_t v) {
csr_write_simple(v >> 32, (CSR_BASE + 0x1014L));
csr_write_simple(v, (CSR_BASE + 0x1018L));
}
static inline uint64_t sdram_dfii_pi0_rddata_read(void) {
uint64_t r = csr_read_simple((CSR_BASE + 0x101cL));
r <<= 32;
r |= csr_read_simple((CSR_BASE + 0x1020L));
return r;
}
static inline uint32_t sdram_dfii_pi1_command_read(void) {
return csr_read_simple((CSR_BASE + 0x1024L));
}
static inline void sdram_dfii_pi1_command_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x1024L));
}
static inline uint32_t sdram_dfii_pi1_command_issue_read(void) {
return csr_read_simple((CSR_BASE + 0x1028L));
}
static inline void sdram_dfii_pi1_command_issue_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x1028L));
}
static inline uint32_t sdram_dfii_pi1_address_read(void) {
return csr_read_simple((CSR_BASE + 0x102cL));
}
static inline void sdram_dfii_pi1_address_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x102cL));
}
static inline uint32_t sdram_dfii_pi1_baddress_read(void) {
return csr_read_simple((CSR_BASE + 0x1030L));
}
static inline void sdram_dfii_pi1_baddress_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x1030L));
}
static inline uint64_t sdram_dfii_pi1_wrdata_read(void) {
uint64_t r = csr_read_simple((CSR_BASE + 0x1034L));
r <<= 32;
r |= csr_read_simple((CSR_BASE + 0x1038L));
return r;
}
static inline void sdram_dfii_pi1_wrdata_write(uint64_t v) {
csr_write_simple(v >> 32, (CSR_BASE + 0x1034L));
csr_write_simple(v, (CSR_BASE + 0x1038L));
}
static inline uint64_t sdram_dfii_pi1_rddata_read(void) {
uint64_t r = csr_read_simple((CSR_BASE + 0x103cL));
r <<= 32;
r |= csr_read_simple((CSR_BASE + 0x1040L));
return r;
}
#endif /* LITEX_CSR_ACCESS_FUNCTIONS */
#endif /* ! __GENERATED_CSR_H */
@@ -0,0 +1,8 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (9ad3ecf74) on 2026-09-16 08:16:18
//--------------------------------------------------------------------------------
#ifndef __GENERATED_GIT_H
#define __GENERATED_GIT_H
#define LITEX_GIT_SHA1 "9ad3ecf74"
#endif
@@ -0,0 +1,20 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (9ad3ecf74) on 2026-09-16 08:16:18
//--------------------------------------------------------------------------------
#ifndef __GENERATED_MEM_H
#define __GENERATED_MEM_H
#ifndef CSR_BASE
#define CSR_BASE 0x00000000L
#define CSR_BASE_VA 0x00000000L
#define CSR_SIZE 0x00010000
#endif
#ifndef MEM_REGIONS
#define MEM_REGIONS "CSR 0x00000000 0x10000 "
#endif
#ifndef MEM_REGIONS_DETAILS
#define MEM_REGIONS_DETAILS "Region Origin End Size \nCSR 0x00000000 0x0000ffff 0x10000 "
#endif
#endif
@@ -0,0 +1,115 @@
#ifndef __GENERATED_SDRAM_PHY_H
#define __GENERATED_SDRAM_PHY_H
#include <hw/common.h>
#include <generated/csr.h>
#define DFII_CONTROL_SEL 0x01
#define DFII_CONTROL_CKE 0x02
#define DFII_CONTROL_ODT 0x04
#define DFII_CONTROL_RESET_N 0x08
#define DFII_COMMAND_CS 0x01
#define DFII_COMMAND_WE 0x02
#define DFII_COMMAND_CAS 0x04
#define DFII_COMMAND_RAS 0x08
#define DFII_COMMAND_WRDATA 0x10
#define DFII_COMMAND_RDDATA 0x20
#define SDRAM_PHY_ECP5DDRPHY
#define SDRAM_PHY_XDR 2
#define SDRAM_PHY_DATABITS 16
#define SDRAM_PHY_DFI_DATABITS 64
#define SDRAM_PHY_PHASES 2
#define SDRAM_PHY_CL 6
#define SDRAM_PHY_CWL 5
#define SDRAM_PHY_RDPHASE 0
#define SDRAM_PHY_WRPHASE 1
#define SDRAM_PHY_READ_LEVELING_CAPABLE
#define SDRAM_PHY_DQ_DQS_RATIO 8
#define SDRAM_PHY_MODULES 2
#define SDRAM_PHY_DELAYS 8
#define SDRAM_PHY_BITSLIPS 4
#define SDRAM_PHY_DDR3
#define SDRAM_PHY_SUPPORTED_MEMORY 0x0000000020000000ULL
void cdelay(int i);
__attribute__((unused)) static inline void command_p0(int cmd)
{
sdram_dfii_pi0_command_write(cmd);
sdram_dfii_pi0_command_issue_write(1);
}
__attribute__((unused)) static inline void command_p1(int cmd)
{
sdram_dfii_pi1_command_write(cmd);
sdram_dfii_pi1_command_issue_write(1);
}
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase)
{
switch (phase) {
case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR;
case 1: return CSR_SDRAM_DFII_PI1_WRDATA_ADDR;
default: return 0;
}
}
static inline unsigned long sdram_dfii_pix_rddata_addr(int phase)
{
switch (phase) {
case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
case 1: return CSR_SDRAM_DFII_PI1_RDDATA_ADDR;
default: return 0;
}
}
#define DDRX_MR_WRLVL_ADDRESS 1
#define DDRX_MR_WRLVL_RESET 6
#define DDRX_MR_WRLVL_BIT 7
static inline void init_sequence(void)
{
/* Release reset */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(0);
sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
cdelay(50000);
/* Bring CKE high */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(0);
sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
cdelay(10000);
/* Load Mode Register 2, CWL=5 */
sdram_dfii_pi0_address_write(0x200);
sdram_dfii_pi0_baddress_write(2);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 3 */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(3);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 1 */
sdram_dfii_pi0_address_write(0x6);
sdram_dfii_pi0_baddress_write(1);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 0, CL=6, BL=8 */
sdram_dfii_pi0_address_write(0x320);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
/* ZQ Calibration */
sdram_dfii_pi0_address_write(0x400);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
}
#endif /* __GENERATED_SDRAM_PHY_H */
@@ -0,0 +1,55 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (9ad3ecf74) on 2026-09-16 08:16:18
//--------------------------------------------------------------------------------
#ifndef __GENERATED_SOC_H
#define __GENERATED_SOC_H
#include <stdint.h>
#define CONFIG_PLATFORM_NAME "platform"
#define CONFIG_CLOCK_FREQUENCY 75000000
#define CONFIG_CPU_TYPE_NONE
#define CONFIG_CPU_VARIANT_STANDARD
#define CONFIG_CPU_FAMILY
#define CONFIG_CPU_NAME "None"
#define CONFIG_CPU_HUMAN_NAME "Unknown"
#define CONFIG_CSR_DATA_WIDTH 32
#define CONFIG_CSR_ALIGNMENT 32
#define CONFIG_CSR_ORDERING_BIG
#define CONFIG_BUS_STANDARD "wishbone"
#define CONFIG_BUS_DATA_WIDTH 32
#define CONFIG_BUS_ADDRESS_WIDTH 32
#define CONFIG_BUS_BURSTING 0
#ifndef __ASSEMBLER__
static inline const char * config_platform_name_read(void) {
return "platform";
}
static inline uint32_t config_clock_frequency_read(void) {
return 75000000;
}
static inline const char * config_cpu_name_read(void) {
return "None";
}
static inline const char * config_cpu_human_name_read(void) {
return "Unknown";
}
static inline uint32_t config_csr_data_width_read(void) {
return 32;
}
static inline uint32_t config_csr_alignment_read(void) {
return 32;
}
static inline const char * config_bus_standard_read(void) {
return "wishbone";
}
static inline uint32_t config_bus_data_width_read(void) {
return 32;
}
static inline uint32_t config_bus_address_width_read(void) {
return 32;
}
static inline uint32_t config_bus_bursting_read(void) {
return 0;
}
#endif // !__ASSEMBLER__
#endif
@@ -0,0 +1,470 @@
BLOCK RESETPATHS;
BLOCK ASYNCPATHS;
LOCATE COMP "clk" SITE "X";
LOCATE COMP "rst" SITE "X";
LOCATE COMP "pll_locked" SITE "X";
LOCATE COMP "ddram_a[0]" SITE "X";
LOCATE COMP "ddram_a[1]" SITE "X";
LOCATE COMP "ddram_a[2]" SITE "X";
LOCATE COMP "ddram_a[3]" SITE "X";
LOCATE COMP "ddram_a[4]" SITE "X";
LOCATE COMP "ddram_a[5]" SITE "X";
LOCATE COMP "ddram_a[6]" SITE "X";
LOCATE COMP "ddram_a[7]" SITE "X";
LOCATE COMP "ddram_a[8]" SITE "X";
LOCATE COMP "ddram_a[9]" SITE "X";
LOCATE COMP "ddram_a[10]" SITE "X";
LOCATE COMP "ddram_a[11]" SITE "X";
LOCATE COMP "ddram_a[12]" SITE "X";
LOCATE COMP "ddram_a[13]" SITE "X";
LOCATE COMP "ddram_a[14]" SITE "X";
LOCATE COMP "ddram_ba[0]" SITE "X";
LOCATE COMP "ddram_ba[1]" SITE "X";
LOCATE COMP "ddram_ba[2]" SITE "X";
LOCATE COMP "ddram_ras_n" SITE "X";
LOCATE COMP "ddram_cas_n" SITE "X";
LOCATE COMP "ddram_we_n" SITE "X";
LOCATE COMP "ddram_cs_n" SITE "X";
LOCATE COMP "ddram_dm[0]" SITE "X";
LOCATE COMP "ddram_dm[1]" SITE "X";
LOCATE COMP "ddram_dq[0]" SITE "X";
LOCATE COMP "ddram_dq[1]" SITE "X";
LOCATE COMP "ddram_dq[2]" SITE "X";
LOCATE COMP "ddram_dq[3]" SITE "X";
LOCATE COMP "ddram_dq[4]" SITE "X";
LOCATE COMP "ddram_dq[5]" SITE "X";
LOCATE COMP "ddram_dq[6]" SITE "X";
LOCATE COMP "ddram_dq[7]" SITE "X";
LOCATE COMP "ddram_dq[8]" SITE "X";
LOCATE COMP "ddram_dq[9]" SITE "X";
LOCATE COMP "ddram_dq[10]" SITE "X";
LOCATE COMP "ddram_dq[11]" SITE "X";
LOCATE COMP "ddram_dq[12]" SITE "X";
LOCATE COMP "ddram_dq[13]" SITE "X";
LOCATE COMP "ddram_dq[14]" SITE "X";
LOCATE COMP "ddram_dq[15]" SITE "X";
LOCATE COMP "ddram_dqs_p[0]" SITE "X";
LOCATE COMP "ddram_dqs_p[1]" SITE "X";
LOCATE COMP "ddram_dqs_n[0]" SITE "X";
LOCATE COMP "ddram_dqs_n[1]" SITE "X";
LOCATE COMP "ddram_clk_p" SITE "X";
LOCATE COMP "ddram_clk_n" SITE "X";
LOCATE COMP "ddram_cke" SITE "X";
LOCATE COMP "ddram_odt" SITE "X";
LOCATE COMP "ddram_reset_n" SITE "X";
LOCATE COMP "init_done" SITE "X";
LOCATE COMP "init_error" SITE "X";
LOCATE COMP "wb_ctrl_adr[0]" SITE "X";
LOCATE COMP "wb_ctrl_adr[1]" SITE "X";
LOCATE COMP "wb_ctrl_adr[2]" SITE "X";
LOCATE COMP "wb_ctrl_adr[3]" SITE "X";
LOCATE COMP "wb_ctrl_adr[4]" SITE "X";
LOCATE COMP "wb_ctrl_adr[5]" SITE "X";
LOCATE COMP "wb_ctrl_adr[6]" SITE "X";
LOCATE COMP "wb_ctrl_adr[7]" SITE "X";
LOCATE COMP "wb_ctrl_adr[8]" SITE "X";
LOCATE COMP "wb_ctrl_adr[9]" SITE "X";
LOCATE COMP "wb_ctrl_adr[10]" SITE "X";
LOCATE COMP "wb_ctrl_adr[11]" SITE "X";
LOCATE COMP "wb_ctrl_adr[12]" SITE "X";
LOCATE COMP "wb_ctrl_adr[13]" SITE "X";
LOCATE COMP "wb_ctrl_adr[14]" SITE "X";
LOCATE COMP "wb_ctrl_adr[15]" SITE "X";
LOCATE COMP "wb_ctrl_adr[16]" SITE "X";
LOCATE COMP "wb_ctrl_adr[17]" SITE "X";
LOCATE COMP "wb_ctrl_adr[18]" SITE "X";
LOCATE COMP "wb_ctrl_adr[19]" SITE "X";
LOCATE COMP "wb_ctrl_adr[20]" SITE "X";
LOCATE COMP "wb_ctrl_adr[21]" SITE "X";
LOCATE COMP "wb_ctrl_adr[22]" SITE "X";
LOCATE COMP "wb_ctrl_adr[23]" SITE "X";
LOCATE COMP "wb_ctrl_adr[24]" SITE "X";
LOCATE COMP "wb_ctrl_adr[25]" SITE "X";
LOCATE COMP "wb_ctrl_adr[26]" SITE "X";
LOCATE COMP "wb_ctrl_adr[27]" SITE "X";
LOCATE COMP "wb_ctrl_adr[28]" SITE "X";
LOCATE COMP "wb_ctrl_adr[29]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[0]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[1]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[2]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[3]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[4]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[5]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[6]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[7]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[8]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[9]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[10]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[11]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[12]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[13]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[14]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[15]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[16]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[17]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[18]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[19]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[20]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[21]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[22]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[23]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[24]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[25]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[26]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[27]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[28]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[29]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[30]" SITE "X";
LOCATE COMP "wb_ctrl_dat_w[31]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[0]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[1]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[2]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[3]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[4]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[5]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[6]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[7]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[8]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[9]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[10]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[11]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[12]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[13]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[14]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[15]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[16]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[17]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[18]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[19]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[20]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[21]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[22]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[23]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[24]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[25]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[26]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[27]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[28]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[29]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[30]" SITE "X";
LOCATE COMP "wb_ctrl_dat_r[31]" SITE "X";
LOCATE COMP "wb_ctrl_sel[0]" SITE "X";
LOCATE COMP "wb_ctrl_sel[1]" SITE "X";
LOCATE COMP "wb_ctrl_sel[2]" SITE "X";
LOCATE COMP "wb_ctrl_sel[3]" SITE "X";
LOCATE COMP "wb_ctrl_cyc" SITE "X";
LOCATE COMP "wb_ctrl_stb" SITE "X";
LOCATE COMP "wb_ctrl_ack" SITE "X";
LOCATE COMP "wb_ctrl_we" SITE "X";
LOCATE COMP "wb_ctrl_cti[0]" SITE "X";
LOCATE COMP "wb_ctrl_cti[1]" SITE "X";
LOCATE COMP "wb_ctrl_cti[2]" SITE "X";
LOCATE COMP "wb_ctrl_bte[0]" SITE "X";
LOCATE COMP "wb_ctrl_bte[1]" SITE "X";
LOCATE COMP "wb_ctrl_err" SITE "X";
LOCATE COMP "user_clk" SITE "X";
LOCATE COMP "user_rst" SITE "X";
LOCATE COMP "user_port_native_0_cmd_valid" SITE "X";
LOCATE COMP "user_port_native_0_cmd_ready" SITE "X";
LOCATE COMP "user_port_native_0_cmd_we" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[0]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[1]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[2]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[3]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[4]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[5]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[6]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[7]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[8]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[9]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[10]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[11]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[12]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[13]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[14]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[15]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[16]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[17]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[18]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[19]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[20]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[21]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[22]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[23]" SITE "X";
LOCATE COMP "user_port_native_0_cmd_addr[24]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_valid" SITE "X";
LOCATE COMP "user_port_native_0_wdata_ready" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[0]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[1]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[2]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[3]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[4]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[5]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[6]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[7]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[8]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[9]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[10]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[11]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[12]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[13]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[14]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_we[15]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[0]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[1]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[2]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[3]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[4]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[5]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[6]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[7]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[8]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[9]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[10]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[11]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[12]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[13]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[14]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[15]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[16]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[17]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[18]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[19]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[20]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[21]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[22]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[23]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[24]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[25]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[26]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[27]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[28]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[29]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[30]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[31]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[32]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[33]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[34]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[35]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[36]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[37]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[38]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[39]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[40]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[41]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[42]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[43]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[44]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[45]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[46]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[47]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[48]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[49]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[50]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[51]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[52]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[53]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[54]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[55]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[56]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[57]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[58]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[59]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[60]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[61]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[62]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[63]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[64]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[65]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[66]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[67]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[68]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[69]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[70]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[71]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[72]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[73]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[74]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[75]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[76]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[77]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[78]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[79]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[80]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[81]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[82]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[83]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[84]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[85]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[86]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[87]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[88]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[89]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[90]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[91]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[92]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[93]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[94]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[95]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[96]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[97]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[98]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[99]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[100]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[101]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[102]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[103]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[104]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[105]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[106]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[107]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[108]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[109]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[110]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[111]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[112]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[113]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[114]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[115]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[116]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[117]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[118]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[119]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[120]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[121]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[122]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[123]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[124]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[125]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[126]" SITE "X";
LOCATE COMP "user_port_native_0_wdata_data[127]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_valid" SITE "X";
LOCATE COMP "user_port_native_0_rdata_ready" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[0]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[1]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[2]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[3]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[4]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[5]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[6]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[7]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[8]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[9]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[10]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[11]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[12]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[13]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[14]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[15]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[16]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[17]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[18]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[19]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[20]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[21]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[22]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[23]" SITE "X";
LOCATE COMP "user_port_native_0_rdata_data[24]" SITE "X";
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