micheleandClaude Sonnet 5
1ce78dff6e
EXP-0056: N_SLOTS=16 failed timing on LFE5U-85F (23-24MHz vs 64MHz
target). First hypothesis (dependency_manager.v's serial ready-scan)
was wrong but real -- built and verified priority_encoder_lsb.v (a
generic recursive tree encoder) and dependency_manager_fast.v, bit-
exact equivalent to the original, but integrated it made no real
difference (24.26MHz). The real cause, found from nextpnr's own
critical-path report: nms_activation_fill_ctrl_v3.v's balanced max-
tree was only ever extended to N_SLOTS in {1,2,4,8}, silently falling
back to the original slow scan for 16. Added the missing case
(nms_activation_fill_ctrl_v3_n16.v), verified isolated (10017/10017)
and functionally (D-Stress N=16 still 256/256 bit-exact). Real result:
71.01MHz, PASS at 64MHz (single seed so far).
EXP-0057: built layer_weight_buffer.v, a double-buffered per-layer
weight scratchpad (fill one buffer in the background from SDRAM while
compute reads many times from the other -- weight-stationary reuse,
as opposed to D-Stress's own deliberately zero-reuse pattern). Wired
to the real sdram_controller_openrow.v + sdram_model.v, no new
hardware. For the same 32768 bytes of useful data: zero-reuse costs
27048 real cycles, reuse costs 3777 -- 7.16x real measured speedup on
the SAME SDR SDRAM, no DDR3, no clock change. This is the answer to
whether DDR3 is necessary for a workload class that actually has
reuse (e.g. conv-style face recognition, unlike D-Stress) -- it isn't,
at least not for this reason.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
280 lines
10 KiB
C
280 lines
10 KiB
C
//--------------------------------------------------------------------------------
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// Auto-generated by LiteX (9ad3ecf74) on 2026-09-16 08:16:18
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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// CSR Includes.
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//--------------------------------------------------------------------------------
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#include <generated/soc.h>
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#ifndef __GENERATED_CSR_H
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#define __GENERATED_CSR_H
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#include <stdint.h>
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#include <system.h>
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#ifndef CSR_ACCESSORS_DEFINED
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#include <hw/common.h>
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#endif /* ! CSR_ACCESSORS_DEFINED */
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#ifndef CSR_BASE
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#define CSR_BASE 0x0L
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#endif /* ! CSR_BASE */
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//--------------------------------------------------------------------------------
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// CSR Registers/Fields Definition.
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//--------------------------------------------------------------------------------
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/* DDRCTRL Registers */
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#define CSR_DDRCTRL_BASE (CSR_BASE + 0x0L)
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#define CSR_DDRCTRL_INIT_DONE_ADDR (CSR_BASE + 0x0L)
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#define CSR_DDRCTRL_INIT_DONE_SIZE 1
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#define CSR_DDRCTRL_INIT_ERROR_ADDR (CSR_BASE + 0x4L)
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#define CSR_DDRCTRL_INIT_ERROR_SIZE 1
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/* DDRCTRL Fields */
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/* DDRPHY Registers */
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#define CSR_DDRPHY_BASE (CSR_BASE + 0x800L)
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#define CSR_DDRPHY_DLY_SEL_ADDR (CSR_BASE + 0x800L)
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#define CSR_DDRPHY_DLY_SEL_SIZE 1
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#define CSR_DDRPHY_RDLY_DQ_RST_ADDR (CSR_BASE + 0x804L)
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#define CSR_DDRPHY_RDLY_DQ_RST_SIZE 1
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#define CSR_DDRPHY_RDLY_DQ_INC_ADDR (CSR_BASE + 0x808L)
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#define CSR_DDRPHY_RDLY_DQ_INC_SIZE 1
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#define CSR_DDRPHY_RDLY_DQ_BITSLIP_RST_ADDR (CSR_BASE + 0x80cL)
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#define CSR_DDRPHY_RDLY_DQ_BITSLIP_RST_SIZE 1
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#define CSR_DDRPHY_RDLY_DQ_BITSLIP_ADDR (CSR_BASE + 0x810L)
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#define CSR_DDRPHY_RDLY_DQ_BITSLIP_SIZE 1
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#define CSR_DDRPHY_BURSTDET_CLR_ADDR (CSR_BASE + 0x814L)
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#define CSR_DDRPHY_BURSTDET_CLR_SIZE 1
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#define CSR_DDRPHY_BURSTDET_SEEN_ADDR (CSR_BASE + 0x818L)
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#define CSR_DDRPHY_BURSTDET_SEEN_SIZE 1
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/* DDRPHY Fields */
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/* SDRAM Registers */
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#define CSR_SDRAM_BASE (CSR_BASE + 0x1000L)
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#define CSR_SDRAM_DFII_CONTROL_ADDR (CSR_BASE + 0x1000L)
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#define CSR_SDRAM_DFII_CONTROL_SIZE 1
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#define CSR_SDRAM_DFII_PI0_COMMAND_ADDR (CSR_BASE + 0x1004L)
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#define CSR_SDRAM_DFII_PI0_COMMAND_SIZE 1
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#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_ADDR (CSR_BASE + 0x1008L)
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#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_SIZE 1
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#define CSR_SDRAM_DFII_PI0_ADDRESS_ADDR (CSR_BASE + 0x100cL)
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#define CSR_SDRAM_DFII_PI0_ADDRESS_SIZE 1
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#define CSR_SDRAM_DFII_PI0_BADDRESS_ADDR (CSR_BASE + 0x1010L)
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#define CSR_SDRAM_DFII_PI0_BADDRESS_SIZE 1
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#define CSR_SDRAM_DFII_PI0_WRDATA_ADDR (CSR_BASE + 0x1014L)
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#define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 2
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#define CSR_SDRAM_DFII_PI0_RDDATA_ADDR (CSR_BASE + 0x101cL)
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#define CSR_SDRAM_DFII_PI0_RDDATA_SIZE 2
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#define CSR_SDRAM_DFII_PI1_COMMAND_ADDR (CSR_BASE + 0x1024L)
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#define CSR_SDRAM_DFII_PI1_COMMAND_SIZE 1
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#define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_ADDR (CSR_BASE + 0x1028L)
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#define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_SIZE 1
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#define CSR_SDRAM_DFII_PI1_ADDRESS_ADDR (CSR_BASE + 0x102cL)
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#define CSR_SDRAM_DFII_PI1_ADDRESS_SIZE 1
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#define CSR_SDRAM_DFII_PI1_BADDRESS_ADDR (CSR_BASE + 0x1030L)
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#define CSR_SDRAM_DFII_PI1_BADDRESS_SIZE 1
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#define CSR_SDRAM_DFII_PI1_WRDATA_ADDR (CSR_BASE + 0x1034L)
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#define CSR_SDRAM_DFII_PI1_WRDATA_SIZE 2
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#define CSR_SDRAM_DFII_PI1_RDDATA_ADDR (CSR_BASE + 0x103cL)
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#define CSR_SDRAM_DFII_PI1_RDDATA_SIZE 2
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/* SDRAM Fields */
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#define CSR_SDRAM_DFII_CONTROL_SEL_OFFSET 0
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#define CSR_SDRAM_DFII_CONTROL_SEL_SIZE 1
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#define CSR_SDRAM_DFII_CONTROL_CKE_OFFSET 1
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#define CSR_SDRAM_DFII_CONTROL_CKE_SIZE 1
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#define CSR_SDRAM_DFII_CONTROL_ODT_OFFSET 2
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#define CSR_SDRAM_DFII_CONTROL_ODT_SIZE 1
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#define CSR_SDRAM_DFII_CONTROL_RESET_N_OFFSET 3
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#define CSR_SDRAM_DFII_CONTROL_RESET_N_SIZE 1
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#define CSR_SDRAM_DFII_PI0_COMMAND_CS_OFFSET 0
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#define CSR_SDRAM_DFII_PI0_COMMAND_CS_SIZE 1
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#define CSR_SDRAM_DFII_PI0_COMMAND_WE_OFFSET 1
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#define CSR_SDRAM_DFII_PI0_COMMAND_WE_SIZE 1
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#define CSR_SDRAM_DFII_PI0_COMMAND_CAS_OFFSET 2
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#define CSR_SDRAM_DFII_PI0_COMMAND_CAS_SIZE 1
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#define CSR_SDRAM_DFII_PI0_COMMAND_RAS_OFFSET 3
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#define CSR_SDRAM_DFII_PI0_COMMAND_RAS_SIZE 1
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#define CSR_SDRAM_DFII_PI0_COMMAND_WREN_OFFSET 4
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#define CSR_SDRAM_DFII_PI0_COMMAND_WREN_SIZE 1
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#define CSR_SDRAM_DFII_PI0_COMMAND_RDEN_OFFSET 5
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#define CSR_SDRAM_DFII_PI0_COMMAND_RDEN_SIZE 1
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#define CSR_SDRAM_DFII_PI0_COMMAND_CS_TOP_OFFSET 6
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#define CSR_SDRAM_DFII_PI0_COMMAND_CS_TOP_SIZE 1
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#define CSR_SDRAM_DFII_PI0_COMMAND_CS_BOTTOM_OFFSET 7
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#define CSR_SDRAM_DFII_PI0_COMMAND_CS_BOTTOM_SIZE 1
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#define CSR_SDRAM_DFII_PI1_COMMAND_CS_OFFSET 0
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#define CSR_SDRAM_DFII_PI1_COMMAND_CS_SIZE 1
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#define CSR_SDRAM_DFII_PI1_COMMAND_WE_OFFSET 1
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#define CSR_SDRAM_DFII_PI1_COMMAND_WE_SIZE 1
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#define CSR_SDRAM_DFII_PI1_COMMAND_CAS_OFFSET 2
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#define CSR_SDRAM_DFII_PI1_COMMAND_CAS_SIZE 1
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#define CSR_SDRAM_DFII_PI1_COMMAND_RAS_OFFSET 3
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#define CSR_SDRAM_DFII_PI1_COMMAND_RAS_SIZE 1
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#define CSR_SDRAM_DFII_PI1_COMMAND_WREN_OFFSET 4
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#define CSR_SDRAM_DFII_PI1_COMMAND_WREN_SIZE 1
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#define CSR_SDRAM_DFII_PI1_COMMAND_RDEN_OFFSET 5
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#define CSR_SDRAM_DFII_PI1_COMMAND_RDEN_SIZE 1
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#define CSR_SDRAM_DFII_PI1_COMMAND_CS_TOP_OFFSET 6
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#define CSR_SDRAM_DFII_PI1_COMMAND_CS_TOP_SIZE 1
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#define CSR_SDRAM_DFII_PI1_COMMAND_CS_BOTTOM_OFFSET 7
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#define CSR_SDRAM_DFII_PI1_COMMAND_CS_BOTTOM_SIZE 1
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//--------------------------------------------------------------------------------
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// CSR Registers Access Functions.
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//--------------------------------------------------------------------------------
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#ifndef LITEX_CSR_ACCESS_FUNCTIONS
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#define LITEX_CSR_ACCESS_FUNCTIONS 1
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#endif
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#if LITEX_CSR_ACCESS_FUNCTIONS
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/* DDRCTRL Access Functions */
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static inline uint32_t ddrctrl_init_done_read(void) {
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return csr_read_simple((CSR_BASE + 0x0L));
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}
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static inline void ddrctrl_init_done_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x0L));
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}
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static inline uint32_t ddrctrl_init_error_read(void) {
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return csr_read_simple((CSR_BASE + 0x4L));
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}
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static inline void ddrctrl_init_error_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x4L));
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}
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/* DDRPHY Access Functions */
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static inline uint32_t ddrphy_dly_sel_read(void) {
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return csr_read_simple((CSR_BASE + 0x800L));
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}
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static inline void ddrphy_dly_sel_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x800L));
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}
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static inline uint32_t ddrphy_rdly_dq_rst_read(void) {
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return csr_read_simple((CSR_BASE + 0x804L));
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}
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static inline void ddrphy_rdly_dq_rst_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x804L));
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}
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static inline uint32_t ddrphy_rdly_dq_inc_read(void) {
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return csr_read_simple((CSR_BASE + 0x808L));
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}
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static inline void ddrphy_rdly_dq_inc_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x808L));
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}
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static inline uint32_t ddrphy_rdly_dq_bitslip_rst_read(void) {
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return csr_read_simple((CSR_BASE + 0x80cL));
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}
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static inline void ddrphy_rdly_dq_bitslip_rst_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x80cL));
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}
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static inline uint32_t ddrphy_rdly_dq_bitslip_read(void) {
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return csr_read_simple((CSR_BASE + 0x810L));
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}
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static inline void ddrphy_rdly_dq_bitslip_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x810L));
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}
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static inline uint32_t ddrphy_burstdet_clr_read(void) {
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return csr_read_simple((CSR_BASE + 0x814L));
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}
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static inline void ddrphy_burstdet_clr_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x814L));
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}
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static inline uint32_t ddrphy_burstdet_seen_read(void) {
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return csr_read_simple((CSR_BASE + 0x818L));
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}
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/* SDRAM Access Functions */
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static inline uint32_t sdram_dfii_control_read(void) {
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return csr_read_simple((CSR_BASE + 0x1000L));
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}
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static inline void sdram_dfii_control_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x1000L));
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}
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static inline uint32_t sdram_dfii_pi0_command_read(void) {
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return csr_read_simple((CSR_BASE + 0x1004L));
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}
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static inline void sdram_dfii_pi0_command_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x1004L));
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}
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static inline uint32_t sdram_dfii_pi0_command_issue_read(void) {
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return csr_read_simple((CSR_BASE + 0x1008L));
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}
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static inline void sdram_dfii_pi0_command_issue_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x1008L));
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}
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static inline uint32_t sdram_dfii_pi0_address_read(void) {
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return csr_read_simple((CSR_BASE + 0x100cL));
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}
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static inline void sdram_dfii_pi0_address_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x100cL));
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}
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static inline uint32_t sdram_dfii_pi0_baddress_read(void) {
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return csr_read_simple((CSR_BASE + 0x1010L));
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}
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static inline void sdram_dfii_pi0_baddress_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x1010L));
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}
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static inline uint64_t sdram_dfii_pi0_wrdata_read(void) {
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uint64_t r = csr_read_simple((CSR_BASE + 0x1014L));
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r <<= 32;
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r |= csr_read_simple((CSR_BASE + 0x1018L));
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return r;
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}
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static inline void sdram_dfii_pi0_wrdata_write(uint64_t v) {
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csr_write_simple(v >> 32, (CSR_BASE + 0x1014L));
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csr_write_simple(v, (CSR_BASE + 0x1018L));
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}
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static inline uint64_t sdram_dfii_pi0_rddata_read(void) {
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uint64_t r = csr_read_simple((CSR_BASE + 0x101cL));
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r <<= 32;
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r |= csr_read_simple((CSR_BASE + 0x1020L));
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return r;
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}
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static inline uint32_t sdram_dfii_pi1_command_read(void) {
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return csr_read_simple((CSR_BASE + 0x1024L));
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}
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static inline void sdram_dfii_pi1_command_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x1024L));
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}
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static inline uint32_t sdram_dfii_pi1_command_issue_read(void) {
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return csr_read_simple((CSR_BASE + 0x1028L));
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}
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static inline void sdram_dfii_pi1_command_issue_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x1028L));
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}
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static inline uint32_t sdram_dfii_pi1_address_read(void) {
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return csr_read_simple((CSR_BASE + 0x102cL));
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}
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static inline void sdram_dfii_pi1_address_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x102cL));
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}
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static inline uint32_t sdram_dfii_pi1_baddress_read(void) {
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return csr_read_simple((CSR_BASE + 0x1030L));
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}
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static inline void sdram_dfii_pi1_baddress_write(uint32_t v) {
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csr_write_simple(v, (CSR_BASE + 0x1030L));
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}
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static inline uint64_t sdram_dfii_pi1_wrdata_read(void) {
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uint64_t r = csr_read_simple((CSR_BASE + 0x1034L));
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r <<= 32;
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r |= csr_read_simple((CSR_BASE + 0x1038L));
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return r;
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}
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static inline void sdram_dfii_pi1_wrdata_write(uint64_t v) {
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csr_write_simple(v >> 32, (CSR_BASE + 0x1034L));
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csr_write_simple(v, (CSR_BASE + 0x1038L));
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}
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static inline uint64_t sdram_dfii_pi1_rddata_read(void) {
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uint64_t r = csr_read_simple((CSR_BASE + 0x103cL));
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r <<= 32;
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r |= csr_read_simple((CSR_BASE + 0x1040L));
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return r;
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}
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#endif /* LITEX_CSR_ACCESS_FUNCTIONS */
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#endif /* ! __GENERATED_CSR_H */
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